Accelerated Technology (AT), the Embedded Systems Division of Mentor Graphics, announced the Nucleus EDGE software development environment based on the Eclipse open platform standard for the embedded systems industry.

Daya Nadamuni, Principal Analyst at Gartner/Dataquest, is quoted in the Press Release: "Open source development environments such as Eclipse, provide a necessary framework for embedded software tools which allow developers to invoke necessary tools within a unified environment, and to become more productive in the process."

Accelerated Technology says the Nucleus EDGE environment includes a project manager with an editor and builder, a number of different debugging environments, run-mode debug capability, kernel awareness when using an RTOS, and basic execution and memory control.

Again per the Press Release: "The first release of the Nucleus EDGE software is for the ARM7, ARM9 and XScale processor cores on Windows. The Nucleus EDGE software initially supports the ARM GNU, RedHat GNU and ARM RealView C and C++ compilers. MinGW, a compiler for Windows, is also provided for use with the host-based debugging feature, giving basic prototyping of applications on Windows."

AMI Semiconductor (AMIS) and ARM announced that AMIS has selected the ARM architecture for some new programmable automotive electronics. AMIS has licensed two ARM7 family processors, the ARM7TDMI and ARM7TDMI-S microprocessors, to use in developing products that the company says will help improve driver information, in-car entertainment, body electronics and passenger safety.

Per the Press Release: "The new ARM Powered AMIS solutions will help suppliers and manufacturers improve engine control to meet environmental legislation as well as increase car safety and performance via enhanced powertrain electronics. The first ARM technology-based automotive solutions from AMIS are expected to be available in 2006."

Apache Design Solutions announced that Toshiba has, in both their Japan and U.S. facilities, adopted Apache’s full-chip dynamic power integrity tools into their SoC power closure flow.

Tamotsu Hiwatashi, Senior Manager of the Planning Department, System LSI Design Department at System LSI Division 1 of Toshiba, is quoted in the Press Release: "RedHawk-SDL provided us with the ability to analyze dynamic supply noise, including package effects real silicon behavior prior to tapeout. With RedHawk-SDL, we were able to detect the dynamic hot spots and verify the supply noise impact on timing, with close correlation to SPICE. By adding RedHawk-SDL in our power closure flow, we expect to lower our production cost for first working silicon."

Cadence Design Systems, Inc. announced the availability of an RTL-to-GDSII reference flow for SoC designs at 130 nanometers and below. The flow uses IP libraries and memories from Faraday Technology Corp., and involves use of UMC's technology that allows both high-speed and low-leakage transistors to be combined onto a single chip.

Ken Liou, Director of UMC's Design Support Division, is quoted: "By working closely with Cadence, we can ensure that the performance and capabilities of their digital IC solutions works smoothly with our process flow."

Cadence Design Systems also announced that Fujitsu Ltd. has standardized worldwide on the Cadence Incisive Conforma equivalence checking tool for verifying ASIC requirements of Fujitsu’s SoC designs.

Kazuyuki Kawauchi, General Manager of the Design Methodology Development Division of the LSI Group at Fujitsu, is quoted: "We've utilized the Conformal technology for four years and have tested it extensively for all our ASIC flows. Incisive Conformal is our equivalence checking solution of choice because of its superior performance, capacity and the ease with which the tool could be deployed to our design teams. Our design teams can reap the benefits of efficient and comprehensive verification from RTL to netlist, helping speed time-to-market and maximizing first-pass silicon success."

As well, Cadence Design Systems announced Stretch Inc. met "an aggressive time-to-market goal for a high-performance software-configurable processor design - and benefited from the strength of a comprehensive Cadence Digital IC design flow and libraries from TSMC to mitigate its design risks and ensure high quality of silicon (QoS) through improved area and performance."

The Stretch design discussed in the announcement included multiple clocks, custom programmable data paths, and extensive high-speed I/Os, which is why it’s not surprising that Wayne Heideman, Vice President of Engineering at Stretch, offered this testimonial: "The Cadence Encounter platform's world-class technology and methodologies, combined with the innovative Cadence VCAD service model and the TSMC-developed libraries, gave us the edge we needed to minimize our design time and achieve the QoS we required."

Finally, Cadence Design Systems and the Shanghai Research Center For Integrated Circuit Design (ICC) (described as "China's first national IC design industrialization base founded by China's Ministry of Science and Technology") announced the availability of the ICC-Cadence CPU/DSP SoC reference methodology. The reference methodology includes the Cadence Encounter platform, Incisive platform and CoWare’s ESL design and verification tools.

Ye Wang, Vice Director of ICC, advocates in the Press Release on behalf of youth: "This methodology reduces the risk of design failures, ensuring predictable performance and reducing the overall development time to silicon. These elements are particularly important for China's local enterprises to grow their SoC chip business when they are young."

Please note you will be tested later on the following paragraph:

"Shanghai Research Center for IC design (ICC) was established in March 2000 by the Science and Technology Commission of Shanghai Municipality. ICC focuses on promoting Shanghai and all China IC Design industry to realize rapid development. ICC set up the public service platform for all IC design enterprises, providing full services to improve design quality and lower the cost. As the executive organization of National IC Design Industrialization Center and National Productivity Promotion Center for IC Design, ICC takes on relevant tasks with the direction of the Ministry of Science and Technology of PRC. The services ICC provides including: Multi-Project-Wafer (MPW) service, Technology Platform service, Training and Evaluation Service, Information Service to name several. Up to now, ICC has provided services to over 200 IC design enterprises in China on more than 400 projects. In addition, ICC is a vice council director of China Semiconductor Industry Associati on IC Design Branch, a vice council director of Shanghai IC Industry Association, the director of Shanghai IC Industry Association IC Design Branch. The headquarters of ICC is located at Shanghai Hi-tech Kingworld, and they have a branch office in Zhangjiang Pudong. The director of ICC is Mr. Zhang Ao, who is the vice director of Science and Technology Commission of Shanghai Municipality."

Chartered Semiconductor Manufacturing announced functional 0.13-micron 300-millimeter wafers from its Fab 7, which the company says demonstrates results which exceeded internal targets within five months of the first equipment installation. Chartered also announced it has launched engineering 300-mm wafers at Fab 7 for its 0.11-micron process, as well for the 90-nanometer platform it is jointly developing with IBM.

Per the Press Release: "For 200-mm and 300-mm manufacturing, Chartered is already engaging with customers on its 0.13-micron and 0.11-micron solutions, as well as on the landmark 90-nm cross-foundry platform that will be available at both Chartered’s Singapore-based Fab 7 and IBM’s East Fishkill, New York fab."

Denali Software Inc. and Mentor Graphics Corp. announced a collaborative effort whereby Mentor Graphics will use Denali's PureSpec verification IP product to confirm that Mentor’s PCI Express IP core is compliant with the PCI Express and Advanced Switching Interconnect (ASI) interface standards, and interoperable with other system designs.

Per the Press Release: "Through this effort, Mentor will provide its customers with the highest possible quality IP, while lowering the cost of deployment and integration." Good news indeed.

Denali Software also announced the company has joined the newly formed Serial ATA International Organization (SATA-IO), and introduced two new products for use in the design and verification of chips incorporating the Serial ATA (SATA) interface standards. The new products include IP core designs and verification IP tools for the SATA II standards. The new core, Databahn-SATA, uses Denali's Databahn IP infrastructure for DDR memory, and helps developers to deploy SATA II interfaces on a chip. The new verification IP, PureSpec-SATA, uses technology from the PureSpec product line to provide for pre-silicon verification of functionality, compliance, and chip-to-chip interoperability in designs utilizing the SATA II standards.

HDL Works announced the release of version 5.2 of the EASE design entry environment for VHDL, Verilog, and mixed-language designs for FPGA and ASIC projects. EASE 5.2 includes Tcl-driven version management with support for ClearCase, RCS, and Synchronicity Design Sync, as well as Verilog 2001 support and a new project browser.

Per the Press Release: "Synthesis and simulation tool independence enables the user to select his most favorite tools while setting-up a complete design flow. EASE continues to be the most intuitive design entry environment in the market, while offering all necessary features for both advanced and novice HDL designers." [Have faith, Virginia. One of these days, there really will be a woman engineer or two.]

LSI Logic Corp. announced three new RapidChip IntegratorQSslices.

Per the Press Release: "The new slices leverage LSI Logic's proven-in-silicon and standards-compliant GigaBlaze serializer/deserializer (SerDes) technology by including four independent lanes of 4.25 gigabits per second (Gbps) SerDes. Another key architectural advantage of the RapidChip IntegratorQS slices is that they support PCI Express datapaths of 250 MHz. These datapaths are implemented in the metal configurable R-cell logic transistor fabric. The combination of SerDes and logic performance ensures that developers can implement ASIC-class low latency, high system performance solutions, with the benefits of risk mitigation and affordable NRE costs associated with Platform ASIC technology."

Silicon Canvas, Inc. announced the release of Laker-AMS version 6.1. The new release includes a new licensing scheme transition from Rainbow to FlexLM, enhanced hierarchy navigator usage, added Tcl/Tk scripting language support, a streamlined Spice-out procedure, and a new interface to the Laker full-custom layout tool.

Per the Press Release: "Greatly increased interest and a desire to shift from a traditional polygon pushing methodology to the schematic driven layout flow methodology make the new release attractive to a broad range of existing customers and new prospects."

SMSC announced what the company describes as "one of the industry’s most comprehensive lines of USB2.0, mobile super I/O and embedded Ethernet controllers for a wide range of consumer and commercial connectivity solutions."

Continuing in a technical vein: "With this announcement, SMSC delivers the USB2503 and USB2507, the industry’s first USB2.0 3-port and 7-port hub controllers with SMSC’s innovative MultiTRAKTM multiple Transaction Translator (Multi-TT) technology, as well as the USB2504, a second generation 4-port hub controller; the USB2228, a controller for 12-in-1 flash card readers; the USB3250, a second generation USB2.0 physical layer transceiver (PHY) device; the SIO1000, a second generation consumer InfraRed (IR) I/O controller; plus the Company’s LAN9118,a second generation 10/100 Non-PCI Ethernet controller." Clearly, these guys have been busy.

Jeff Ravencraft, USB Implementers Forum Chairman and Intel Technology Strategist, is quoted in the SMSC Press Release: "The industry is making great strides toward developing interoperable computing and consumer electronics devices, bringing the power of the PC to the digital home and allowing end users the ability to create, edit, store and stream their music, videos and photos. With its focus on USB 2.0 and non-PCI embedded Ethernet technology, SMSC is showing a commitment to connecting consumers in the digital home."

Synopsys, Inc. announced that Samsung Electronics Co. Ltd. has signed a multi-year license agreement for Synopsys' DesignWare IP, under the terms of which Samsung is licensing Synopsys’ PCI Express and USB families of digital cores and analog PHYs. The first DesignWare IP Core Samsung will use under the license agreement is the USB 2.0 PHY core. By standardizing on Synopsys' certified Hi-Speed USB 2.0 PHY core, Samsung says it will more quickly deliver "flexible, cost-effective USB 2.0-enabled products based on 130-nanometer and 90-nanometer process technology to its ASIC customers."

Synopsys also announced that IPCore Technologies Corp. (described as "China's pioneer pure design foundry") has signed a multi-million dollar agreement to adopt Synopsys' Galaxy Design and Discovery Verification Platforms, and Synopsys’ DesignWare IP portfolio as IPCore's primary internal design flow. The company says that under the terms of the agreement, "Synopsys Professional Services will also expand its delivery capability in China by selectively utilizing IPCore on a subcontracting basis."

Jerry Lee, CEO of IPCore Technologies, is quoted: "Synopsys' solutions have been successfully used for thousands of designs worldwide. This expertise is especially important as we move into the complex realm of deep submicron design."

Meanwhile, Synopsys announced the availability of the DesignWare USB 2.0 On-The-Go (OTG) PHY (Physical Layer) Core targeted to TSMC's 90-nanometer, 130-nanometer, and 180-nanometer processes, as well as an extension of the Hi-Speed USB 2.0 PHY Core product line to the 90-nm process node.

Per the Press Release: "The new OTG PHY handles HNP (host negotiation protocol) and SRP (session request protocol), which are the OTG-specific differences between the Hi-Speed 2.0 and the new OTG standard. Available targeted to TSMC's 180-nanometer, 130-nanometer, and 90-nanometer processes, the OTG solution is based on the Synopsys USB 2.0 PHY that is already certified and shipping in volume."

"The new USB PHYs, which are complete physical layer interface cores compliant with the USB 2.0 OTG standard that provide an integrated solution that has been implemented in silicon and tested with Synopsys' leading family of digital USB IP cores, including the DesignWare Hi- Speed OTG controller, Host Controller and Device Controllers."

TransEDA announced the availability of its PCI All-in-One verification IP and its latest VN-Control bus-based system-level test generator release 3.0. Per the Press Release: "The PCI All-in-One verification IP provides a single, compatible programming interface which enables verification teams to easily reuse their tests on systems containing any combination of PCI Express, PCI-X and PCI buses. The new IP accommodates testing of various system-level configurations such as systems containing PCI Express buses only, a combination of PCI-SIG standard buses, or a single PCI-SIG standard bus selectively enabled."

"The new version of the VN-Control test generator works with TransEDA's verification IP for PCI Express, PCI-X, PCI, Intel processor buses, or user-created verification IP to speed up debugging and provide greater flexibility for creating bus activity and tests. The latest version of the VN-Control test generator creates more sophisticated system-level tests and contains an enhanced debug data display."

Jim Pappas, Director of Initiatives at the Intel Enterprise Platform Group, is also quoted in the Press Release: "The benefits of PCI Express technology appeal to a wide range of manufacturers of applications that include desktop, mobile, server and communications products. TransEDA's announcement of pre-silicon verification IP and tools reflects the broad adoption of PCI Express throughout the industry and the breadth of tools emerging to support that growth."