There's lots of dense reading here, so please try to concentrate, but first an Editor's Note ...

The people in the PR community go to a lot of effort to produce Press Releases. It's true that editors often complain about the fact-to-hype ratio that frequently shows up in those documents, but frequently there's also a great deal of valuable technical information and nuance as well. This week's new items, I think, are particularly representative of that situation. There's some very handsome writing here, so whoever wrote all of this - and you know who you are - Great job!

** How the disaggregated design and supply chain works **

Let's look at this one exactly as is came off the wires. It's enchanting to that the news comes from four locations and five companies.

CAMBRIDGE, UK; SUNNYVALE, Calif.; MOUNTAIN VIEW, Calif.; and HSINCHU, Taiwan -November 8, 2004 - ARM, Artisan Components, Inc., National Semiconductor Corp., Synopsys, Inc., and UMC today announced that the five companies are collaborating to deliver a comprehensive low-power, energy-efficient SoC technology demonstrator for the ARM926EJ-S processor. The "ULTRA" technology demonstrator for the ARM926EJ-S processor is being implemented in UMC's 130e Fusion process, a 130-nanometer process platform designed for the integration of high-speed and low-leakage transistors in a single CMOS process. The ULTRA technology demonstrator name stands for UMC Low-power Technology Reference using the ARM926EJ-S processor.

Lowering power is one of the greatest challenges facing the IC industry today. Each of the five companies in this collaboration has demonstrated technologies that contribute substantial power savings. The close collaboration between the five companies promises to deliver even greater systematic power savings by linking their power-saving technologies into an integrated power reduction solution. The combined power-savings capabilities of these technologies are expected to demonstrate up to 60 percent energy savings. This savings is expected to translate directly into the longer battery life required by the fast growing hand-held/portable markets in which multimedia products that include 3-D graphics, video/audio and communications functions are becoming more prominent.

The ULTRA technology demonstrator for the ARM926EJ-S processor will incorporate ARM Intelligent Energy Manager (IEM) technology and the National Semiconductor PowerWise Technology Advanced Power Controller (APC) with an integrated Hardware Performance Monitor (HPM) to reduce overall power and energy consumption. The combined technologies enable the system to implement Adaptive Voltage Scaling (AVS) as well as frequency scaling. The system is expected to show the lowest voltage and frequency required to meet software deadlines while maintaining user quality.

The ULTRA SoC technology demonstrator for the ARM926EJ-S processor will use Synopsys' leading Galaxy Design Platform for a comprehensive low-power design implementation flow that includes multi-voltage and multi-frequency design optimization. Additionally, the ULTRA SoC technology demonstrator for the ARM926EJ-S processor will use Synopsys' DesignWare Library for AMBA bus and peripheral IP to implement a complete SoC. Synopsys Professional Services is providing the RTL-to-tapeout design services for the demonstrator chip using this advanced low-power methodology.

Artisan's Metro platform of products is the underlying physical IP that enables the low-power technology demonstrator design. The platform includes standard cells, I/Os, memories, phase locked loops (PLLs) and other mixed-signal cells designed for low dynamic and leakage power at any operating voltage. In addition, the products are characterized to operate at very low voltages, thus allowing the energy reduction enabled by ARM IEM technology.

The technology demonstrator will be enabled by UMC's advanced 130-nm Fusion process, which combines high-speed and low-leakage transistors onto a single chip to create a low-power solution while minimizing performance trade-offs. The embedded ARM926EJ-S processor is already silicon proven in UMC's process. The ARM926EJ-S processor delivers high performance, low power and operates at low-voltage ranges.

The technology demonstrator will include a finished SoC, a demonstration printed circuit board (PCB), and software, and will show how each company's low-power capabilities contribute to a comprehensive low-power offering. The SoC resulting from the collaboration is not intended for sale, but instead to demonstrate both the unique and combined capabilities of the five companies when applied to the problem of IC power use. The partners are planning to exhibit the technology demonstrator at select tradeshows beginning in early 2005.

The Press Release wraps up with quotes and commendations from Mike Inglis, executive vice president marketing, ARM; Neal Carney, Artisan's vice president of marketing; Peter Henry, vice president of Portable Power Systems at National Semiconductor; Rich Goldman, vice president, Strategic Market Development, Synopsys, Inc.; and Patrick T. Lin, chief SoC architect at UMC. I don't envy the uber-PR coordinator who had to pull all of that together!

ZMD announced what it calls "the industry's first sub-1GHz, IEEE 802.15.4 development kit for ZigBee applications. This development kit, the ZMD44101DK, lets developers perform detailed evaluation of ZMD's low-power ZMD44101 RF transceiver using a simple graphical interface, and includes a software framework for application development. Tailored for ZigBeeT applications, the fully integrated CMOS transceiver enables highly reliable wireless networks for monitoring and control in industrial, commercial and residential applications." ZMD says the development kit enables test functionality at the physical layer and MAC layer, has two wireless transceivers, quick-start hardware, compiled MAC libraries, and examples for application development.

Xilinx, Inc. announced two new devices in the CoolRunner-II CPLD product family. Straight from the horse's mouth: "Known as CoolRunner-IIA and available in 32 and 64 macrocell densities, the XC2C32A and XC2C64A devices incorporate an additional I/O bank to support voltage level translation and device interfacing - at the same time preserving the cost-optimized, low-power characteristics of the CoolRunner-II product family. Xilinx is also offering the two devices in smaller footprint, lower cost packages. The new Micro Lead Frame (MLF) chip scale package options reduce the device footprint at prices comparable to standard Quad-Flat-Pack (QFP) packages (historically, chip scale packages have been substantially more expensive and therefore not good candidates for high volume applications)."

"The need to integrate multiple circuit functions in a single device is critical - especially for today’s highly integrated handheld devices. The new features of the XC2C32A and XC2C64A devices enable this integration in a wide range of applications. They are ideally suited for interfacing busses and devices that use varying voltages and standards. They are employed as fixes or extensions to standard products and ASICs. In addition, with the low power and high performance enabled by the proprietary RealDigital technology from Xilinx, these new products are the ultimate custom logic for low-power sensitive, handheld designs."

"The need for voltage translation is common in many systems. While there are numerous discrete logic solutions to address this problem, they are limited by their relatively high price and inability to integrate additional functionality. By comparison, the CoolRunner-IIA CPLD solutions allow a designer to cost effectively implement voltage translation as well as many other logic functions in a single programmable logic device."

"With the new MLF packages, customers can now get the benefit of chip scale packages at a significantly lower cost. The CoolRunner-IIA 32 macrocell CPLD is available in a 32 pin, 5mm by 5mm MLF package with 21 I/O, while the 64 macrocell CoolRunner-IIA CPLD is available in a 48 pin, 7mm by 7mm MLF package with 37 I/O. These packages offer substantial price savings over similar sized ball grid array packages. They also offer better electrical characteristics and are much easier to probe since there are no buried pins. The new packages are available at Pb-free devices - to support applications that must comply with Reduction of Hazardous Substances (ROHS) requirements. Xilinx uses the package designator "Quad Flat No-Lead Pb-free" (QFG) for MLF package options."

X-FAB Semiconductor Foundries AG says it has a new, patented PIN-diode module for its 0.6 µm BiCMOS technology (XB06). For the first time, the company says it is now possible "to integrate PIN diodes (PIN = positive intrinsic negative) with CMOS and BiCMOS transistors on a single chip. The parameters of standard XB06 transistors are not influenced by the integration of PIN diodes. The significant advantage of PIN diodes over conventional PN diodes is a reduction in barrier capacitance of around 80%. As a result, a speed increase of over 85% in signal rise and fall times is achieved. In addition, light is converted into electrical signals more rapidly, which makes PIN diodes ideally suited for high-speed data communications, e.g. for DVD pickup systems. The diodes' spectral sensitivity enables their implementation in DVD systems with either red or blue lasers. Furthermore, it is possible to use an antireflective coating (ARC) that further optimizes the diodes' spectral characteristics."

ViASIC Inc. announced the availability of its new 0.13-micron ViaMask library for TSMC and TSMC-compatible processes. The company says the new library is silicon-proven and produces a 10-percent increase in density, and a higher performance than the previous version. Per the Press Release: "ViaMask is a one-mask configurable logic and memory semiconductor technology that may be used as an embedded block on a chip or as a full-chip fabric for building structured ASICs. With single-photomask configurability of both memory and logic, ViaMask can deliver densities in excess of 80% of standard-cell densities, more than double most structured ASIC fabrics. Performance improvements enable two-nanosecond RAM access and logic speeds greater than 2 gigahertz."

Toshiba Corp. and ARM announced that Toshiba has licensed the ARM1136J-S processor. Toshiba says it will use the processor to develop ASICs for products such as consumer electronics and network systems. That's a good idea. The Press Release says, "Since 1998, Toshiba has licensed the ARM7, ARM9, and ARM10 family processors for numerous applications ranging from mobile communications to consumer electronics. This announcement demonstrates Toshiba's commitment to the ARM11 family for the development of system ASICs. This agreement includes an option for Toshiba to license other ARM11 family processors." Probably also a good idea.

Thomson announced that the company has licensed ARM OptimoDE signal processing technology for the development of broadcast video processing ICs. Jean-Charles Hourcade, CTO at Thomson, is quoted in the Press Release: "Thomson and ARM share a common dedication to providing innovative technologies that help maintain competitive advantage, and leverage advanced microprocessor technology to enable innovative broadcast applications. The flexibility of the OptimoDE Data Engine will ensure that we can tackle current industry standards, such as AVC, and address emerging standards without sacrificing product quality or bearing the cost of complete product re-design."

Stelar Tools, Inc. has introduced HDL Explorer, which the company describes as "the first EDA tool to deliver rapid RTL Closure. HDL Explorer provides a unique combination of new design creation, and exploration and editing of new and legacy designs and testbenches—all while using best-known methods (BKMs). HDL Explorer lets designers and verification engineers quickly and easily find and fix errors, and define and manage the design – verification interface in their new or existing HDL designs. This results in a 30 percent reduction in the time it takes to get a complex ASIC, SoC, structured ASIC, or FPGA design from concept through synthesis. HDL Explorer is the first in a family of products from Stelar that will speed the design, verification, analysis, and testing of complex electronic product designs."

Steve Sapiro, vice president of marketing, is quoted in the Press Release: "Because it costs 10 times more to find and fix errors at each successive stage in the design process - for example, errors found at simulation are 10 times more expensive to find and fix then those caught at RTL, and those found at synthesis are 100 times more expensive - customers are excited about using HDL Explorer to help them get their designs clean before synthesis. With HDL Explorer, we’ve collapsed into one place the hundreds of tasks that must be completed in a large design project. We’ve made the tool fast and easy to use, and easy to integrate into a projects’ existing tools and methodologies, enabling users to focus on completing their designs."

Study on ... "Designers traditionally spend time manually creating design entities using traditional text editors and exploring existing legacy designs using hard copy printouts and hand-drawn diagrams. Many designers use a simulator or synthesis tools as error checkers and debuggers. And often, design projects must start from ground zero because documentation in today’s changing engineering environment is insufficient and knowledge gained from previous projects has been lost or not sufficiently documented. It is important for the project that information is captured and distributed to all members of a design team."

"HDL Explorer can deliver benefits to designs of every size, but all of its features and thus maximum benefit come into play for designs of two million gates or more. Using five patent-pending technologies, HDL Explorer lets users create new design entities, IP, connections and testbenches, and stitch blocks together. It also enables users to explore and analyze existing designs and testbenches using various views - helping users quickly find and fix design errors, and to define and manage the design-verification interface. In addition, it offers design managers the ability to easily extract status and statistical information from a large design for better management. With these options, HDL Explorer facilitates rapid RTL Closure to provide a huge time savings over traditional approaches."

And in closing ... "As designs get larger, the text files are substantially larger and harder to deal with using typical text editors. Using a ‘smart’ editor that combines interactive, intelligent text and smart graphics features, HDL Explorer lets an engineer pick the best method for design creation. Users are not forced to choose between text and graphics - they can easily switch between smart graphical and intelligent text views of a design as needed. The graphics mode enables users to see the big picture, and the intelligent editor enables them to quickly add and connect modules, signals or testbenches through the hierarchy, or to encapsulate a group of modules for later use."

Stelar Tools, Inc. also said it has integrated Verific Design Automation’s HDL Component Software with its graphical and textual design environment. The companies say that Verific’s HDL Component Software, which has C++ source code-based Verilog and VHDL parsers, analyzers and elaborators, acts as the front end to Stelar’s toolset "for creating, exploring, navigating, analyzing, documenting and modifying a design within an existing design environment."

The Press Release includes Point/Counterpoint ...

Scott Bloom, Stelar’s vice president of engineering, commends the Verific tools, "The runtime and memory footprint is on par or vastly superior to all other parsers that we evaluated. Support has been superb, as well. No issue took longer then three days to have a workaround, and all enhancement requests were granted.

Joe Tanous, Stelar’s CEO comments on the business side of the equation: "Verific was willing to work with us pre-funding and went out of its way to help us build a quick prototype to show to investors."

Michiel Ligthart, Verific’s vice president of operations, returns the compliment: "Stelar is an emerging EDA company with loads of promise. Our intention is to be part of its success every step of the way."

SoftJin has released a free suite of IC design layout data exchange libraries and tools for use by IC designers and EDA product companies. This includes GDSII and OASIS readers, writers and GDSII-to-OASIS translator, in source code form. The software suite is named Anuvad (a named that means "translation" in Sanskrit) and according to the company "includes one of the earliest available tools to handle the OASIS format, and the only one available for free use in source code format."

Per the Press Release: "The volume of the data to represent the IC design during the layout design phase has exploded in size, with enormous growth in the size and complexity of the ICs as well as nanometer accurate manufacturing processes. GDSII has been the industry standard format for representing the Layout data and exchanging layout data between chip design teams, silicon foundries and mask companies. OASIS (Open Artwork System Interchange Standard), promoted by Semiconductor Equipment and Materials International (SEMI), is a new and much more compact format that is slated to replace GDSII as the standard data format used for exchanging layout data."

"The Anuvad suite contains building blocks that facilitate early adopters to migrate towards OASIS format. The GDSII and OASIS reader and writer libraries enable users to develop their own post layout analysis, editing, mask data preparation and other DFY/DFM tools. In addition, a suite of utilities developed using the GDSII and OASIS libraries are also released in source code form. Among these, the most significant is the GDSII to OASIS converter that has been tested and benchmarked with real life layout data from several semiconductor companies. It has been observed that this tool provides an average of 20X compression while converting layout data from GDSII format into OASIS format. Apart from the significant value addition these utilities bring on their own, the source code release of these utilities demonstrates the way to use the GDSII/OASIS libraries. "

SoftJin says it has released the source code of the entire Anuvad software for free download from the company's website. The license enables users to use, enhance and modify the source code to develop their own tools and utilities for internal as well as commercial use. There is no restriction on source code redistribution internally. There is no restriction on the object code distribution internally or externally. However, the source code redistribution externally is restricted only through the common mailing list meant for Anuvad developers.

Kamal Aggarwal, Vice President, Marketing and Strategy at SoftJin, is quoted in the Press Release: "For early adoption of OASIS and smooth transition of GDSII legacy to OASIS, the tool developers should be able to work on the high value added tools which would exploit the native constructs of OASIS rather than using OASIS simply as a compact form of GDSII. For this, the tool developers have to focus on fundamental changes in the in-core array and hierarchical data representation and parallel algorithms working on them, rather than spend energies on the readers, writers, translators and viewers for GDSII and OASIS. Anuvad is being released with the objective of providing jumpstart to OASIS based tools development by commoditizing the basic infrastructural libraries for GDSII and OASIS by making them freely available in source code format."

Kamal Aggarwal sent these additional comments in response to a question I sent to him about a business model that makes EDA tools available free of charge: "To answer your question about releasing the Anuvad product for free, please note that the Anuvad software suite contains essential building blocks that help early users to migrate towards OASIS format. These building blocks shall enable tool developers to work on high value added tools that use the native constructs of OASIS. They need not spend time and effort in developing readers, writers, etc. The free source code release of Anuvad is in line with our customized tool development service business model. We want to be the leading player in developing customized tools in the post layout domain and specifically in the OASIS domain. So, the release of Anuvad serves as a useful demonstrator of our customized tool development services related capabilities in this domain."

SMSC and TransDimension announced that TransDimension's high-speed USB controller IP, a ULPI interface block, and SMSC’s USB3300 ULPI stand-alone physical layer transceiver (PHY), are the first products to pass the high-speed USB Implementers Forum (USB-IF) compliance testing using the new ULPI interface. ULPI modifies the UTMI+ link/PHY interface to significantly reduce the pin count for discrete USB transceiver implementations supporting host, device and On-The-Go (OTG) functionality. This low pin count interface allows for transceivers to be kept separate from the associated digital ASICs as the technology nodes become smaller and integrating the PHY becomes more complex and expensive.

John Cassidento, IP Marketing Manager at TransDimension is quoted. "By implementing external PHYs with a proven, low pin count interface such as ULPI, SoC manufacturers will be able to keep this difficult analog technology out of their designs and thus lower risk and improve time-to-market. We are proud to have SMSC as a proven, certified partner for our high-speed IP."

Sequence announced a "major milestone" in recent power optimization efforts with Toshiba. Toshiba says it signed off on a wireless design using Sequence's MTCMOS (Multi-Threshold CMOS) technology. So, now Sequence says it is the first EDA company "to achieve power-gating optimization by dramatically reducing leakage on a 90 nanometer design." That's pretty interesting.

Per the Press Release: "MTCMOS power-gating works to reduce leakage currents by disconnecting the power supply from portions of the circuit when those portions are inactive. Leaking currents are prevented by inserting a series switch transistor between the logic cells and the power supply or ground. The switch is closed when the logic is operational and opened when the logic is inactive. Sequence and Toshiba have worked together to develop an automated process, based on Sequence's Physical Studio framework, to size and insert power-rail switching transistors. Reductions of 10x to 100x in leakage can be achieved by using this technique."

Shinichi Imai, Senior Manager of System LSI Design Department at Toshiba, is quoted: "The leakage current reduction realized by Sequence is not possible with any other currently available tool. Sequence's innovative circuit design and automation techniques used on Toshiba's MTCMOS technology automatically reduced leakage currents while concurrent electrical checks ensured that the logic and signaling did not violate user-specified limits on key electrical parameters such as virtual ground voltages and currents." Good job.

OASIS Tooling has announced support of the OpenAccess platform version 2.2. Per the Press Release: "OASIC Mosaic is a developers' platform for semiconductor design using the OASIS interchange format and making OASIS an extension of the OpenAccess database. Part of OASIS Mosaic’s tool suite and utilities is the OpenAccess database 2.2 Viewer (2d and 3d) with user-controlled layer selection, layer color and rendering style, and process based layer height and thickness for 3d viewing. The native OASIS import and export facility includes an enhanced data compression based on modal variable filtering, repetition recognition, trapezoid recognition and the use of CBLOCK. Mosaic is a multi-threaded execution; multiple views can be converted to OASIS at the same time resulting in very high throughput on multi-processor systems. OASIS Mosaic also uses the new OA 2.2 Turbo DM system with library level access method for ensuring data integrity while viewing and OASIS import/export. The limited timeframe no-charge license still applies to OpenAccess and SEMI OASIS Working Group Members. Up-front commercial licenses and custom development programs are also available."

MatrixOne, Inc. announced that Elettronica (ELT), a leading manufacturer of Electronic Defense equipment and systems headquartered in Rome, Italy, has successfully completed implementation of MatrixOne's PLM platform.

The document lifecycle has been revolutionized through a simplified coding and management architecture for the data and the specifications of each component listed in the database. Component classes and types have been reduced from sixty-six to twenty-five, and adopted code types have been reduced from seven to two.

These revisions of the information system, combined with the adoption of a new packet-based data management system, notably raised the business database's reliability. Moreover, the real-time data sharing capabilities allow for better monitoring and timely resolution of critical problems. The introduction of digital signatures for project validation and the use of shared documents in electronic format have significantly reduced the printing and management costs of internal archives for each department. In addition to facilitating each project implementation, the new information architecture enables every user to always access the most up-to-date information about BOM modules and reporting activities, thereby shortening product implementation times.

More effective coordination among all the key value chain participants, with a special consideration to partners and suppliers, has sped the digital prototyping and testing of new product models. Research and development and quality management activities benefit greatly from the information system integration and reengineering, allowing Elettronica to speed the time to market of new product models within increasingly demanding industries, such as Aerospace & Defense.

CoWare Inc. has announced what it calls "a major new release" of its SystemC-based ConvergenSC SoC design tools. The company says the new tool will speed adoption of ESL design methodologies by system designers and architects. New features allow for faster modeling and debug of IP models, platform subsystems, and SoC designs in SystemC, with an open environment that eases integration of internal tools and IP into the system-level flow. The new SystemC development environment, ConvergenSC includes a SystemC integrated development and debug environment (IDE) based on the open Eclipse C++ development environment for embedded software. CoWare also says that ConvergenSC supports the latest release from OSCI, SystemC version 2.1.

Manoj Bhatnagar, Principal Engineer for CPE System Architecture at Centillium Communications, is quoted in the Press Release: "The Eclipse-based SystemC IDE is very feature rich, and it provided production quality capabilities needed for hardware/software development. The Eclipse IDE enabled us to be productive immediately while adopting SystemC and ESL for the first time."

This part of the Press Release is particularly cogent: "Faster Design of SoC Platforms and Derivatives Platform subsystems, consisting of IP blocks and software tailored for specific domains, are emerging as the industry's new definition of IP. As interactions between hardware and software become more complex, ESL design tools are essential to designing and re-using these platform subsystems. With this new release, ConvergenSC adds capabilities that ease integration of user IP and enable re-use of platforms in derivative designs, magnifying the benefits of ESL methods that include: SystemC 2.1 and open support for user TLM specifications; Hierarchical platform development; Export of fixed platform subsystems; Import of subsystems for SoC assembly and extension Using these capabilities, platform providers can more easily create system-level models of platform subsystems for their customers' rapid evaluation, customization, and design-in." This is what it's going to take to get ESL into the mainstream. Good job, CoWare.

Atmel Corp. and Mentor Graphics Corp. announced an extension/expansion of the existing OEM agreement between the two companies for "advanced synthesis, simulation, and verification tools" from Mentor Graphics. The companies say, "The new agreement signifies the industry's most comprehensive OEM relationship between a PLD vendor and EDA solutions provider, and spans the full spectrum of tools essential for both FPGA and CPLD design."

Anadigm says it has launched the first of a series of Configurable Analog Starter Kits that include "ready-to-use EDA files, source code for dynamic configuration, and extensive step-by-step instructions for implementing the circuit in a field programmable analog array (FPAA)." Features include a subwoofer signal conditioner, which has three examples of potential single-chip FPAA subwoofer signal conditioning circuits; an audio effects phaser, which describes a reference design for implementing a simple audio phase shifter using a single AN221E04 FPAA; and a dynamic programming guide low-frequency filter design kit, which explains how to build any type of low-frequency filter using the AnadigmDesigner2 EDA software and a single FPAA device. The company also says that it's sending "complete instructions show how to use C-code automatically generated by AnadigmDesigner2 to control all the attributes of the filter dynamically." That's definitely going to come in handy.

Altium Ltd. announced the Service Pack 2 for the Nexar FPGA-based system design software will include a new 32-bit FPGA-based RISC processor that the company says will simplify the development of 32-bit systems targeted for FPGA implementation, and help to take the risk out of migrating systems to the 32-bit domain.

Per the Press Release: "The processor has been specifically designed to minimize the complications and complexity usually associated with 32-bit system design. Dubbed the TSK3000, the RISC processor is internally based on the Harvard architecture, but features a simple memory structure and hardware-based vectored interrupt handling to make coding simpler. Interfacing to the processor is also simplified by the provision of separate bus interfaces for connecting memories and peripherals. A user-configurable, fast on-chip memory system improves performance and simplifies memory system design.

The TSK3000 uses the open-standard Wishbone "System-On-Chip Interconnect" bus to allow system designs to be used on any target FPGA families with no licensing issues. A large selection of Wishbone peripherals is supplied with the Nexar design system ... The TSK3000 is supplied pre-synthesized for a wide variety of target devices ... Service Pack 2 for Nexar will also see the addition of full embedded software development support for the TSK3000, with a highly-optimizing C compiler based on Altium's TASKING Viper compiler framework, as well as a fully-integrated assembler, profiler and source-level debugger."

Altium Ltd. also said it will be expanding the HDL capabilities of Nexar with support for Verilog. Also, the upcoming Service Pack 2 for Altium's DXP 2004 design systems, which includes updates for Nexar and the Protel board-level design system, will add syntax-aware code editing, parsing and compilation support for Verilog.

Agilent Technologies Inc. announced the availability of its new ultra-wideband (UWB) Design Exploration Library. The company also announced that Daido Steel Co. Ltd. has selected Agilent’s Advanced Design System (ADS) 2004A EDA software and the new UWB Library to help in the development of bandpass filters used for UWB transceivers. Takahiko Iriyama, general manager of Daido Steel, is quoted in the Press Release: "Agilent’s UWB Design Exploration Library will allow us to verify our filter spectrum against FCC specifications, both today and as new wireless applications emerge. Combining measurement results from Agilent instruments with ADS and the UWB Design Exploration Library lets us investigate design ideas very early in the process, which helps us deliver superior products to our customers."

Agilent Technologies also says it's offering a free MP3 player/voice recorder for EDA users in a special promotion. By way of a weekly drawing, the company says it will give away the devices to those viewing a 10-minute, online video about the newest ease-of-use and productivity features of its ADS software. After watching the video, viewers can enter the drawing for the combination 3-in-1, 256 MB USB storage device/MP3 player/voice recorder. Drawings will be taking place through April 30, 2005. I once got some free luggage in a drawing.

AccelChip Inc. announced that the Jet Propulsion Laboratory (JPL) has selected AccelChip DSP Synthesis and AccelWare IP libraries to develop a digital filter for space-based radar applications. The companies say that AccelChip’s DSP design automation tools will be used to shorten the design cycle and explore design alternatives, including performance and resource utilization, to obtain the level of optimality required in sensitive radar applications. JPL will be using the MATLAB language to model the digital filter. The AccelChip algorithmic synthesis tool will then be used to automatically generate synthesizable, bit-accurate VHDL and Verilog from the MATLAB model and provide a testbench for implementation and verification, accelerating the design process.

To Infinity & Beyond: "Managed for NASA by the California Institute of Technology, JPL has exciting missions spread throughout the solar system. It handles such projects as the 2004 Mars rover landings, the Cassini spacecraft, which is currently undergoing a four-year study of Saturn, and the Deep Space Network, an international network of antennas that support communications between distant spacecraft and Earth-based teams. JPL missions also turn a watchful eye on the Earth, using spacecraft and instruments aboard NASA satellites to expand knowledge of our home planet. Technologies developed for space often have other applications in fields such as medical, communications, security, and more." Good news, because the home planet could use a watchful eye now and then.