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* Actel Corp. announced new capabilities with its Libero Integrated Design Environment (IDE).

Per the Press Release: "Libero 6.3 software provides a secure design flow – from synthesis through implementation – for integrating Actel’s CoreMP7, the industry’s first soft ARM7 family processor, into Actel’s single-chip, nonvolatile FPGAs … The enhanced software also automates the task of I/O voltage assignment and supports Actel’s new RTAX4000S devices, the industry’s highest density FPGA for space applications … Tight integration with industry-leading, third-party tools from Magma Design Automation, Mentor Graphics and Synplicity enables seamless synthesis, verification and physical synthesis for designs incorporating CoreMP7. Enhanced black-box support from Synplicity and Magma Design Automation, within their respective synthesis and physical synthesis tools, enable a secure flow, while Actel’s own proprietary tools provide state-of-the-art encryption to protect the valuable ARM7 IP from unauthorized access."

Michael Mertz, Senior Manager of Tools Marketing at Actel, celebrates the new release: "By enhancing Libero to support a soft ARM7 family processor implementation, we can put this advanced microprocessor technology into the hands of more FPGA designers. Further, by automating previously manual tasks and offering unique timing analysis capabilities, we enable FPGA designers to quickly achieve optimal results."

* Aldec, Inc. announced the release of Active-HDL 7.1. Per the company, "Active-HDL 7.1 is a new FPGA and ASIC design entry and verification platform with several new high productivity tools. New tools include, ultra-high speed gate-level simulation technology (SLP), VHDL and Verilog Linting tools, improved support for MATLAB and Simulink and new SystemVerilog simulation support … Active-HDL 7.1 also includes new VHDL and Verilog lint tools, all new MATLAB and Simulink interfaces (exclusive to Aldec), and smart incremental compilation for Verilog."

Laura Consoli, Product Marketing Manager for Aldec, adds per the Press Release: "Adding the debugging improvements for SystemVerilog will provide a completely new level of support from Aldec."

* Applied Wave Research, Inc. (AWR) announced that its Visual System Simulator (VSS) software now provides a WiMAX broadband fixed-wireless solution for the design of WiMAX-certified broadband wireless access (BWA) products. AWR's VSS meets the IEEE standard 802.16-2004 Wireless MAN-OFDM PHY specifications, and includes all the bit level functions, framing, randomization, RS-CC coding, interleaving, modulation, pilot, channelization, and bandwidth options for uplink and downlink operations.

Chuck Campbell, Design Engineering Director at TriQuint Semiconductor, offered an associated testimonial: "AWR’s support team and software products are an integral part of the TriQuint design process, so AWR was a natural partnership choice when we needed to develop a WiMAX standard capability. The seamless integration of Microwave Office circuit design and VSS system design software in one platform has really helped our engineers meet the challenges of designing cutting-edge integrated circuit products quickly and easily."

* ASSET InterTech Inc. announced an online service that "validates the accuracy of boundary scan description language (BSDL) files which describe the boundary-scan characteristics of semiconductor devices."

ASSET collaborated with Agilent Technologies on the development of the service – Agilent previously offered an e-mail-based BSDL checker, but this new BSDL Validation Service expands on those capabilities.

Alan Sguigna, Vice President of Sales and Marketing for ASSET, explains: "Before JTAG tests can be automatically generated, the engineer has to have BSDL files for all of the devices on a scan chain. So the whole process begins with BSDL files. Anything we can do to help chip suppliers verify the accuracy of BSDL files will greatly improve the testability of printed circuit boards and systems for hardware manufacturers."

* Cadence Design Systems, Inc. announced that the Cadence Encounter Test family of products "has been validated on Agilent's 93000 SOC Series automated test system. With this validated test and diagnostic flow between EDA and ATE, joint customers can be confident of higher-quality tests, faster test program creation, and more rapid resolution of yield limiters for their most challenging nanometer designs." Nice news during ITC Week.

Pascal Ronde, Vice President for Semiconductor Test Solutions at Agilent, is quoted: "This linking of EDA and ATE for test generation and diagnostics removes a significant barrier to meeting critical time-to-market requirements faced by semiconductor companies without such a validated flow."

* Cadence also announced a "cooperative quality modeling initiative" with STARC (The Semiconductor Technology Academic Research Center). The two companies say they are working together to estimate the semiconductor device outgoing quality level as a function of delay test robustness applied in manufacturing.

Happily, the first result of the initiative is STARC's quality model's validation of Cadence's Encounter True-Time Delay Test, which shows that delay defects slow signal transitions in nanometer-scale designs, making delay testing critically important." Guess it wouldn't be critically important otherwise.

Yasuo Sato, Senior Manager for the Test Methodology Group at STARC, is pleased: "STARC has developed a statistical delay quality model (SDQM) methodology to quantify the effectiveness of a given delay test method. Cadence has successfully implemented support and validated results for this technology. Based on the results observed with our experiments, we expect that Encounter True-Time Delay Test can be very effective in detecting small delay defects, and thus improve the chip's outgoing quality level."

* Cadence also announced that its new Encounter Test Architect technology helped Atmel Corp. tape out Atmel's first single-chip DVD/CD SoC.

Mehdi Bathaee, Atmel's Network Storage Business Unit General Manager, is impressed: "Inserting the test and generating patterns in time for tapeout was key to our project's success. With Encounter Test, and the Cadence team's support, we achieved our time-to-tapeout and exceeded test coverage objectives."

* Cadence also announced that Kawasaki Microelectronics, Inc. selected the Encounter True-Time technology, which Cadence says is "the industry's first delay test ATPG that uses design timing to automatically generate faster-than-at-speed delay tests. Cadence also introduced two key enhancements to its delay test technology, True-Time for bridges and True-Time through RAMs."

Hiroyuki Nakamura, Manager for CAD Development at Kawasaki Microelectronics, looked before he leaped: "Effective transition fault ATPG testing is a key requirement to detect delay defects in nanometer designs – a problem that will only get worse at smaller process geometries. After extensive evaluation, we have chosen Encounter True-Time delay test for our flow, based on its ability to maximize test coverage by detecting the smallest delay defects, and support for on-product clock generation for path delay and transition fault tests."

* Cadence also announced that MediaTek Corp. in Taiwan has adopted Cadence Encounter Conformal Constraint Designer. MediaTek says the company "intends to deploy the tool throughout all the company's design divisions over time."

* Carbon Design Systems announced that Pacific Design has "made available its configurable VUPU processor and accompanying instruction set simulator on Carbon's VSP validation platform. This latest VSP addition enables a system prototype with Pacific's VUPU to be rapidly assembled and functionally validated on an engineer's desktop months before silicon."

* Yoshihide Sugiura, President of Pacific Design, is quoted: "Our customers need to validate their software with the target hardware implementation. Carbon's VSP enables data path blocks, IP cores, and our ISS to simulate together. Carbon is the answer to continuous SOC validation, from early stage architecture performance modeling, to validating the final embedded software before tapeout."

* CAST, Inc. announced "the immediate availability of ready-to-use IP subsystems for designers working with ARM processors and the AMBA bus architecture. The new Pre-integrated IP (PiP) products give SoC designers a head start by providing the basic hardware and software infrastructure needed for an ARM-based SoC."

Per the Press Release: "Each PiP includes several essential IP cores — bus controllers, timers, interrupt controllers, UARTs, SRAM controllers, I/O interfaces, and more — plus all the device drivers and boot code needed to start developing application software right away. They also include embedded real-time operating system (RTOS) support, and a comprehensive test suite that features an ARM7 bus functional simulation model. The ARM-based PiPs are developed by new CAST partner SoC Solutions LLC, a Georgia-based embedded products company and one of only three US firms with Approved Design Center Certification from ARM, Ltd. These and other IP products are already used in production or design-phase projects by a number of SoC Solutions customers."

* ChipX and Magma Design Automation Inc. announced the availability of an RTL-to-GDSII design flow, which the companies say is based on the Blast Create SA and Blast Fusion SA that supports the new CX6000 Structured ASIC product line.

Ophir Nadir, Vice President of Engineering at ChipX, celebrates seamlessness: "We worked very closely with Magma to optimize the CX6000 fabric and refine the flow to reduce structured ASIC development time and accelerate time to market. We're now able to offer our customers a swift and seamless path from RTL to placed gates to final silicon that takes full advantage of Magma's outstanding tool performance and our complete structured ASIC capabilities."

Meanwhile, Kam Kittrell, General Manager of Magma's Logic Design Business Unit, is also celebrating: "We're pleased to work with the structured ASIC leader to deliver two innovative products and flows that offer our mutual customers a low-cost alternative to ASIC design, and that enables them to implement high-performance designs in record time."

* CoWare Inc. announced the High Speed Downlink Packet Access (HSDPA) models in 3GPP Library for the company's SPW signal processing design tool.

Per the Press Release: "HSDPA delivers high data rates according to the transmission conditions by using adaptive modulation and coding (AMC) schemes. These cover a wide dynamic range in order to cope with the varying downlink radio and channel quality conditions at the handset. HSDPA adapts to these conditions by modifying the effective code rate, the modulation scheme, the number of codes used and power per code. The Hybrid ARQ (H-ARQ) mechanism is used in HSDPA to reduce the delay and increase the efficiency of the retransmitting data.

Ahmad Vafaei, Senior Staff Engineer at InterDigital Communications Corp., offers a testimonial: "We have been using CoWare's HSPDA Library as a reference tool for the 3GPP Release 5 standard. Having an executable reference for 50% of the modem functionality lets us focus on the differentiating components of our HSDPA algorithms."

* Kilopass Technology announced completed of the qualification of its XPM non-volatile memory (NVM) IP on TSMC's 0.18-micron CMOS logic process. The companies say, "The qualification involved passing a rigorous quality standard set by TSMC that includes over 1000 hours of high temperature operating life tests."

Charles Ng, Vice President of Worldwide Sales and Marketing at Kilopass, is delighted: "This achievement opens the door for chip developers to embed Kilopass' low-cost, field-programmable, non-volatile memory technology into a variety of silicon products that can be targeted to the world's largest dedicated semiconductor foundry."

* Mentor Graphics Corp. announced that ZTE, Ltd., "the largest listed communication device maker and national wireless supplier in China," has purchased XtremePCB.

Liu Zhang, EDA Director at ZTE, says it's a rational product: "XtremePCB provides a new platform for design process management, rational allotment of specialized design resources and can coordinate projects done in global dispersed locations. It is a new, highly-efficient solution to break the time limit of bursting PCB design tasks."

Henry Potts, Vice President and General Manager of the System Design Division at Mentor, agrees: "With XtremePCB, Mentor has answered a challenge posed by our customers who asked for a tool that allowed simultaneous changes from multiple team members. For our customers like ZTE, with aggressive time-to-market goals and either large, global design teams or technology specialized design resources, XtremePCB enables real-time, automated feedback for complex, PCB designs incorporating diverse design technologies."

* Magma Design Automation announced the successful tapeout of a 65-nanometer, high-density, low-power IC using Blast Create, Blast Fusion and Blast Noise. The IC was designed by Aeluros, Inc. and is "a high-performance, analog-intensive, 5-Gbps chip that was completed in less than three months."

Don Stark, Vice President of Engineering at Aeluros, is quoted: "We selected Magma for our first 65-nm design after achieving first-pass silicon success on a number of 0.13-micron designs. We needed to establish a reliable flow that could handle custom analog blocks along with standard-cell-based digital ASIC design. Magma's easy-to-use Tcl interface and automated flow allowed us quickly to repeat the entire design process every time we made a change to the RTL or constraints. This was key to helping us achieve the performance we needed without having to add engineering resources."

* Nallatech announced four new COTS FPGA products that the company says "combine the processing and I/O performance of Xilinx Virtex-4 FPGAs with enhancements to Nallatech’s DIME-II architecture including host interface improvements and enhanced clocking." The announcement includes the BenNUEY-PCI-X, a PCI-X DIME-II motherboard with on-board Virtex-4 FX FPGA and three DIME-II expansion sites. Three additional FPGA computing modules complete the new product set: BenBLUE-V4 dual-FPGA processing engine; BenDATA-V4 mixed memory and digital I/O module; and BenADC-V4 ultra-high-speed analog capture module.

Nallatech’s new products are available with the Virtex-4 LX FPGAs with high performance logic capability or the Virtex-4 SX family optimized for DSP performance.

Malachy Devlin, Senior Vice President. and CTO at Nallatech, is quoted: “These new Virtex-4 solutions are a significant milestone in Nallatech’s product development that enable developers to use the full potential of the Xilinx Virtex-4 architecture with our hardware, software and design tools. As a Xilinx Alliance Program Partner, Nallatech was able to combine critical enhancements during our engineering to the DIME-II architecture with attention to the latest industry standards/form factors and extended hardware and software support.”

* Open Core Protocol International Partnership (OCP-IP) announced availability of a set of English language compliance checks that formally describe the 'legal' constraints for signals on an OCP interface, for members. Per the Press Release, "The compliance checks eliminate the need for "best guess" verification by engineers making certain an OCP interface complies with the specification, assuring verification quality and IP blocks are compatible at system level."

"Compliance checks define a set of rules for the OCP specification. Constraints can be as simple as 'check that a signal is never 0' or may be complex temporal expressions. If no check is violated by functional and/or formal verification, the logic is proven compliant with the protocol."

"The compliance checks can be used in several different ways. Formal tools can use checks to be sure a design never violates them; proving OCP compliance. They can also use the same checks to cover the number of times a given restraint was hit. Functional verification tools can use the properties to build protocol checkers (in Verilog/VHDL/E/SystemC). By applying stimuli to the design under test (DUT) and verifying that protocol checkers are not reporting violations, OCP compliance is verified."

"Work on the compliance checks was completed by the OCP-IP Functional Verification working group including representatives from: Jeda Technologies, MIPS, Sonics, Synopsys, Texas Instruments, TransEDA, and Yogitech."

* Sequence Design announced enhancements to the company's PowerTheater toolkit for SoC power analysis and optimization; CoolPower; and CoolTime.

Per the Press Release: "PowerTheater now features gate-level time-based power analysis, providing a view of power dissipation as a function of time within a waveform display. The analysis also provides average power estimation numbers 2-3X faster than the existing flow. PowerTheater is now supported on the Intel Xeon platform as well running the SUSE 9 and RHEL 3 operating systems. It also provides strong links to CoolTime and other dynamic voltage drop tools for generating state information based on highest activity or highest power."

"CoolTime dynamic analysis run time has been improved by 2-4X without sacrificing accuracy. A 14-million gate design now takes about three hours (as compared to 10 hours earlier) to complete a dynamic analysis run on an Opteron machine. In addition, this design takes less than 16G of memory (half of what the earlier version required). CoolTime has an updated extraction engine, PRX, which improves the GDS extraction runtime by 3-5X. CoolTime now features voltage drop optimization (VDO) for individual blocks or full chip ... CoolPower now has the ability to transform a non-power gated design into a power gated one with a new technology, Power Gating Transformation (PGT) ... to reduce leakage current. PGT replaces all non-power gated cells in the specified modules or lists with the equivalent power gated versions, inserts switch cells to connect the power gated cells to real ground, connects the switch cells' control inputs to the specified Sleep_Control signals, and inserts interface cells on the nets driven by power gated instances but received by non-power gated instances."

* Synopsys, Inc. announced what the company calls "the industry's first unified current source model for accurate and efficient modeling of nanometer effects. Using Synopsys' Composite Current Source (CCS) modeling technology, designers are, for the first time, able to perform comprehensive timing, noise and power analysis using a single, open library model. Anchored by the industry's golden sign-off tool, Synopsys' PrimeTime tool, CCS modeling technology extends sign-off to include noise and power effects that are required for today's nanometer designs. Accurate physical IP models are essential for implementation and sign-off tools. With the move to 90-nm and below, many new effects in timing, noise and power need to be accurately modeled. Some of these effects are inter-dependent and can no longer be analyzed in isolation. CCS modeling technology allows designers to reduce design margin and deliver designs with higher performance, less area and lower power consumption. To speed adoption of CCS, Synopsys is providing a complete support system for library creation and validation including: open source Liberty modeling format, parsers, characterization/validation tools and guidelines."

Neal Carney, Vice President of Marketing for Physical IP at ARM, declared: "CCS is an innovative, unified model that addresses the industry's advanced process demands and new design styles. In addition to advanced Liberty models currently available for ARM Physical IP, we will be starting delivery of production CCS timing models for our Advantage and Metro 90-nanometer standard cell libraries in Q4 of 2005."

* In related news, Synopsys announced the company's Galaxy Design Platform now supports Composite Current Source (CCS) modeling technology. Per the Press Release: " The CCS modeling technology offers a unified solution to account accurately and efficiently for important new effects in timing, noise and power that become significant in designs at 90 nanometers and below. Having to account for these nanometer effects by adding design margins leads to over-design and extra iterations that can significantly impact designer productivity."

Nobuyuki Nishiguchi, Vice President and General Manager for Development Department 1, Design Methodology Group, at STARC, is enthused: "Using the CCS library models with the Galaxy Design Platform allows our customers to reduce design margins and improve productivity by taking advantage of the new voltage scaling and IR-Drop delay analysis capabilities."

* UMC announced a "comprehensive" reference flow for 90-nanometer SoC designs. Per the Press Release: "The silicon-verified, RTL-to-GDSII flow is based upon the foundry’s proven 0.13-micron low-power design package and incorporates timing closure, signal integrity, and power closure features to help SoC designers overcome 90-nanometer design-related challenges. Moreover, the added dimension of the latest DFM rules, applied within the reference flow, provides designers with new capabilities to achieve accurate, first-time-right designs and shortened time-to-market."

Ken Liou, Director of the IP and Design Support Division at UMC, is quoted: “SoC designers today require proven design support solutions to help them overcome the challenges of 90 nanometers and below technologies. The availability of our newest, comprehensive reference flow promises to help our customers navigate the most seamless path to 90nm silicon success by providing a feature-rich solution that is supported by the latest EDA tools and DFM methodologies.”

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What's your ASIC done for you lately?

* ZMD America has announced a temperature sensor integrated circuit (TSic ) plug-and-play LABkit that enables designers to evaluate up to four TSic sensors at one time. The company says the product makes development of temperature sensing applications "fast and efficient by allowing simultaneous display and evaluation of four signals: data, minimum, maximum, and average. Data can also be recorded in a text file that can be imported by other applications, such as Microsoft Excel software."

"The kit includes: 1) Four TSic 306 e-line sensor ICs with an accuracy of +/- 0.3 degrees C) with a 1-meter (ie, 3 feet) cable; 2) TSic LABkit USB Adapter for up to four temperature sensors, including a USB cable; 3) Recorder for data acquisition, display and recording software for PC/Windows. The TSic family of digital temperature sensors are completely tested and calibrated by IST AG to provide absolute accuracy when delivered to customers."