When shall we discuss the wisdom of releasing all the news for the year just prior to DAC?

AccelChip Inc. announced that it has added a singular value decomposition (SVD) core generator to its AccelWare Advanced Math Toolkit.

Per the Press Release: "Computationally intensive, sensor array processing enhances the ability to localize sources of energy, track sources, and mitigate the effects of noise and interference in challenging physical environments. Sensor array processing relies on the implementation of linear algebra-based, high-performance algorithms. Singular value decomposition is a highly robust algorithm that can always produce a result, even when other matrix inversion methods fail. The specific algorithm used in the AccelWare SVD core is designed to exploit the highly parallel structures available in FPGA and ASIC implementations."

Actel Corp. introduced CorePCIF into company’s PCI product family that also includes CorePCI and CorePCIX. CorePCIF, an FPGA PCI core, incorporates netlist and RTL versions with 33 and 66 MHz speeds, 32- and 64-bit bus widths, as well as target, master and target + master configurations. Actel has also added FIFOs at the application interface, CardBus and Compact PCI support, a simplified plug-and-play interface for PCI and an improved user test bench.

Agilent Technologies Inc. introduced a 64-bit version of its Momentum 3D-planar electromagnetic software. The company says the release "offers significantly improved accuracy, capacity and speed for design and verification of passive components and interconnects for RFIC, MMIC and PCB/hybrid/module design. The new 64-bit capability eliminates memory limitations and cuts EM simulation and verification time in half. For problems such as large interconnect, packaging and antenna-array structures, speed improvements of up to eight times have been observed"

Per the Press Release: "Until now, 3D-planar EM simulators have been available only for 32-bit processing, such as in personal computers. Thirty-two-bit computers are limited to up to a few gigabytes of memory, which also limits the size and complexity of the problems they can solve. Designers are often faced with simplifying their designs to stay within memory limitations, thus sacrificing accuracy. In many cases, EM analysis has simply been eliminated from the design process, incurring the risk of poor design performance and costly additional prototyping."

ARM and UMC announced the two companies have signed an agreement for ARM to provide its Artisan Metro IP platform for UMC’s 130-nanometer process technology. The licensed ARM physical IP products include the Artisan Metro low-power standard cells, I/Os and memories designed for low dynamic and leakage power. The companies say that all products are characterized for timing and power over an extended range of voltages, enabling customers to do accurate pre-tapeout simulation of multi-voltage designs.

Neal Carney, Vice President of Marketing, Physical IP at ARM, is quoted: "ARM has worked closely with UMC to implement our Artisan low-power platform products in UMC’s 130nm process to solve these challenges. Including these products in the Artisan Access Library program at no charge to IC designers enables sophisticated lower power design techniques to move into the mainstream of IC design for foundry customers."

AXIOM Design Automation announced the release of a complete SystemVerilog verification environment optimized for the AMD Opteron processor family. Per the Press Release: "MPSim is currently the only simulation product offering native integrated testbench, assertion based verification, coverage and debugging capabilities that leverages multi-processor hardware to deliver up to 6x faster verification performance. "

Atiq Raza, President and CEO of Raza Microelectronics and former President and COO of AMD, is quoted: "AXIOM has taken a leadership role in the functional verification space by taking advantage of multi-processor hardware to significantly improve simulation performance. MPSim provides a quantum gain in overall verification productivity necessary to overcome challenges faced by IC design teams working on complex SoCs."

Badru Agarwala, President and CEO of AXIOM, is also quoted: "In order to more fully maximize performance, a design has to be partitioned in such away that at every simulation cycle, each processor has balanced event activities. Since the event activity is determined by the test you are running, this is very difficult to predict at compile time. Using AXIOM’s patent-pending technology, partitioning is done at the run time and not at compile time. MPSim’s auto-learn mode can assist in generating an optimal partitioning scheme for each test, providing significant gains in performance."

Bellum Software announced availability of its first product, a visual tool for high-end design and protocol mapping for Electronic System Designs (ESD).

Per the Press Release: "Protocollum, offers the ability to create a high level architectural model that facilitates comprehension of architectural behavior by providing graphical visualization and allowing user interaction. [The] product enables an engineer to quickly specify, implement and validate communication protocols. It allows the engineer to capture and edit the rules, which define the protocol behavior. These rules become an executable model, which can then be run in a visual environment for design testing. Alternative approaches today consist mainly of interpreting English language specifications provided in printed documentation, leaving a tremendous amount of room for error."

Reed Christensen, founder and president of Bellum, is quoted: "What we have really set out to do with Protocollum is to offer a tool that allows system architects, designers, functional block implementers and test and validation engineers a way to communicate and simulate with the same design intent and high level descriptions. The software is really intended to be a workbench for the engineer, providing a basic foundation upon which any custom design can be created."

Bob Hunter, Vice President of Marketing and Sales for Bellum, is also quoted: "Protocollum gives system designers, test and validation groups the ability to visually simulate the passing of messages, including some time information, to get a head start on developing test strategies before the use of HDLs has even begun. As the functional blocks are later developed in a HDL, questions about how the original architect intended the design to function can be bounced off the original visual description and simulation, rather than having to refer to a written spec, which by then is probably outdated."

Berkeley Design Automation Inc. announced its initial product, PLL Noise Analyzer, which the company describes as "the industry's first noise analysis tool for circuits containing phase-locked loops (PLLs) The tool has already been adopted by leading semiconductor companies and is proven to dramatically improve their ability to accurately analyze noise before tape-out and to reduce silicon re-spins."

"PLL Noise Analyzer is a complete solution for noise and jitter analysis in analog integrated circuits and provides: fast and accurate phase noise and jitter analysis of full PLLs; quick identification of top circuit noise contributors; thorough analysis of circuit noise sensitivity; and easy integration with existing analog verification flows These benefits have been demonstrated on more than 35 customer designs in silicon technologies from 0.25 micron to below 90 naometers from the world’s leading integrated device manufacturers and foundries, including TSMC."

"The new product is based on the company’s proprietary Stochastic Nonlinear Engine, which allows fast and accurate analysis of the nonlinear, time-varying behavior of full PLL circuits at the transistor-level. PLL Noise Analyzer provides complete phase noise and jitter analysis for noise caused by all sources – random and deterministic sources that are inherent or external to the analog circuits."

Ravi Subramanian, Berkeley Design Automation's president and CEO, is quoted: "Analog circuits are pervasive today, even in the most 'digital' of designs. Our customers have told us that the greatest challenge in the design process today is to reduce the rate of silicon spins required to achieve volume production for these analog-rich ICs. Berkeley Design Automation has successfully delivered to the market a new generation of IC verification technology that has been customer-validated to provide greater predictability and certainty to the design of these complex ICs."

Cadence Design Systems and Oki Electric Co., Ltd. announced: "Oki has achieved five times faster design turn-around-time for its analog blocks than with its previous design methodology and has successfully completed 30 reusable analog IP designs using Cadence Virtuoso NeoCircuit technology." Not surprisingly, Oki's designers were looking to reuse the analog IP they had already created without having to manually repeat design work.

Ichiro Yamamoto, Senior Manager, Design System Department in the LSI Design Division of Oki Electric's Silicon Solutions Company, is quoted: "We are proud to announce that we have established a new design culture based on Virtuoso NeoCircuit with our proprietary IP templates. This Cadence technology allows us to compete more effectively with other leading manufacturers in this market segment."

ChipVision Design Systems announced the availability ORINOCO 2005.1, which the company describes as "the industry's first power optimization solution at the ESL. The new release features leakage power estimation capabilities and improved interaction with implementation teams using the ORINOCO Micro Architecture Specification. The estimation accuracy is also improved to be within 25 percent of gate-level estimates. Users now have access to an automated characterization flow to create libraries for pre-RTL estimation. In addition, a reference design example has been developed demonstrating 78% savings in average power and 63% savings in energy at the electronic system level."

Gary Smith, Chief EDA Analyst at Gartner Dataquest, is quoted from a research note: "As we were preparing for DAC, power was obviously the most important design issue. These tools reach from back end analysis tools to RTL power design tools and ESL power analysis tools. We will need them all."

Stan Krolikoski, CEO of ChipVision, is quoted in the Press Release: "The ESL leakage estimation technology enables leakage optimization at the earliest point in the design flow and helps design teams to significantly improve design productivity with the ORINOCO Micro Architecture Specification, which efficiently delivers low power constraints to RTL designers."

EdXact will introduce two versions of its standalone netlist reduction tool JIVARO for analog and RF circuits, and JIVARO-D for digital and mixed-signal circuits. The company says they are "the first netlist reduction tools able to handle accurately coupled capacitors, inductors and even mutual inductors. Both tools are standalone and complementary to all major EDA vendors’ tools, plugging into existing flows through transparent interfaces based on SPICE, SPECTRE, DSPF and SPEF file formats. This helps accelerating accurate post-layout verification necessary to reduce the number of re-spins, one of the biggest challenges in today’s semiconductor industry."

"JIVARO provides unparalleled netlist reduction capabilities and is the first tool able to handle all types of parasitic netlist components: R, RC, RLC, RLCK, coupled, decoupled, inductance, mutual inductance and substrate. JIVARO netlist reduction technology uses no heuristics and relies on mathematically proven algorithms. This leads to up to 99% reduction of parasitic components and file size, but the main goal is to boost the simulators by assuring the accuracy. Memory consumption reduction and simulation speedups between 10x and 100x have been confirmed."

Mathias Silvant, EdXact President, is quoted: "These results are now available for most existing tools, at the cost of a mere plug-in. Our JIVARO tools enable faster time-to-market through a reliable sign-off, easier analysis and the ability of full-chip simulation."

eInfochips, Inc. introduced ChipMaestro, which the company describes as "a portfolio of domain expertise, IP and services to support ASIC development in the consumer electronics, communications and computer peripheral markets. As a leading provider of ASIC design and verification services, eInfochips has brought together IP cores, verification IP and design and verification expertise to support clients over the entire lifecycle of ICs in these volatile markets. Because verification against industry standards, successful tapeout on complex processes and organized product life management are essential to success it today’s ASIC market, ChipMaestro goes far beyond conventional design services."

Tapan Joshi, Vice President of Marketing at eInfochips, is quoted: "ChipMaestro, incorporates our extensive domain experience, design and verification IP and customized design flow to the needs of specific markets. This makes it easier for customers to entrust their design, verification and sustaining engineering tasks to us."

Emulation and Verification Engineering announced a collaborative effort with Novas Software Inc., which now links EVE’s hardware-assisted verification platform with the Verdi Automated Debug System from Novas.

Per the Press Release: "Interoperability between the EVE and Novas product lines streamlines design debug with a single, unified interface for the development, verification and debug of SoC designs. The result is an optimized verification flow between EVE’s ZeBu and Novas’ Verdi that enables systems engineers and hardware designers to quickly track and correct causes of errant behavior before a design is fabricated. Additional integration efforts between the two companies will be announced later in the year.

Lauro Rizzatti, Vice President of Worldwide Marketing and General Manager of EVE-USA, is quoted: "Verification and debug continue to be the most time consuming activities of a design project,". "Successfully integrating our ZeBu with Novas’ debug capabilities helps streamline this effort and provides dramatic improvement in overall verification time and debug effectiveness."

Denali Software and GDA Technologies announced a cooperative effort to deliver a comprehensive IP platform for chip developers implementing the Advanced Switching Interconnect (ASI) standard.

Good words are in the Press Release: "Leveraging strong foundations in PCI Express solutions, they now provide SoC designers high-quality IP solutions for developing and deploying ASI designs in silicon. Primary elements of the platform include Denali’s PureSpec verification IP product for the ASI standard, and GDA’s Advanced Switching IP core (GPEX-AS) product. GDA’s Advanced Switching IP core verification environment uses PureSpec as one of the verification components that provides a complete verification framework with flexible stimulus generation. The environment is reusable for complete IP verification, system-level functional modeling, register transfer level (RTL) bring-up and integration, and system performance modeling. Denali’s fully functional backend model provides an executable specification for RTL integration with GDA’s Advanced Switching IP core. Use of PureSpec for Backend supports use in Verilog only or any other supported high-level verification language (HVL) environments, including C, and is easily ported for custom user interfaces."

Rajeev Kumar, ASI SIG president and Intel’s Advanced Switching Initiatives manager, is quoted: "With recent announcements by several silicon vendors, the industry support for ASI technology is growing as we move into an implementation phase marked by the availability of first silicon during the second half of the year," says "Design and verification products are a key part of this ecosystem. By providing these integrated IP solutions, Denali and GDA are helping enable designers to more efficiently deploy ASI designs that will help speed broad adoption of the standard."

Denali also announced last month that its PureSpec verification intellectual property (VIP) product is now available for the verification of USB designs.

Vic Juneja, Denali's Product Marketing Manager, is quoted: "Whether it's PCI Express, DDR, Flash or USB, our customers count on PureSpec as the most complete, high-quality verification solution for their designs. Seamless integration to all the latest testbench tools and languages ensures out-of-the box productivity, and when the pressure is on, they know that our world-class engineering and support staff is committed to their success."

Esterel Technologies announced a tool integrate IP blocks designed using Esterel Studio into system-level virtual prototyping environments using ARM RealView tools with MaxSim technology. The combined solution will enable developers of ARM technology-based SoCs to insert Esterel Studio IP executable specs into an ARM RealView system model. The Esterel Studio and ARM RealView co-simulation capabilities enable thorough IP debugging in a system context. Microarchitects and designers can further explore their IP microarchitecture options, measure real impact on system performance, and choose the optimal IP design to meet system requirements. Esterel Studio’s automatic generation of implementation-quality RTL not only saves RTL coding time, but also ensures that IP specification, virtual prototyping, and implementation views will be consistent at all stages of the design flow.

Chris Lennard, ESL Technical Marketing Manager at ARM, is quoted: "Esterel Studio technology’s formal IP specification and finite-state machine debugging environment complements the ARM RealView technology. The RealView simulation technology’s powerful profiling engines enable Esterel Studio technology users to quickly optimize their design before flowing directly to component implementation."

Giga Scale Integration Corp. (Giga Scale IC) announced that it has introduced "the industry's first comprehensive IC economic analysis engine. The feature is now available as an upgrade to the company's InCyte chip estimation tool, which can be downloaded in a free, time-unlimited version at ChipEstimate.com. InCyte's economic analysis engine enables designers and architects to transform a high level design specification into a complete IC budgetary quotation, determining final chip cost, long before committing engineering resources for implementation."

The analysis takes into account economic dimensions including: Yielded silicon die cost ('good chip' cost); IC package recommendation and cost; Test and assembly costs; NRE costs including masks, engineering, tools, and IP; and ROI analysis on IP and NRE investments The result of InCyte's economic analysis is a complete budgetary quotation and ROI analysis listing all of the factors which are built into the final product cost of an IC.

Per the Press Release: "With the addition of its new economic analysis engine, InCyte becomes the only commercial class EDA tool capable of providing designer teams with meaningful insight into the economics of IC design, enabling an understanding of the factors contributing to total chip cost, and allowing them to explore how IP, implementation, and chip architecture options can influence total chip cost."

Helic S.A. announced that . Micro Linear Corp. selected its VeloceRF EDA product for synthesis, modeling and verification of integrated inductors in its RFIC designs.

Bob Koupal, Director of Engineering at Micro Linear said: "We evaluated EDA tools that address integrated inductor modeling and design, concentrating on the accuracy of the models, their integration into standard design flows, and their component synthesis and verification capabilities. We concluded that for our needs, VeloceRF is the best-in-class design tool that combines all in one. Based on the commitment of the Helic team to our design needs, their technical expertise and high-quality support services they provided, we decided to adopt VeloceRF into our flow."

IBM, Chartered Semiconductor Manufacturing and Samsung Electronics Co., Ltd. announced that they are jointly developing design kits for the 65-nanometer base and low-power processes. The kits that consist of physical verification [design rule checking (DRC) and layout versus schematic (LVS) matching] and parasitic extraction (RCX) technology files. Additionally, the companies will also make available common SRAM kits for single- and dual-port memories, eFUSE kit and electrostatic discharge (ESD) kit. These initial design kits have been validated using a test chip.

Kevin Meyer, Vice President of Worldwide Marketing at Chartered, is quote: "At 65 nanometers, IBM, Chartered and Samsung have taken steps to define and develop process-optimized solutions in tandem with the design community. The customer benefits are the early availability of manufacturing-aware design solutions tuned for enabling the manufacturability of 65-nanometer designs."

Incentia Design Systems, Inc. announced availability of the 2005.05 release of its timing and synthesis software products-TimeCraft, DesignCraft, and DesignCraft Pro. The company says the release improves runtime, capacity and quality across the board, when compared to last year's (2004.10) release. The release also includes several new timing sign-off features for 90-nanometer designs and "strengthens low power synthesis and analysis capabilities to reduce chip area and power consumption."

Knowlent Corp. announced that it has added XAUI interface electrical verification support to its Opal Electrical Verification Platforms (EVPs), and is also introducing the Opal XAUI EVP. Opal also supports Serial ATA and PCI Express PHY (physical) layer interface verification.

Per the Press Release: "Opal EVPs comprehensively verify the electrical layer of the high- speed interfaces before tape-out to avoid any surprises post-silicon. Opal also speeds up the verification process by interactively and automatically verifying the PHY layer of PCI Express, Serial ATA or XAUI interfaces of electronic designs."

Manhattan Routing, Inc. announced what it describes as "the EDA software product that uses actual physical, logical, and timing information from various levels of physical hierarchy for the analysis and final optimization of hierarchical integrated circuit (IC) designs. The Hierarchical Physical Window/Optimization Cockpit (hPW/hOC) is a hierarchical timing closure system for chip design teams – both logical and physical designers – who are responsible for top-level chip integration. hPW/hOC enables design teams to analyze and optimize hierarchical physical designs without having to create the often inefficient and inaccurate models used to merge multiple levels of physical hierarchy. hPW/hOC "

"The key features of MRI’s new hierarchical physical design tool include: full 'flat' view of the entire chip for visual debugging of nets crossing physical block boundaries; hierarchical analysis to see inefficiencies in the implementation of nets and paths crossing physical block boundaries; hierarchical timing optimization across physical block boundaries for insertion and deletion of cells and nets at the most appropriate level of physical hierarchy; final functional and timing ECOs at the most appropriate level of physical hierarchy."

Tor Ekenberg, MRI President and CEO, is quoted: "Designs are getting too large to handle ‘flat,’ and design teams are paying a penalty in performance when tools cannot optimize across physical hierarchical boundaries. Furthermore, the integration of soft IP from multiple sources often dictates the need for independently implemented sub-blocks, driven by a set of boundary constraints developed at the chip’s top level, making the final integration at the chip level difficult when optimizing for performance. Our goal is to support customers both before and after a design has entered the timing closure phase and now we can facilitate flat as well as hierarchical physical designs."

Mentor Graphics Corp. announced a multi-year agreement with Siemens AG. Mentor will supply various tools to multiple Siemens business units operating in 40+ locations around the globe. Tools purchased under the agreement include Board Station, Expedition, XtremePCB, ICX and DMS, ModelSim, Precision Synthesis, Catapult C, the HDL Designer Series for ASIC and FPGA design; and Seamless for system design.

Johann Pöschl, CAE manager, Siemens PSE, Vienna, is quoted: "We chose Mentor Graphics as a global provider of design solutions because they have the broadest range of market-leading products in design areas that are critical to us. Mentor’s leading technologies will enable us to deliver cutting edge products faster and more cost-effectively."

Murata Manufacturing Co. Ltd. and Ansoft Corp. released a new device library for Ansoft's Nexxim based on Murata's discrete Capacitor/Coil Inductor products. The companies say designs such as WLANs, car navigation systems, and cellular base stations can incorporate the electrical responses and mechanical layout features for these parts within their large-scale PCB analysis. The library contains proprietary equivalent simulation models of Murata monolithic ceramic chip capacitors and coil inductors, and is available for free on the Murata website.

OEA International, Inc. announces new update to its SPIRAL a 3D inductor design toolset for designing and synthesizing on-chip inductors in analog and RF chips. The new version of SPIRAL includes a set of RF design engineering tools for doing common calculations in RF passive circuits. These include basic resistance and inductance series/parallel calculations and conversions, transmission lines on PCBs, wavelength calculations, resonance circuits and impedance matching circuit calculations; A new circuit simulation environment for quickly simulating the newly designed inductors into user definer RF spice circuits, such as tank circuits. The circuits are simulated with the fast OEA PANTHER linear spice simulator and the resultant S, Y, Z-Parameter and LRQ files are displayed on the PlotView interface; New solving algorithms for faster and more accurate substrate models, capacitance models, and RL skin effect models.

OEA International also announces a "major revision" to DP-PLAN dynamic power planning tool for pre-design of the core power grid on SoC designs. The new version includes a color-coded output of the voltage simulation outputs for user defined time slices and for global supply violation reporting. The company says that in this way, "the user can quickly identify problem areas in the layout and implement fixes by adding decoupling capacitors or changing the power grid. The color-coded display is provided by the OEA Post-Layout Workshop tool which allows for a global view or zoomed in detail view showing exact simulated values at any point on the power grid."

OEA International also announced "a 50X performance boost in the calculation of the resistance portion of a net for its popular NET-AN full 3D RCLK parasitic extraction tool of a network. The NET-AN tool, the fastest and most accurate full 3D extractor in the industry, is now even faster. With its higher resistance extraction speed, designers can extract entire power networks on a chip. This is particularly important for designers who work with advanced nanometer technologies where accurate power simulation is a major concern."

The Open SystemC Initiative (OSCI) announced the delivery of the SystemC Transaction-level Modeling (TLM) Standard 1.0. The new TLM standard defines application programming interfaces (APIs) and provides a library that implements a foundation layer upon which interoperable transaction-level communication can be built. The standard, along with the library implementation can be downloaded under the open source license at www.systemc.org.

Companies and organizations endorsing this standard include Cadence Design Systems, CoWare, Forte Design Systems, Mentor Graphics, Royal Philips Electronics, STMicroelectronics, Synopsys, Atrenta, Calypto Design Systems, Celoxica, ChipVision Design Automation AG, Synfora, Summit Design Automation, and OCP-IP.

Mark Milligan, OSCI president, is quoted: "The SystemC TLM 1.0 kit was unanimously approved by the OSCI’s Steering Group and Board for public release on the SystemC website. We are pleased to note that today it is in use at major companies, with the intent to use it as a corporate-wide standard."

Frank Ghenassia, OSCI TLM Working Group chair, is also quoted: "More than 50 TLM working-group members have worked for over two years in development and review of the standard APIs and open source library. OSCI is delivering a canonical TLM foundation that enables the industry to widely adopt Transaction-Level Modeling techniques."

PDF Solutions, Inc. and Synopsys, Inc. announced that they are working together "to achieve a new level of designer productivity for yield optimization. The two companies have combined their expertise in design and manufacturing to extend Synopsys’ Liberty library format for cell-based yield rated data. This data is compatible with PDF Solutions’ .pdfm format and pDfx process-aware DFM environment … Galaxy IC Compiler reads yield data through Liberty library format, letting Synopsys and PDF Solutions’ mutual customers achieve faster time-to-results and better quality-of-results, optimizing concurrently for timing, area and power, as well as yield."

Kevin MacLean, Vice President of DFM at PDF Solutions, is quoted: "The combination of PDF Solutions’ yield models with the Synopsys next-generation physical design system is a natural fit. For years, we have used our Characterization Vehicle infrastructure to accurately model and improve our customers’ processes. Wherever we can use our yield models to produce higher yielding designs, we help our customers even further. Using pDfx compatible yield optimization within Synopsys IC Compiler’s XPS – extended physical synthesis – technology delivers a new level of designer productivity for yield optimization."

Saleem Haider, Senior Director of Marketing for physical design tools at Synopsys, is quoted: "Working with PDF Solutions, we are now expanding this support into physical synthesis. By enabling concurrent optimization in IC Compiler, we are providing the top-of-the-line infrastructure necessary for considering yield as well as area, timing and power during the cell selection process."

Ponte Solutions Inc. announced that NEC Electronics Corp. will use its model-based yield analysis technology for internal research and augment its own process analysis systems.

Eiji Konishi, General Manager, Test Analysis Technology Development Division at NEC Electronics, is quoted: "NEC Electronics possesses vast experience in process analysis and has developed several internal methodologies to analyze and continually improve process technology. Ponte Solutions’ model-based technology has shown excellent correlation to our own analysis of random defects, and we look forward to using it for researching systematic defects in leading edge technologies."

Sierra Design Automation, Inc. introduced a new version of its Pinnacle product suite, and announced "multiple customer successes establishing Pinnacle as the EDA industry’s premier Design for Variability solution for 90 and 65-nanometer designs …With its Detailed Native Analysis kernel architecture, Pinnacle enables concurrent and scalable multi-mode/multi-corner analysis and optimization of all design metrics including timing, area, power, and signal integrity … IC designers using Pinnacle have experienced significantly improved design performance in much shorter design cycles when compared to last-generation physical implementation products that are encumbered by aging and inefficient architectures."

"Pinnacle’s DFV solution concurrently optimizes the various design metrics at multiple modes and corners throughout the implementation flow. The Pinnacle suite includes: a detailed native analysis kernel; a signoff quality timing analysis engine; and an adaptive variability engine."

John Fallin, General Manager, Design Solutions Center, NEC Electronics America, is quoted: "We used Sierra Pinnacle for prototyping and physical synthesis and clock tree placement of the complete chip. During the prototyping phase, Sierra was used to quickly analyze various floorplans and identify missing constraints. During the implementation phase, Pinnacle successfully exceeded the performance targets: operating 10 percent faster, using two watts less power, and reducing buffer count while concurrently optimizing at eight process corners. In addition to reducing the number of iterations, Sierra's run times were also very impressive: 30 minutes for a prototyping run and about four hours for an implementation run. Pinnacle enabled us to achieve high performance quickly by minimizing the number of iterations for large complex chips."

Jean-Pierre Geronimi, Director of CAD, FTM-Central CAD, STMicroelectronics NV, is also quoted: "For complex chips, current solutions require us to run multiple analysis and optimization incrementally for timing closure over all mode/corner combinations. Sierra Pinnacle eliminates this unpredictable process by enabling us to define all the mode/corners up front and simultaneously analyze and optimize all the design metrics at all mode/corners. We are very pleased with the correlation to sign-off, quality of results and runtimes we are experiencing when enabling multi-corner/multi-mode optimization on large and complex chips."

Sagantec announced the its Tool Set version 8 (STS8), which the company says includes support for 65-nanometer and 45-nanometer technology design rules, has been used to deliver 65-nanometer silicon, and is being used in an early 45-nanometer engagement. In addition, he 64-bit capability in STS8 supports the AMD 64-bit Opteron processor and the Intel 64-bit Xeon processor. The new version updates all Sagantec products: SiClone, SiFix, Companion, and Anaconda.

Silicon Dimensions, Inc. announced additional power analysis, custom wire-load model generation and predictive floorplan design in its Chip2Nite platform for early design planning tools. The company says the new capabilities deliver an expanded level of information to logic designers about the physical issues of a design, before implementation.

Per the Press Release: "Power analysis has been added to the post-placement analysis suite and is activity based, using data from SAIF files generated during simulation. The analysis detects power issues early for power-grid design planning and IR drop analysis. Chip2Nite 2.3 will also generate custom wire-load models based on physical properties of the design for more accurate timing prediction during the synthesis process. Finally, predictive floorplanning delivers physical information, such as pin locations, for early detection and identification of critical design issues."

Michael Naum, President and CTO of Silicon Dimensions, is quoted: "Design planning, placement and analysis are not just a good thing for logic designers to have as feature sizes shrink below 130 nanometers, they are crucial to design closure. Attacking problems on the front end eliminates iterations back and forth between the logical and physical designers and ensures right-first-time design."

Silicon Navigator Corp. announced its Library Smart technology that "revolutionizes EDA tool intelligence for its Rocket Framework (introduced in April). Library Smart technology enables a new class of design optimization using multiple libraries on the same die with simultaneous analysis of multiple PVT (Process, Temperature and Voltage) corners. Library Smart technology centralizes, organizes and manages library data with best practices to make ASIC design flows simpler. It gives EDA tool developers a head start on creating tools that bridge the growing disconnect between Semiconductor IP (Design Kits for a specific process node) and EDA tools."

"Library Smart is organized on the principles of design once and measure many times. Chip timing, power and packaging must be designed to work under worst case conditions. However, electronic consumer products involve an ever-increasing range of power profile modes, nominal temperatures and operating conditions dictated by the product environment. Optimization must operate under a range of user selectable operating points, not just at the worst case corners."

Silicon Navigator CEO George Janac is quoted: " Silicon Navigator closes the gap between the tacit knowledge that is embedded in today's Semiconductor IP but lost to EDA tools. Today there is no substitute for the tall-thin designer that understands all facets of both reference libraries and chip design. A high degree of design intent is often lost between Semiconductor IP designers and chip"

SMSC announced its USB2602 Hi-Speed USB hub and 15-in-1 flash media compound device controller, which combines two USB device controllers – flash media and hub – onto one chip.

Per the Press Release: "Since the device is USB based and serial cable length can reach five meters, design engineers have more flexibility to physically place digital photography connections where they are easy to access and convenient to use. Designers of products that interface with digital cameras are faced with several possible photograph transfer methods. By providing single-chip flash memory reader and USB hub port support, SMSC allows designers to use a single USB host port to open the gateway for digital photographs … increasing photo transfer speeds by a factor of 1.5 to 5 times, depending on flash media type."

SMSC also announced that Telechips has selected SMSC’s new USB2005 USB to ATA controller with Windows Media Digital Rights Management (Windows Media DRM) for its reference design serving the personal media player market.

Telechips CTO Hyun Min-Ho is quoted: "Telechips’ MP3 player reference designs are used in consumer applications around the world. With SMSC’s USB2005 controller, we will enable our customers to protect the copyrighted content stored in their players, which is top of mind in today’s designs of consumer downloadable, file sharing devices."

Sonics Inc. and TransEDA announced a collaboration that produced new versions of TransEDA’s Coverage and Coverability Analysis tool, and Automatic Protocol Verification tool optimized with Open Core Protocol (OCP) version 2.1 support. "This agreement highlights the active and ongoing collaboration between leading OCP intellectual property companies, such as Sonics, and leading-edge EDA companies, such as TransEDA, to further advance the process used for implementing OCP-based SoCs for improved engineering efficiencies. This alliance is part of the first phase in a new Sonics initiative to produce a reference methodology for SoC designs containing Sonics SMART Interconnects. Sonics chose TransEDA’s VN-Cover as its primary code Coverability Analysis tool, and imPROVE-HPK to formally check IP compliance with the OCP."

Ian Mackintosh, President of OCP, is quoted: "We are now seeing increasingly extensive collaborations such as the Sonics/TransEDA effort within the Open Core Protocol community which continues to add to the existing infrastructure being used worldwide. These collaborations highlight the importance and value of OCP as a defacto standard for the SoC design industry."

Summit Design, Inc. announced the release of its Vista 1.1 IDE for SystemC-based analysis and debug, which the company says includes a transaction-level modeling (TLM) viewer that allows for improved observability of system-level design behavior.

Per the Press Release: "SystemC verification and optimization has delivered a significant simulation speed-up, but the time benefit has been largely lost in debug …Vista enables designers to automatically view communication protocols and system-level interfaces, and to identify transaction function calls between blocks, without the time-consuming manual code instrumentation that has historically been necessary in SystemC design environments. The Vista TLM Viewer supports constructs critical to the hardware portion of system-level design with minimal set-up and short learning curve for both advanced and novice SystemC users."

Zvika Amir, Technical Marketing Manager at Summit Design, is quoted: "While Vista is an ideal choice for the advanced SystemC user, even novice users will find that they can be up and running within an hour, without any product-specific training … The developer has access to public domain design environments – such as Xemacs, GDB, GCC, OSCI – all through the single Vista IDE, and without the need for complex integration between them."

Synopsys, Inc. and IBM announced availability of synthesizable versions of IBM's PowerPC 405 and 440 processors as part of the DesignWare Star IP program. The IBM PowerPC processors will be distributed as fully soft RTL cores which can be implemented in any foundry process and configured to product design requirements including low power, high performance, or small silicon area. SystemC models of the PowerPC cores and associated peripherals will be distributed in Synopsys' System Studio architecture design and analysis environment. The processors are foundry-independent.

Synopsys also announced the addition of Serial ATA (SATA) verification IP to its DesignWare Library. SoC designers can use the SATA VIP to verify 1.5Gb/s and 3.0Gb/s generations of the SATA standard with direct and constrained random verification methods at the block and chip level. The company says the SATA VIP includes device controller and monitor models for verifying designs with a SATA host controller interface, support for third-party VHDL, Verilog and SystemVerilog simulators, Synopsys' VCS simulator, and Synopsys' Reference Verification Methodology (RVM).

Similarly, Synopsys also announced that its DesignWare IP for PCI Express supports the recently released PCI Express 1.1 specification, which includes several errata updates and improvements to increase the robustness of power management and error handling. The PCI Express 1.1 specification is fully backward compatible with the PCI Express 1.0a specification.

Guri Stark, Vice President of Marketing in the Synopsys Solutions Group, is quoted: "The quick support of the PCI Express 1.1 release demonstrates Synopsys' commitment to providing industry-leading PCI Express solutions that help enable the rapid adoption of PCI Express."

Tharas Systems, Inc. announced Virtual Connect, which the company describes as "the industry’s first RTL accurate virtual emulation capability, removing many of the traditional barriers to adopting emulation for system-level design and integration. When used in conjunction with the company’s new Hammer family of hardware assisted appliances (see below), Virtual Connect provides an easy-to-use, cost-effective and efficient way to perform hardware-software validation for embedded software development … uses a suite of functional accurate software models to provide application-specific platforms for graphics, networking and wireless market segments – Virtual-PC, a platform for graphics applications; Virtual-Net, a platform for networking applications and Virtual-3G, a platform for wireless applications."

"Using Virtual Connect, the pre-silicon SoC platforms and embedded systems can be verified while device development teams concurrently debug software. Software teams can port an operating system, develop device drivers and complete most of the software stacks several months before the silicon exists. Productivity features include shortened time to validation, enhanced ease-of-use and superior scalability without compromising cost-effectiveness. Virtual Connect incorporates an integrated, Transaction Based architecture based on the Accellera Standard Co-Emulation Modeling Interface (SCE-MI) to minimize communication overhead between the test environment and the design under development in the Hammer hardware-assisted appliance."

Rahm Shastry, President and CEO of Tharas, is quoted: "Virtual Connect facilitates an emulation environment wherein the driver code and application program directly interacts with the RTL design running inside Hammer. This allows users to verify their RTL, prior to tape-out, in the context of the embedded application software. This innovative approach significant reduces many of the barriers to adopting emulation and makes hardware-software co-development and validation a reality."

Tharas Systems also announced it next generation Hammer verification appliances.

Per the Press Release: "The Hammer S-Class and M-Class, the first two appliances in the series, are both based on a new custom processor chip design that enables run-time speeds of hundreds of kilohertz. The modular series maintains Tharas’ leadership with plug-and-play event accurate acceleration and extends utility into logic emulation. The rack mountable and single user Hammer S-Class addresses the needs of logic and system designers up to 16 million gates, while multi-user M-Class addresses the needs of designers up to 64 million gates. The new series also provides the industry’s first ‘virtual emulation’ capability, Virtual Connect, a software-model based approach that targets key application segments and offers embedded software validation capabilities to support concurrent hardware and software development."

Verific Design Automation announced that Renesas Technology Corp. of Tokyo has selected Verific's HDL component software for use in Renesas' EDA environment. Keiichi Suzuki, Senior Engineer, System level Design and Verification Technology Dept., LSI Product Technology Unit at Renesas, is quoted: "Verific’s commitment to customer support by the R&D team is commendable. Their dedication ensured that we got the features we needed, and made a significant impact with us."

Virtual Silicon announced that K-Micro has licensed the Virtual Silicon 90-nanometer Mobilize Digital Frequency Synthesizer PLL IP and will provide it as part of its standard 90-nanometer offering.

Sunil Baliga, Vice President of Marketing and Business Development at K-Micro, is quoted: "We use PLLs to cover a wide range of applications. K-Micro pursues partnerships with leading IP vendors to ensure that our customers have access to the most advanced and affordable technology and that we can provide the flexible designs the market requires. "

The VSI Alliance (VSIA) announced the release of the VSIA QIP Metric 2.0, developed by VSIA and FSA member companies. The metric is designed to address the need to measure quality of SIP cores in order to ease integration efforts, by helping IP vendors and IP consumers communicate based on an objective foundation.

Per the Press Release: " Several leading semiconductor intellectual-property (IP) vendors and users that are members of the VSIA or of the FSA will participate in a beta program that will begin on June 20, 2005. These companies include Agilent, Cadence Design Systems, Cirrus Logic, Conexant, Freescale Semiconductor, LSI Logic, Matrix Semiconductor, Mentor Graphics, NVIDIA, Philips and STMicroelectronics. In addition, a limited number of FSA and VSIA members can apply to become QIP 2.0 beta test companies – interested members are invited to apply for the beta program. In approximately six months, when the beta phase of the program is complete and input is incorporated, the Metric"

"Since its initial release in August 2003, the VSIA QIP Metric has undergone rigorous beta trials and version 2.0 reflects the feedback from this beta testing. The new version of the metric is easier to use than its predecessor and is more streamlined. New in 2.0 is a vendor qualification worksheet, applying to all IP from a vendor, covering development processes, quality assurance, design and support infrastructure, and other general corporate capabilities. This version also has simpler IP-qualification metrics covering documentation, deliverables, and information specific to the IP integrator as well as IP development practices. The VSIA QIP Metric 2.0 includes the newly added vendor assessment and the requirements for Soft IP have been restructured and revisited. Legacy worksheets, taken from the previous QIP Metric version, include software IP, verification IP, and hard IP worksheets, including digital and analog/mixed signals —these will be updated in future QIP Metric releases."

Mike Kaskowitz, General Manager of Mentor Graphic’s IP Division and VSIA President, is quoted: "Accurately assessing IP providers in order to determine IP quality continues to be one of the greatest challenges facing the SoC industry today. As the leader in creating industry standards for IP and SoCs, VSIA’s new QIP Metric provides the basis for measuring a core’s characteristics against an industry-approved list of attributes. As a leading IP supplier, Mentor believes that the metric will shorten the IP sales cycle and allow the Company to showcase their IP cores through an objective scoring system."

Kathy Werner, Freescale IP Reuse Manager, serves as chairperson over the VSIA and FSA groups working on the development of the Metric. These companies include: Cadence Design Systems, Freescale Semiconductor, LSI Logic, Mentor Graphics, Philips, STMicroelectronics and TSMC.

Xpedion Design Systems announced the latest version of its GoldenGate simulator, version 3.5, which the company says "uses 50 percent less memory while doubling the speed over the previous version. [As a result], design for yield analysis, such as Monte Carlo and sweeping process corners, become feasible for full transceiver radios."

Pete Johnson, director of marketing at Xpedion. "GoldenGate 3.5 enables designers to perform Monte Carlo analysis as part of the typical design flow to accomplish these goals. Furthermore, tighter specifications and shorter design windows are driving designers to implement a Best Practices RFIC design methodology, of which GoldenGate is a significant contributor. "

Xpedion Design Systems also announced validation of its GoldenGate simulator, which the company describes as "the first frequency-domain simulation technology to be validated as "Ready for IBM Technology" … a mark [that] identifies solutions that have been tested and validated for compatibility with IBM Microelectronics products and services by the solution developers and assures that these solutions are compatible with IBM Microelectronics products."

Pete Johnson, Xpedion’s Director of Marketing, is quoted: "Xpedion and IBM have worked closely together for several years to provide our mutual customers with leading RFIC simulation and manufacturing capabilities. IBM’s validation of our technology as a "Ready for IBM Technology" is a significant benefit to these customers."

Zuken, and CAD Systeme Kluwetasch (CSK) introduced a new MRP (Materials Requirement Planning) Link that the companies say "reduces design time, saves money, ensures product quality and facilitates management of the product development and manufacturing processes. By integrating CADSTAR tools with MRP SQL databases and establishing a bi-directional connection, users have access to a vast amount of additional component information for harmonization of part data in electronic designs and for the creation of highly customizable bills of materials. The MRP Link includes four main features: synchronization, parts management, history management, and BOM management."

Zuken also introduced its Spacing Synthesizer 2D and 3D routing checker for high voltage PCBs.

Per the Press Release: "Where voltages over 60V appear on a multi-layer PCB, designers are challenged with the problem of ensuring adequate separation of signal paths in the Z dimension of the board, as well as in the X and Y dimensions. This is particularly important where the board is to be used in environments that demand intrinsically safe performance, for example on oil rigs and in mines, where any insulation breakdown between layers can cause hazardous sparking. The traditional way of making the Z-axis checks is manual, often taking a designer up to six weeks to check a typical 4-layer board. This task has been reduced to a few minutes with a new Spacing Synthesizer tool that works within the CR-5000 enterprise-wide PCB design suite from Zuken. The tool enables engineers to assign groups of signals, and the distance between signals of the same or a different group, from within the system schematic during the design process. The signal groups can then be visualized in different colors within System Designer, the schematic capture module of CR-5000. A distance-matrix is automatically created that shows the design rules required in Board Designer, the tool-suite's board layout module. Until now, designers had to settle for completing design rule checks in 2D."