Things - tools & technology

April 8, 2005

** AC Microwave announced version 6.3 of the company's LINMIC Microwave and RF IC Design Suite. Per the Press Release: "In the release 6.3, the active device modelling has been extended for consideration and extraction of temperature dependencies of FET/HEMT model parameters. These new dependencies can be taken into account in DC, AC and harmonic balance circuit simulation when using LINMIC, so that active circuits can now be simulated including self-heating effects."

"Also, for a tighter integration of the main circuit simulator and the auxiliary tools like MLSIM and SFPMIC, new library elements are now available which reference to the structure file and the result file of an auxiliary component simulation. This allows to conveniently switch between the main circuit level and the auxiliary component simulation levels."

** Apache Design Solutions announced that Airgo Networks used Apache's RedHawk full-chip dynamic power integrity tool to achieve "first-pass silicon success" in developing their 802.11 next generation Wi-Fi chipset. Airgo says it "successfully taped out multiple designs using Apache's physical power integrity solution."

Derrick Lin, Senior Director of Engineering at Airgo, is quoted: "RedHawk enabled us to analyze dynamic voltage drop effects in addition to static IR drop analysis, resulting in more robust designs. RedHawk's ability to accurately detect potential chip failures caused by dynamic power supply noise prior to tape out has provided us with a high degree of confidence in our power grid design. RedHawk is an integral part of our sign-off flow."

** Atrenta Inc. announced a new line of EDA tools that the company says "substantially improve the risk/reward equation for companies developing electronic products, enabling them to create more innovative systems faster and more cost-effectively. Atrenta's 1Team Family represents a new class of design automation solution, called Predictive Development, which turns the expensive and error-prone activity of system development into a more predictable, manageable and reliable process. The 1Team Family also enhances engineering creativity, teamwork and productivity. The first member of the family, 1Team Implement, is now available."

Atrenta CEO Ajoy Bose is quoted in the Press Release: "This is a time of enormous challenge for system developers. Systems are becoming extremely complex as chip processes shrink below 130 nanometers and embedded software requirements soar. The convergence of consumer, computing and communications technologies is driving new economic and time-to-market pressures. And at the same time, electronics companies are grappling with the logistical complications of increasingly dispersed design teams. Atrenta's 1Team solutions give companies a way to rein in the risks and expense, and aggressively pursue innovative new product directions even in the face of these challenges. Predictive Development is a key to surviving and succeeding in this new era."

** Atrenta then announced availability of 1Team Implement, which the company describes as "a breakthrough design automation solution enabling electronics companies to plan, design and implement complex SoCs with far greater speed, accuracy and capacity than was previously possible. 1Team Implement is the first member of Atrenta's new 1Team Family of Predictive Development solutions. 1Team Implement is the industry's first unified physical planning, design and implementation solution, from architectural planning to RTL (register transfer level) design to initial placement. It provides SoC architects, logic designers and implementation teams with rapid, interactive guidance on the detailed physical implications of their designs, including timing, chip area, congestion and power consumption. 1Team Implement consists of three tightly-coupled products."

"1Team Architect is used by SoC architects to quickly evaluate key design trade-offs such as timing, die area and power. 1Team Architect is unique in providing SoC architects with rapid, accurate feedback on the key physical trade-offs of their block-level architectures, unlike the rough estimates provided by previous architectural-level solutions. 1Team Architect accommodates partial RTL (VHDL and/or Verilog), hard IP, soft IP, and chip specifications."

"1Team Create is used by logic designers to visualize the physical implications (including congestion, chip area and timing) of their RTL microarchitectures. 1T Create provides logic designers with precision guidance on the physical implications of their RTL designs. This is made possible by unique physical synthesis technologies that perform silicon virtual prototyping and floorplanning of a design at the RTL level--transparently and at interactive speeds."

"1Team Construct is used by physical implementation teams to quickly validate that timing and area projections can be met and to rapidly generate high-quality initial floorplans. 1Team Implement is built on industry standards, including Open Access database and .lib, SDC, LEF, DEF, PDEF interfaces. 1Team Construct is a major milestone among physical implementation solutions. It is the only commercial tool with the ability to perform automatic floorplanning of designs with large numbers of mixed-size macro blocks and standard cells, quickly generating high-quality, routable floorplans ready for place and route by existing back-end implementation tools."

** Celoxica Ltd. and the Japan Advanced Institute of Science and Technology (JAIST) announced they have developed a high-speed digital watermarking detection system with real-time operation across the Internet. The organizations say: "The joint research project used ESL design and C-based synthesis to accelerate watermarking algorithms in a hardware co-processor. The project resulted in a low-power solution that runs detection scanning 148 times faster than software only configurations. The complex algorithm design was implemented using Celoxica's DK Design Suite of ESL tools and RC Series hardware platforms."

** Renesas Technology Corp. announced that "following an extensive nine-month evaluation of power-analysis tools from multiple EDA vendors" the company has adopted Sequence Design’s CoolTime as its standard for dynamic voltage drop analysis on Renesas' next-generation SoC designs worldwide.

** Magma Design Automation Inc. announced what the company calls the "industry’s first 'Signoff in the Loop' flow for dramatic reduction in integrated circuit turnaround time. Magma’s Quartz RC, Quartz Time and Blast Fusion QT expands Blast Fusion into a self-contained IC design signoff system for timing and noise signoff. Developed to address customers’ needs for faster design flows at advanced geometries of 90 and 65 nanometers, Magma’s 'Signoff in the Loop' eliminates external signoff iterations and delivers correct-by-construction results, reducing signoff to a mere checklist activity."

Satya Gupta, Vice President of Engineering at Open-Silicon, is quoted: "We have used the Magma flow successfully on many tapeout designs to identify and correct signal integrity and OCV problems and are very pleased that Magma is incorporating more advanced capabilities to analyze and optimize the design for OCV at multiple corners and for multiple modes. We strongly believe that these features are required for advanced designs and the integration of these capabilities within the implementation flow will allow us to identify and fix problems faster and more efficiently."

** Magma Design Automation also announced the availability of its "next generation of design software, the result of its recent 18-month-long Cobra development initiative." The products comprise Magma’s 2005.03 release and include new products and enhanced capabilities to existing Magma software.

New capabilities in the Cobra release include: timing, noise and power 'Signoff in the Loop' with static statistical timing analysis; a single design platform for all IC silicon architectures, including FPGAs, structured ASIC and standard cell; design-for-test automation; integrated yield optimization; next-generation DRC/LVS (design rule checking/ layout-versus-schematic) architecture; automated hierarchical design flow and interconnect synthesis.

The 2005.03 release includes these new products: Quartz RC: Provides parasitic extraction and can operate as either a standalone tool or integrated with the Blast Fusion system; Quartz Time: Combines the static timer in Magma’s Blast Fusion with advanced timing capabilities to create a standalone signoff timing system; Blast Fusion QT: Provides capabilities that enable "Signoff in the Loop" timing analysis with concurrent optimization. This includes the ability to perform concurrent analysis and optimization with multi-corner operating conditions, multiple operating modes, on-chip variation (OCV) and the use of the advanced ECSM delay model; Blast DFT: Provides integrated design for test and advanced testability. Includes advanced BIST capabilities for logic and memory, including built-in self-repair capabilities; Quartz SSTA: Accounts for process variations and provides a parametric yield analysis capability for the design, providing parametric extraction and SSTA simultaneously.

Magma CEO Rajeev Madhavan is quoted: "The 18-plus months that have gone into this effort have delivered products that will significantly expand design options available to our customers as they do more and more design work at 90 and 65 nanometers. Many of the capabilities that the Cobra project delivers are the result of strategic acquisitions we have made in the last few years – small, early-stage companies that brought us talented technologists who could make key contributions to Magma’s design system. A key element in the Cobra release is the integration of timing, noise, power, test and yield signoff into the implementation flow."

** Silicon Navigator Corp. announced its Rocket Framework, which the company says is built on the OpenAccess database. Per the Press Release: "The Framework extends services beyond the core database to include a GUI, scripting, schematic and layout visualization, timing and Library Smart design data organization. The Rocket Framework supports a fully integrated static timing engine, the Rocket Timer, providing fast incremental timing analysis for a wide variety of OpenAccess applications."

Silicon Navigator says it is "closing the gap between closed proprietary EDA Frameworks and the capabilities available from the open sourced OpenAccess database. These new extensions and services enable a broader set of EDA applications on OpenAccess. Silicon Navigator leverages the OpenAccess database created by Cadence Design Systems Inc. with open availability from the Silicon Integration Initiative (Si2) and controlled by the community of member companies of the OpenAccess Coalition."

"The Rocket Framework provides many essential services required by front-end applications, layout, optimization, and analysis based on OpenAccess. The platform is targeted at software developers, IDMs, and EDA companies that wish to jump start the development of proprietary tools or customized IC design flows on OpenAccess. Silicon Navigator originally developed the Framework for its own applications but as the company kept encountering customers that needed the same set of baseline services, it made the dramatic decision to make these capabilities available to others and allow customers and partners to integrate their software at the API level."

** Synopsys, Inc. announced that Atmel Corp. has adopted the latest release of Synopsys' VCS RTL verification tool.

Eric Costello, Design Methodology Manager at Atmel, is quoted: "VCS' NTB has been easy to adopt and has proven itself by providing increased productivity in validating our designs. The availability of native verification technologies in a single tool allows us to easily deploy advanced verification techniques. In one recent project, we found benefit by relying on NTB's constraint solver to create complex test sequences versus the traditional approach of writing directed tests. Using the tool to exercise the part saved us time and resources, found bugs and let us run more cycles."

** UpZide Labs AB and Tensilica, Inc. announced a development agreement "in the area" of VDSL2 data-path design. Under the agreement, UpZide says it will develop a reference design utilizing multiple Xtensa LX processors from Tensilica to implement the VDSL2 (second-generation Very high-speed Digital Subscriber Line) standard.

Per the Press Release: "Because the standard is evolving, it’s essential that the VDSL2 data-path component be designed with the flexibility required to adapt to all possible changes. By designing with highly configurable Xtensa processors rather than RTL (register transfer level code), and by extending the instruction set to handle the data-intensive demands of the VDSL2 standard, UpZide will be able to make available for license a fast, efficient, and programmable solution for this rapidly growing market. The VDSL2 standard provides broadband connections at speeds of up to 100 Mbps symmetrical, which is fast enough to deliver the "triple play" applications of voice, data and video to a wide audience. This technology is seen as key to delivering VoIP (voice over Internet protocol), VoD (video on demand) and HDTV (high-definition television) simultaneously over standard telephone lines."

** Zenasis Technologies, Inc and Agilent Technologies Inc. announced that Agilent has successfully used Zenasis' ZenTime, cell-based timing optimization tool in developing a 90-nanometer SOC design, intended for next-generation desktop printer and imaging applications.

Jay McDougal, IP Design Methodology Program Manager for Agilent's Imaging Solutions Division, is quoted: "ZenTime is a unique EDA tool that helped us improve SOC performance to meet our design objectives. With ZenTime, we saw significant timing improvement on one of our most challenging IP cores. Using ZenTime helps Agilent maintain its SOC integration and performance leadership."