0-In Design Automation announced new products within the company’s Archer Verification system will support Accellera’s SystemVerilog 3.1a design constructs and IEEE-1076 VHDL. The company says the new products add to 0-In’s support of standard languages including IEEE-1364 Verilog and Accellera’s Property Specification Language (PSL). Mentor Graphic’s purchase of 0-In Design, announced last week at DAC, does not seem inclined to change these initiatives.

Steve White, 0-In’s President and CEO, is quoted: "0-In is actively and firmly committed to open standards and interoperability. Our customer base, with over 15,000 assertion simulation licenses and 5,000 formal verification licenses, continues to help us prioritize rollout of standards support. Now customers using SystemVerilog and VHDL will have access to the industry’s most widely used tools and proven methodologies for reaching verification closure."

Accelerated Technology, the Embedded Systems Division of Mentor Graphics Corp. announced the release of the Nucleus PLUS real-time kernel for the SHARC ADSP-21161 Processor from Analog Devices, Inc.

Per the Press Release: "Embedded developers using the SHARC ADSP-21161 now have a royalty-free solution in which to build a variety of digital signal processing-intensive applications. A member of ADI's second-generation SHARC Processor family, the ADSP-21161 provides highly optimized 32-bit floating-point performance to complement the scalable and fast Nucleus PLUS kernel and gives users a powerful solution for the development of their embedded applications. Additionally, the source code and no-royalty business model from Accelerated Technology provide maximum value for developers building high-volume, price-sensitive applications."

Meanwhile, Mentor Graphics announced that it has acquired compiler technology and engineering resources from Atair GmbH. Terms of the deal were not disclosed. Neil Henderson, General Manager for the Embedded Systems Division at Mentor Graphics, is quoted: "The addition of the Atair compiler technology will help round out Mentor's product portfolio in this area and position us to lead the way in meeting the challenges of proliferating dual-core embedded systems."

Actel Corp. announced what the company describes as its "most flexible and comprehensive tool suite to date," the Libero Integrated Design Environment (IDE) version 6.0.

Per the Press Release: "The streamlined IDE seamlessly integrates the industry's best third-party design tools and delivers unprecedented flexibility and efficiency for today's complex, time-sensitive FPGA designs. Imparting enhanced functionality and performance, all editions of Libero 6.0, including its free Silver edition, now include Synplify Actel Edition (AE) software, Synplicity's industry-leading synthesis tool specially optimized for Actel's flash- and antifuse-based FPGAs."

Saloni Howard-Sarin, Tools Marketing Director at Actel, is quoted: "As FPGAs continue to push the envelope in terms of performance, we recognize that third-party software companies like Synplicity and Magma Design Automation possess the expertise to provide top-notch front-end design tools. By joining forces with these companies, Actel is able to leverage this superior technology and offer customers the best mix of design tools the industry has to offer."

Libero customers may purchase Synplicity's Synplify Pro AE, and users can access a full version of Magma Design Automation's PALACE (Physical and Logical Automatic Compilation Engine) physical synthesis tool directly from within the Libero 6.0 interface.

I spoke with Saloni Howard-Sarin just before DAC. She laughed when she told me, "This launch was carefully timed, so I would still be in the office before taking maternity leave for our first baby. I wish I could go to DAC next week however, as I’m hearing there will be a number of new companies launched and I would like to see them."

"Actel’s new Libero announcement reflects our strategy in the FPGA space, which is different [than our competitors]. Our strategy has been one of going with OEM vendors for tools for our customers. FPGA customers love Synplicity’s tools, and today people are also demanding tools for physical synthesis. They’re relying more and more on leading-edge companies like Magma to provide those tools."

"Therefore, we’ve gone with a deliberate strategy of including Magma’s tools as part of our new Libero suite. We feel that Magma probably understands best - of the big EDA vendors - how to transition from the ASIC business model to the FPGA business model. They’ve been a great company to work with throughout the integration process. Of course, we’ve always enjoyed working with Synplicity."

Aldec, Inc. announced a release of the company’s Riviera-IPT product with support for ARM. The company says this version of Riviera-IPT provides high-speed co-verification and debug environment for complex embedded software/hardware co-development utilizing the ARM processors.

The companies say that using Riviera-IPT’s hardware accelerator with ARM will allow engineers to run their designs at MHz speed, which is not possible using software models alone. In contrast, while emulation provides similar speed, that strategy is limited by the inability to debug the design on the fly and requires a lengthy set-up. Riviera-IPT is described as providing the best of both situations as demand for better system-level verification solutions increases.

Altium Ltd. announced updates to the autorouter in the company’s board-level design system. Protel 2004's PCB autorouting technology (the Situs topological autorouter) now features a "comprehensive" Routing Setup Report that will assist designer in troubleshooting rule violation and improve routing completion rates. The report analyzes the defined design rules and reports on potential routing conflicts and routability problems. The designer can rectify errors early in the board routing process and have more ability to deal with differing design geometries via routing alternatives, which include orthogonal routing strategy options and a re-cornering pass.

AmmoCore Technology, Inc. announced new capabilities for Fabrix that support increased design complexity and higher clock rates while delivering reduced die size. Larry Yamada, AmmoCore’s Vice President of Asia Sales and Marketing, is quoted in the Press Release: "We are starting to see increased market acceptance for our Fabrix solution. Our customers are beginning to realize the benefits of the improved quality of results and die size reduction with our production-proven software - especially as they are facing the challenges associated with designs greater than four million gates."

Per the Press Release: "The Fabrix enhancements significantly improve Quality of Results in the areas of timing, area and productivity, as well as further improve the customers’ return on investment by providing reduced die size and shorter design cycles."

Apache Design Solutions announced the SkyHawk automated constraint-driven power grid generation and optimization engine for nanometer SoCs. The company says the new product will help chip designers determine power grid requirements early in the design process, refine the power grid as the design evolves, and analyze it at every stage of the design cycle. SkyHawk uses the same simulation kernel as Apache’s RedHawk-SDL signoff dynamic power-grid tool (validated in TSMC’s reference flow 5.0 - see below).

SkyHawk aims to prevent power integrity issues that may be difficult to fix late in the design cycle. SkyHawk generates multi-layer, multi-region power grids while honoring all routing, power, and blockage constraints. It also considers the effects of simultaneous switching logic and I/Os when determining the amount and type of routing resources needed by a power grid. The company says that SkyHawk, combined with RedHawk-SDL’s vectorless-dynamic engine, generates power grid designs that ensure "silicon-proven accuracy."

Cadence Design Systems, Inc. announced its First Encounter Global Physical Synthesis (GPS), which the company says integrates silicon virtual prototyping and second-generation global physical synthesis technology into a single environment. Per the announcement, designers can now create much larger chips than was practical with "older" methods. The new technology is described as "completing" the Cadence Encounter digital IC design platform's core technology portfolio.

Per the Press Release: "First Encounter GPS leverages Cadence RTL Compiler's global-focused synthesis for speed and capacity and Quality of Silicon. Unlike first-generation physical synthesis approaches that optimize a single logic path at a time, global physical synthesis optimizes timing for many paths concurrently. This dramatically reduces the compute effort needed for design convergence and enables silicon success even on very large blocks in short design schedules. First Encounter GPS supports both RTL-to-placed gates and netlist-to-placed gates design styles."

Hisaharu Miwa, Department Manager of the EDA Technology Development Dept. at Renesas Technology Corp., is quoted: "Very large SoC designs are becoming difficult to complete using block sizes of 1 or 2 million gates. The chips must be divided into so many blocks that assembly becomes impractical. First Encounter GPS enables practical design closure on larger block sizes that we would not even have tried in the past. It changes how we look at large-scale SoC design."

Cadence Design Systems, Inc. and ASML MaskTools announced a "multi-year, multi-million dollar" software licensing and joint development agreement for resolution enhancement technology (RET) software solutions. The two companies say they will work together to develop a "tightly integrated" design for manufacturability flow. As DFM is such a hot topic these days, look for further news regarding this particular collaboration.

Under the agreement, Cadence will license and co-develop two ASML MaskTools software packages: MaskWeaver, a full-chip RET and optical proximity correction (OPC) mask and optimization solution, and LithoCruiser, a lithography process analysis and optimization solution.

Meanwhile, Cadence says it will become the sole worldwide distributor for MaskWeaver, while both Cadence and ASML MaskTools will distribute LithoCruiser to their respective EDA and manufacturing customers. The products will be offered as standalone and integrated solutions within the Cadence Encounter and Virtuoso design platforms. Not surprisingly, the Press Release says, "These best-of-breed solutions will bridge the design-to-manufacturing gap and accelerate the rate at which customers can reach 65 nanometers and below in their semiconductor process."

CAST, Inc. and Innovative Semiconductors, Inc. announced a relationship under which the companies say they will deliver a "complete, easy-to-use package for physically implementing USB 2.0 On-The-Go (OTG) connections in a variety of electronic products."

The new offering is said to combine the CAST USB2-OTG core with the Innovative SL210 USB 2.0 OTG mixed-signal PHY hard macro core, and is intended to give designers the functionality of CAST’s host/device controller core and the mixed-signal circuitry of Innovative’s physical layer transceiver together in a single configuration. The new package will be available in July 2004 for several ASIC technologies, and will include full documentation and a complete test environment.

Celoxica announced "advanced" synthesis technology for the SystemC language. Celoxica says its new Agility Compiler synthesis SystemC directly to high-density FPGA and programmable SoC logic and generates RTL VHDL and Verilog for SoC design.

Per the Press Release: "The Agility Compiler takes in SystemC and outputs optimized EDIF netlists for high-density programmable logic devices from Actel, Altera Corp. and Xilinx. The Agility Compiler also generates VHDL and Verilog RTL output to support SoC synthesis tools. Integrated with Celoxica’s popular DK Design Suite of tools for co-design and co-verification, the Agility Compiler extends the benefits of Software-Compiled System Design to users of SystemC."

Jeff Jussel, Vice President of Marketing for Celoxica, is quoted: "By bridging the gap between design idea and product reality, we’ve addressed one of the major bottlenecks to SystemC adoption and enabled companies to realize a return on investment in their SystemC modeling, design and verification efforts."

Denali Software announced that Agere Systems used Denali’s PureSpec verification software to design its ET1310 native PCI Express Gigabit Ethernet controller. William Billowitch, senior manager of IP Reuse Design & Development at Agere, is quoted: "With the personal computer market transitioning to PCI Express at a very fast clip, our customers have called on us for very high quality, ultra high reliability system-on-chips with PCI Express capability. Functional verification of these systems is critical. For the PCI Express interface, we choose Denali. The quality and completeness of Denali’s verification IP helped us produce a high-quality product on-time."

Emulation and Verification Engineering (EVE) announced a collaborative effort with Novas Software, Inc. aimed at enhancing interoperability between the products from the two companies. Through the collaboration, the companies say they will reduce tool complexity, accelerate user learning curves, and optimize the verification flow. The joint effort was coordinated through the Novas Harmony Program and marries EVE’s ZeBu hardware/software co-verification platform and Novas’ debug platform to provide a single, unified interface for verification and debug. The companies also say that further development will integrate elements of the Novas debug platform as the cockpit for ZeBu.

Per the Press Release: "The integrated EVE/Novas solution will provide an intuitive way for system engineers and software developers to track, understand and correct causes of errant behavior before a design is implemented."

FishTail Design Automation recently announced that Toshiba's System LSI Division has purchased the company's Focus tool for generating false and multi-cycle paths, and will use it in its System LSI chip-implementation projects.

Masato Nagamatsu, senior manager from Toshiba, is quoted in the announcement: "We continually run into problems with incomplete timing constraints during chip-implementation. Prior to Focus, we had to manually sift through timing reports and establish whether timing problems were real. This was a tedious, error-prone and time-consuming task, taking several weeks. By deploying Focus, we expect to be able to significantly reduce the time we spend during timing closure. In addition to the productivity improvements, on a 300K gate design being implemented, we also saw a 7% reduction in random-logic area through the use of Focus. The area reduction was made possible because of the false-paths identified by Focus."

Helic S.A. announced an IP and EDA tools collaboration with Cadence Design Systems in which both companies say they aim to become the "springboard for the design of next-generation wireless semiconductor products."

As part of the agreement, Helic’s VeloceRF, Helic's tool for modeling and synthesis of on-chip and in-package inductances, becomes a third-party extension to the Virtuoso custom design platform. Additionally, Cadence says it will license Helic's PolyRadio RFIP to serve as a Wi-Fi reference design in the Virtuoso platform. The Helic IP is comprised of RF silicon blocks including a low-noise amplifier, a fully integrated power amplifier, and voltage-controlled oscillator, linear direct-conversion mixers and programmable analog baseband circuitry. Helic says its RFIP has already been fabricated and validated on a series of "leading" SiGe BiCMOS foundry processes.

Yorgos Koutsoyannopoulos, Helic CEO, is quoted in the Press Release: "VeloceRF and PolyRadio have found a perfect match in the Virtuoso platform. We are very upbeat about partnering with the world leader in RFIC EDA solutions. Over the coming years, demand for integrated EDA platforms, smarter flows, more functionality and automation particularly in RF and multi-GHz applications is expected to explode. Smartly packaged intellectual property blocks accessible through these flows will be the way to go. Helic, with its combined VeloceRF and PolyRadio offering, brings additional functionality to the Cadence Virtuoso platform. Through our combined efforts, we will be able to offer a more compelling solution for semiconductor manufacturers seeking to capitalize on this emerging opportunity."

I met with Helic at DAC and won a cup of coffee from VitalComPR because I pronounced Koutsoyannopoulos’s last name on my first attempt. Of course, Helic’s CEO won nothing as he could not pronounce my last name at all.

Magma Design Automation Inc. announced that Blast Fusion’s built-in parasitic extraction capability has been validated by UMC for its 0.13-micron process. Ken Liou, Director of UMC's Design Support Division, is quoted: "UMC continues to expand its design resources in order to provide the most comprehensive support for our customers developing complex SOC designs on our advanced processes. The validation of Magma’s Blast Fusion parasitic extraction capability on our 0.13-micron technology means that customers can now access a valuable EDA tool suite to help them achieve silicon success in a shorter amount of time."

Meanwhile, Magma Design Automation and PDF Solutions, Inc. have agreed on the preliminary terms whereby the two companies will create an IC implementation flow with embedded capabilities for design for manufacturability (DFM) and design for yield (DFY). This new flow intends to enable IC designers to optimize the manufacturability and yields of chip designs earlier in the design process, without needing additional DFM or DFY tools or processes. We’ll all be watching.

Nitin Deo, Magma Vice President of Marketing, is quoted in the announcement: "To ensure high-quality silicon, it is critical that IC designers incorporate yield data into their complete implementation flow, especially for nanometer technologies. Magma’s implementation system delivers this capability because it is fully integrated from RTL to GDSII. By inserting PDF Solutions’ industry-leading yield and process-aware DFM technology directly into our solutions, we will provide our customers the fastest path from their RTL to high-quality silicon. Designers can use their familiar design flow with no need for cumbersome and capacity-limiting data exchange."

Monterey Design Systems announced the availability of its Dolphin physical implementation system on the Red Hat Enterprise Linux operating system for AMD 64-bit Opteron processors.

Alan Feinberg, Vice President of Marketing and North America Sales at Monterey, is quoted in the Press Release: "By porting our software to a 64-bit architecture we’re able to offer higher capacity, better performance and faster turnaround time for the most demanding physical implementation applications."

Also from Monterey - The company announced a new design planning technology that it says "automates the placement of hundreds of hard macros and significantly reduces the die size of SoCs - and integrates seamlessly into all major back-end design flows."

Per the Press Release: "AFP Technology improves profit margins for SoCs in high volume applications, where every square millimeter of die size is critical. Recent customer projects have validated that die size depends primarily on the quality of standard cell and hard macro placement. For SoCs with many hard macros, traditional design planning methods involving manual placement or early-generation automatic block placers produce sub-optimal results, including poor utilization and larger die size. By introducing AFP Technology into the design planning process for designs with as few as 20 hard macros, Monterey customers have achieved considerable die size reductions. Monterey’s AFP Technology easily integrates into physical design flows from Cadence Design Systems, Synopsys, and Magma Design Automation without requiring changes to intellectual property (IP) or libraries. Similar quality of results and die size reductions have been achieved in all three major flows by AFP Technology early customers."

Finally from Monterey - The company announced that Mobileye N.V. has implemented all major blocks of their latest SoC using Monterey’s physical design tool suite. Mobileye’s product line aims to automate on-board driver assistance systems that can be made available to every driver. The chip referenced in the Press Release, called EyeQ, was designed using Monterey’s Calypso silicon virtual prototyping and Dolphin physical implementation systems, Mobileye says it was able to generate dense, compact block designs for its complex EyeQ technology, and therefore produced a smaller chip at a very attractive price.

Pulsic Ltd. announced a new release of its Lyric Physical Design Framework. Release 4.2 is described by the company as providing a common platform for all tools supported by a shape-based methodology, giving users "a huge leap in flexibility and the required quality of results to meet performance targets."

Pulsic says the Lyric Framework is expanded vertically to address more tasks within the physical design flow, and horizontally to address specific design areas, such as datapath, DRAM/SRAM and analog/RF. The new product expands Lyric from shape-based routing to include placement across a range of target designs including analog, mixed-signal, memory, datapath, and custom digital. Additionally, the extended single, shape-based data model supports floorplanning, automatic/interactive placement, and automatic/interactive routing with concurrent built-in RC extraction to control timing and signal integrity in a unified environment.

Mark Williams, Founder and COO at Pulsic, is quoted in the Press Release: "Designers can now take a design from just cell and netlist data, through floorplanning, place, route (all auto/auto-interactive/ interactive) to their final sign-off stage all within the single Lyric platform. Its extensive checking tools are extremely powerful due to the data model being shape-based."

Similarly, Pulsic Ltd. announced Lyric Analog, which the company says is aimed at the analog and analog RF market. Lyric Analog is described as a "sub-set of the advanced Lyric Physical Design Framework specifically developed to meet the exacting needs of pure analog and analog/RF designs. This new module will initially include interactive and semi-automatic transistor placement, fully automatic and interactive routing and signal integrity."

Mark Williams, Founder and COO at Pulsic, is quoted in this announcement as well: "There are an increasingly large number of designs in the pure analog and RF space, where the customers are looking for a more affordable solution. These designs are relatively small in capacity but need to consider a distinct set of design criteria, such as matched and shielded differential signals, resistance and capacitance constrained paths and current densities."

Real Intent Inc. announced that Verix version 4.3 is now shipping with support for PSL, Accellera's Property Specification Language. Prakash Narain, Real Intent's President and CEO, is quoted in the Press Release: "The growing acceptance and demand for PSL, Accellera's new verification standard, has been a catalyst for our business. With this release of PSL support in Verix, we allow designers to apply the power of formal analysis in their flow and leverage standards that protect their investments and improve their verification ROI."

Summit Design, Inc. says it has expanded its Visual ESC package with the latest Cycle Callable Models (CCM) for ARM processors, a new AMBA AHB bus model, and the ARM RealView debugger. Visual ESC is part of Summit's Visual Elite functional modeling, design, and verification environment, and is a HW/SW co-verification platform with an integrated instruction set simulator (ISS) models for target architectures.

Summit's Visual ESC package also includes a new AMBA AHB bus model based on the new Cycle Level Interface (CLI) standards from ARM supporting transaction-level communication interfaces. The bus model, as well as the ARM processor ISS includes built-in performance analysis functions that trace and monitor bus traffic, data transactions and software execution threads. Therefore it’s possible to analyze busload and contention, latencies and SW instruction distribution during HW/SW functional simulation. In addition, the ARM ISS model is now integrated with the ARM RealView debugger, and therefore provides a multi-process HW/SW debugging platform.

Tim Holden, EDA Relations manager of ARM, is quoted: "Summit's ESC solution enhanced with support for our fast CCM processor models and the RealView debugger provides a fast and cycle accurate system development environment for both hardware and software developer. The ability to offer a comprehensive set of SystemC modules, along with the verification tools, is of great benefit to our mutual customers."

Synopsys, Inc. and ARM announced that the two companies are collaborating to deliver AMBA AXI verification IP through Synopsys’ DesignWare Library and DesignWare Verification Library. Synopsys and ARM say they will develop the AMBA AXI verification IP and make it available for no additional charge to the 25,000+ design and verification engineers who currently use DesignWare Library products.

John Cornish, Director of Product Marketing at ARM, is quoted: "We are working closely with Synopsys to ensure that the AMBA AXI technology-based DesignWare solution is fully compliant with the XVC methodology, enabling, ARM to deliver verification vectors that run ‘out of the box.’ By adding AMBA AXI Verification IP to the DesignWare Library products, Synopsys is helping ensure that designers creating AMBA AXI technology-based SoCs will have a high-quality, low-risk solution with strong technical support that scales from block-level verification through subsystem to complete SoC verification."

Meanwhile, Synopsys and Altera Corp. announced an agreement for the establishment of Synopsys Professional Services resources to support the HardCopy design center. The companies say the collaboration will establish an "advanced and optimized" back-end design flow and provide access to expert physical design resources that will complement Altera's existing HardCopy design center.

Additionally, designers can now use Synopsys' Galaxy Design Platform front-end flow to design their Altera Stratix FPGAs. The agreement is said to build on work already in progress for the development of a new timing-driven HardCopy back-end design flow based on Synopsys' Galaxy Design Platform, which has been optimized for Altera's FPGA-to-HardCopy migrations.

Tharas Systems, Inc. announced the Hammer 100 simulation accelerator for functional verification of complex ASIC and system designs. I had a chance to speak several weeks ago with the executive team at Tharas. They told me, "Tharas is delivering hardware for chip verification. Using hardware verifications tools in the past have required a lot of work - they’ve been neither easy to use, nor to adopt. In contrast, however, we’ve always wanted our systems to be transparent to the users, which is our main differentiation. Ours is a fresh approach to hardware verification."

I would invite you to read these excerpts from the Press Release describing the technology, which the Tharas team referred to in their comments: "The patented Hammer custom-processor architecture compiles Verilog, VHDL or mixed-language designs at 20 to 50 million RTL gate equivalents per hour on a single workstation - the fastest compilation of in the industry. The modular compiler enables design changes without full compile for even faster design preparation time. Design blocks or chips can be compiled separately and linked later to allow for pre-compiled modules (PCM) that can be managed and linked during compile time. Only changed PCM is incrementally compiled and re-linked during source-level engineering change orders. Incremental change can be done to either the design or testbench source."

"The Hammer 100 now includes up to 4 gigabytes of memory to increasing run-time performance up to two times faster than the earlier generation Hammer systems. The Hammer 100's built-in arithmetic operators further speed commonly used computational functions in computing, graphics and DSP applications."

"Advanced Trace Data Conversion for Debug Productivity Debug of complex designs involves the time-consuming process of converting gigabytes of trace data files into waveforms. The Hammer 100 now offers advanced debug facilities in concurrent, parallel and progressive waveform conversion to industry standard formats such as fast signal database (FSDB), value change dump (VCD), or VCD post-processing data (VPD). The Hammer 100's concurrent waveform conversion capability offers dramatic reduction in time-to-waveforms, by compressing trace data and concurrently converting trace data to waveforms."

"Designers can start debug with the portion of the waveforms with all signals while more waveforms are being generated as accelerated verification proceeds. Parallel waveform capability allows conversion of compressed simulation trace data dumps across a network of workstations in parallel. Progressive waveform converter can be used during active debug sessions, allowing a verification engineer to save relevant trace data only if and when simulation fails or does not meet expected results. The user may choose to save signals for a certain number of clock cycles or trace data sets at the time the simulation failed walking backwards."

TeraSystems, Inc. announced low-power, advanced optimization, and mixed-language options for its TeraForm front-end product, which are designed to assist developers with chip design issues efficiently and early in the design cycle. TeraSystems also released an updated version of TeraForm, which includes TeraForm Diamond, TeraForm Emerald and TeraForm Crystal configurations.

The low-power option lets users analyze leakage power at the RTL level and optimize micro-architecture for timing, area, and power. Designers can profile their designs without having to generate huge numbers of vectors for dynamic power analysis. The optimization option is designed to reduce the time associated with critical paths in datapath-intensive designs. The mixed-language option allows design teams to qualify RTL written in a combination of Verilog and VHDL.

Per the Press Release: "Mixed-language designs are far more likely as designs become more complex at 90 nanometers and below, and include IP from multiple sources."

Also per the Press Release: "The TeraForm Diamond configuration includes RTL Design Consultant (RDC) technology and an environment for building and analyzing RTL with respect to logical, timing, physical and power attributes of the design. TeraForm Emerald includes RDC technology and an environment for building and analyzing RTL with respect to logical, timing and power attributes. TeraForm Crystal includes timing analysis, constraint analysis and a visualization environment for analyzing results generated by Diamond or Emerald. The TeraForm front-end environment uses the high level of abstraction provided by a TeraGate library for fast runtimes, capacity greater than 15 million gates, and intuitive, high-level visualizations."

TransEDA has announced the availability of a Coverability Analysis Option to the company's VN-Cover Coverage Analysis tool. TransEDA says it thereby extends the scope of its coverage tools, bringing "New Dimensions in Coverage" to actively guide designers to full coverage from specification to functional coverage, across design languages and simulation platforms. The new Coverability Analysis option to VN-Cover results from the "synergy" of TransEDA's advanced Coverage Products and TNI-Valiosys' innovative Formal Verification Technologies.

Per the Press Release: "In order to fulfill their test plan, most verification engineers have coverage targets to meet. In practice it is generally not a problem to reach 90-percent structural coverage, but it often turns out to be a real burden to find stimuli that trigger the remaining uncovered areas. Meeting the coverage goals can hence be a painful and time-consuming task. Moreover, setting a coverage target questions how coverage is measured. A coverage-driven verification methodology strongly relies on the correctness of coverage measurement. Accuracy is therefore critical to set reachable coverage goals and insure convergence of random or pseudo-random tests."

Modesto Casas, head of Worldwide Sales and Marketing at TransEDA, is quoted: "The ultimate goal for designers is to get 100% coverage. TransEDA has a unique solution to this problem by integrating formal techniques into our leading coverage tool. Where standard code coverage passively tells designers what is covered, our Coverability Analysis option actively guides them on how to reach full coverage using their existing design environment and without having to integrate multiple vendors' tools nor needing formal verification knowledge."

TriCN announced the immediate availability of "the most area and power-efficient" PCI-Express PHYs in the industry. The company says its PCI-Express PHYs incorporate a two-tiered configuration approach towards the highly scalable PCI-Express interface technology.

Per the Press Release: "The first is a true X1 lane configuration that allows for the most efficient design possible for companies striving to minimize area and power (such as consumer product applications). This is a departure from many competing offerings that disable multi-lane PHYs that penalize customers with unnecessary overhead. For multi-lane configurations, TriCN employs a scalable, multi-lane design architecture starting with a X4 implementation and scaling to a X32. With the addition of multiple lanes, the TriDL digital sampling technology enables significant area and power gains versus comparable analog designs, while also providing exceptionally reliable data transmission across the link. TriCN PCI-Express PHYs are PIPE 1.0a compliant, and include the SerDes, the PIPE logic and the I/Os. The products are delivered as a hard macro requiring no further RTL synthesis."

Meanwhile, TriCN also announced the verification of its PCI Express PHY using Denali Software's PureSpec verification IP. The companies say that "PureSpec's analysis verifies that TriCN's PCI Express PIPE macro is fully functional within a complete PCI Express environment, including Link Level Controller, Root Complexes, Bridges and Switches."

David Lin, Vice President at Denali, is quoted: "We've worked with TriCN on numerous high-speed interface designs and we continue to be impressed with their technical expertise and commitment to customer success. TriCN has developed a robust design and verification methodology. We are very pleased that PureSpec delivered value in their verification flow and enabled delivery of a very high-quality end-product."

TSMC & Friends introduced TSMC’s Reference Flow 5.0 with a view to power and integrated design by hosting a nice party on a boat docked in the San Diego Marina on Tuesday evening at DAC to help announce/celebrate the various technology partners who have made contributions to the flow.

Best described by the Press Release: "Taiwan Semiconductor Manufacturing Company announced Reference Flow 5.0, the industry's first reference flow providing critical power closure and integrated chip-to-package design for nanometer SoC integrated circuits. Building on the powerful dual-track methodology, which was built around major EDA developers Cadence Design Systems and Synopsys, Inc. and introduced in Reference Flow 4.0, the new reference flow includes significant new power management, design-for-test, design-for-manufacturing, flip-chip design capabilities, and the first integrated chip-to-package design capabilities. In addition to Synopsys and Cadence, Reference Flow 5.0 includes specialty tools from Mentor Graphics Corp., and newly introduced EDA partners Apache Design Solutions, Atrenta Inc., and Optimal Corp."

"TSMC's fifth-generation reference flow specifically addresses an increasingly problematic element of IC design: power closure. Driven by high-performance applications requiring smaller chip size and longer battery life, designers continually target smaller process geometries for leading-edge chip designs. Because of their small size, increased design complexity, and high performance needs, these SoCs typically display both active and leakage power levels that are dramatically increased at the 90nm-and-below technology nodes. This presents numerous design challenges. To address these challenges, TSMC Reference Flow 5.0 provides solutions for dynamic power optimization, leakage power optimization, and static and dynamic IR final verification. This suite of power optimization and analysis capabilities is the most robust methodology ever assembled for an advanced technology process."

** Edward Wan, Senior Director of Design Services Marketing for TSMC, offered up one of several comments issued on behalf of the new flow: "Reference Flow 5.0 carries on the TSMC Reference Flow tradition of providing timely solutions to the key issues facing leading-edge chip designers. There's no other foundry methodology available to encompass all of these issues in a single integrated chip-to-package design flow."

Friends included in the flow - Apache, Atrenta, Cadence, Optimal, and Synopsys - all released coincident announcements at DAC, each embellished with celebratory comments from TSMC spokesman Ed Wan.

Apache Design Solutions announced that TSMC has adopted RedHawk-SDL as an "integral part" of its new Reference Flow 5.0. Per the Press Release: "Today’s industry-leading semiconductor devices contain tens millions of transistors. Hundreds of thousands of these switches may be toggling at any given time, creating highly dynamic power demands that may result in a power integrity issue. RedHawk-SDL provides full-chip dynamic voltage drop analysis and global I/O SSO (Simultaneous-Switching Output) verification, to ensure that all this activity does not compromise the design."

** Edward Wan, Senior Director of Design Services Marketing for TSMC, is quoted in the Press Release: "As process technology moves to 90nm and below, power integrity due to dynamic supply noise has become a key factor in chips meeting frequency, voltage, and yield requirements. By adding Apache’s RedHawk-SDL to Reference Flow 5.0, we are able to offer power closure for next-generation SoC designs."

Atrenta Inc. announced that TSMC has adopted Atrenta’s low power and ERC products as "key enabling technologies" in the TSMC Reference Flow 5.0. The company says that both products are part of the unified Atrenta platform that includes tools for clock domain analysis, DFT analysis, constraints analysis, and automated functional analysis.

** Edward Wan, Director of Design Services Marketing at TSMC, is also quoted here: "We have been working closely with Atrenta and are impressed with Atrenta’s low power and ERC solutions and their rapid response in addressing our issues. Incorporating these products into the power closure and the chip integration flows in Reference Flow 5.0 completes these important tasks, enabling designers to achieve faster time to market for their products."

Cadence Design Systems, Inc. announced the integration of the Cadence Encounter digital IC design platform and the Cadence Allegro system interconnect design platform into TSMC's Reference Flow 5.0. Per the Press Release: "This reference flow includes key Cadence technologies for low power design and chip-package design that enable higher productivity and improved design quality. Supporting designs targeting TSMC's 90-nanometer process technology, the reference flow is the latest milestone in the long-standing design chain collaboration between TSMC and Cadence."

** Edward Wan, Senior Director of Design Services Marketing for TSMC, also appears here: "TSMC and Cadence have been collaborating closely to provide complete design solutions available for our mutual customers. TSMC Reference Flow 5.0 delivers a comprehensive offering that uses advanced Cadence solutions to address critical 90-nanometer issues such as power closure and IC package optimization. The result is a methodology that manages nanometer-scale design issues while delivering faster time-to-volume for low-power and high-performance designs."

Optimal Corp. says it’s a "key player" in the integrated chip and package co-design methodology introduced as TSMC’s Reference Flow 5.0.

Optimal says it has contributed three tools to the TSMC Reference Flow to provide power and timing closure in the IC and package co-design phase. PowerGrid-DC provides the IR drop, current density and SPICE netlists, while PakSi-E and SIDEA are used to extract package parasitics and generate timing information in SDF (standard delay format).

** Edward Wan, Senior Director of Design Services Marketing for TSMC, is quoted here as well: "As we geared up to handle the next generation of system-on-chip designs, it became clear that power closure would become a dominant technical issue. The ability to provide power closure through to the package design increases the reliability of the design, greatly enhances the design experience and accelerates time-to-market."

Synopsys, Inc. and TSMC announced that TSMC Reference Flow Release 5.0 incorporates "unique features and innovations of Synopsys' Galaxy Design Platform for designs at 130 nanometers, 90 nanometers and below. Synopsys' Galaxy Design Platform addresses design challenges that include power management, power and signal integrity (SI), design for manufacturing (DFM) requirements for yield enhancement, testability, design planning, and advanced flip chip capabilities in the TSMC Reference Flow Release 5.0."

** Edward Wan, Senior Director of Design Services Marketing for TSMC, is not surprisingly quoted yet again: "Synopsys has made immense contributions to the TSMC Reference Flow since version 1.0. We've worked collaboratively to ensure that Galaxy's unique power optimization, testability, DFM handling for yield improvement, power integrity and advanced flip chip capabilities work seamlessly in our 5.0 Reference Flow. Many of our customers haven't had to face these issues until recently. At 130 and 90 nanometers, power and manufacturing concerns are becoming as important as timing and signal integrity. The Galaxy Design Platform addresses these issues."