Cadence Design Systems, Inc. announced that Azul Systems implemented a high-density, high-speed design using the Cadence Encounter digital IC platform and RTL Compiler. The design was targeted to a "leading edge process" from TSMC.

Scott Sellers, Vice President of Hardware Engineering, CTO, and Co-founder of Azul Systems, is happy: "Utilizing CeltIC provided us an advanced signal integrity analysis capability. Coupled with RTL Compiler's concurrent global synthesis capabilities, this helped us achieve our aggressive frequency target. Working with Cadence gives us access to a preeminent design flow, leading edge tools and foundry support for our nanometer design."

PolarFab is talking technical and says it has "improved its 6-inch complementary BiCMOS (c-BiCMOS) RFBC/ABC3 processes to provide reduced die sizes and decreased design times. Both processes are used for a variety of analog and mixed-signal applications such as low-noise amplifiers, photodetector integrated circuits (PDIC), line drivers, and power management. Three digital cell libraries have been added to the RFBC/ABC3 standard cell library portfolio in order to reduce design times and increase first pass success for designers. The first library, optimized for synthesis, place and route (SP&R), is a 72-cell library that includes logic (Verilog) and synthesis views."

QualCore Logic was also talking technical when it said the company "has added two new IP cores to its product portfolio. The first is a digital Serial ATA Host Controller with OCP Interface. The second is high-speed analog dual serializer/deserializer (SerDes) core for SXGA/SXGA+/UXGA application that utilizes a Low Voltage Differential Signaling (LVDS) I/O. This core is used for flat panel displays in laptop computers. Both cores are intended for use in system-on-chip (SoC) designs. They have taped out and have been implemented in silicon." As always in IP, the proof's in the (silicon) pudding.

Sequence Design announced that S3 Graphics has "benefited" from the company's PhysicalStudio optimization software by reducing timing and noise violations on S3 Graphics' designs.

Michael Shiuan, Vice President of Engineering at S3 Graphics, is ecstatic: "When we increased the complexity of our graphics processors, we needed a tool that could handle the timing and signal integrity challenges inherent in higher gate-count designs. Building this complex 130-nanometer, high-frequency, 10 million+ gate SoC required a state-of-the-art push down flow approach for top level optimization. PhysicalStudio is the best chip- and block- level signal integrity analysis and optimization tool we have used – the number of timing and noise violations it eliminates is extraordinary!"

SMSC says it has expanded its line of Environmental Monitoring and Control (EMC) solutions to include "four new temperature sensors: the EMC1001, EMC1002, EMC1023 and the EMC1033, providing industry first solutions that address these customer issues with the highest levels of accuracy while conserving board space." Clearly, the customers are happy.

Mark Beadle, Director of EMC Product Marketing at SMSC, is quoted in the Press Release: "Our customers are faced with ever-increasing power consumption as systems become more complex, faster and heat sensitive. This has put a tremendous burden on engineers working to get quality products to market quickly and efficiently. It’s our job to provide customers with complete thermal and hardware management solutions, and with today’s announcement we are delivering greater functionality and more differentiated features than the standard solutions the market currently has to offer." Sounds like Beadle et al are indeed doing their job.

Synopsys, Inc. announced the "general availability of the industry's first verification intellectual property (VIP) suite for the AMBA 3 AXI protocol. The DesignWare VIP for the AMBA 3 AXI protocol, created through the collaboration of industry leaders Synopsys and ARM, builds on the success of the AMBA AHB interface, the most widely adopted de-facto standard interface already used in hundreds of embedded processor-based designs. The AMBA 3 AXI protocol is the next-generation of the AMBA family of on-chip interface protocols, targeted at high-performance, low latency designs."

John Cornish, Director of Product Marketing at ARM, is quoted: "The launch of Synopsys DesignWare VIP for the AMBA 3 AXI protocol highlights the increasingly wide adoption of interfaces from the AMBA 3 protocol family. Having it available within Synopsys' DesignWare Library and Verification Library instantly puts a high quality verification solution for the AMBA 3 AXI protocol into a broad customer base with world-class Synopsys support." In closing, Synopsys & ARM are happy as well.