The mother of all press tours ...

Hey, I'm as happy as the next guy to know there's been yet more progress in the march towards world peace as evidenced by the joint news that was put out last week from:

Clearly something was up because the e-mail with the related press materials for the requisite phone briefing included 3 PowerPoint presentations and 8 Press Releases.

But anybody who opened this e-mail and saw 11 attachments – particularly amidst pre-DAC Press Release mania – just closed the e-mail and went off to get another cup of coffee.

After re-caffeinating, I wrote back to the person who had sent the e-mail and asked for some guidance. I said I'd open one attachment, maybe 2 – but not 11, so tell me which one to look at.

As I didn't get a response until after the phone briefing had come and gone, I posed the same question to the guys on the phone when they called. This is who all was on the call – Kevin Meyer, John Martin and Walter Ng from Chartered, Walt Lange from IBM and Neal Carney from ARM. As it turns out, they asked me to open the 3 PowerPoint presentations one at a time, and one by one the relevant spokesperson walked me through the slides.

I have to say that actually worked out okay and there was still time for Q&A afterwards. However, I didn't open a single Press Release during the call. I saved that exercise for afterwards, and even then it was enough to make your eyes glaze over.

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* IBM and Chartered Semiconductor Manufacturing announced a further expansion of their jointly developed 90-nanometer process platform with the addition of common design enablement support. The additional support includes power-optimized, manufacturing-aware libraries; low-power EDA reference flows; and design kits for critical high-speed connectivity interface standards, including USB 2.0 and PCI Express^.

Expanded support – provided by ARM, Cadence Design Systems, Magma Design Automation and Synopsys – augments the existing ecosystem of support for the IBM-Chartered 90nm base process platform and underscores the companies’ expanding efforts to help early adopters reduce design risks and achieve fast volume ramp for their leading-edge system-on-chip (SoC) products.

Extending ARM’s current library support for the 90-namometer base process at IBM and Chartered, ARM’s Artisan Metro low-power libraries – a suite of standard cells, memory generators, and general purpose and specialty I/O cells developed and optimized for low-power design – are immediately available as the initial foundation library offering to support low-power processes and third-party low-power reference flows.

Cadence, Magma and Synopsys are collaborating with Chartered and IBM to provide low-power reference flows for the 90 nanometer common platform. The validation process involves running both a high-level block-based design and more complex SoC design through the reference flows to demonstrate important low-power design techniques while achieving electromigration, signal integrity and timing closure requirements. Upon availability, the reference flows, coupled with the libraries will support a variety of power reduction methodologies – multi-voltage threshold design, voltage scaling and voltage islands – and therefore help enable a more efficient and effective way to design to the 90-nanometer low-power process platform.

* IBM, Chartered Semiconductor Manufacturing and Samsung Electronics Co. announced that Samsung has licensed the 90-nanometer common design enablement technology utilized by IBM and Chartered. As a result of this license agreement, Samsung, IBM and Chartered can make available common foundry design kits and tests chips as well as work with design enablement parties to provide future third-party solutions, initially for the 90-nanometer baseline and low-power CMOS logic processes.

The announcement builds on Samsung’s licensing rights to the jointly developed 90nm process platform, with the goal of expanding customers’ flexibility to source designs among the manufacturing facilities of Samsung, IBM and Chartered. Samsung also collaborates with IBM, Chartered and Infineon for the development of 65nm process technologies.

KP Suh, Executive Vice President of System LSI Technology Development at Samsung Electronics, is quoted: "The synergy created from the joint technology process development program at 65nm has increased our confidence in the common platform. The 90nm design enablement platform complements the leading-edge production capacity available at Samsung and increases sourcing flexibility for customers. We firmly believe the common platform to be a truly attractive manufacturing model for the Nano-Age. The arrangement that we have with IBM and Chartered to provide mutual design enablement and increase compatibility among our fabs will be a great benefit to our internal users and external customers."

Steve Longoria, vice president, Semiconductor Technology Platform for IBM, is quoted: "As an electronics leader, Samsung adds valuable system-level understanding and expertise to the common platform that should benefit our customers, both in terms of the underlying process as well as the overall open enablement solutions we offer. We are pleased to have Samsung involved at multiple levels of this collaboration and look forward to providing increased open and collaborative solutions to the marketplace through our common 90nm enablement platform."

Kevin Meyer, vice president of worldwide marketing at Chartered, is quoted: "The transition to 90nm and 300-millimeter manufacturing has drawn the industry to deeper and broader levels of collaboration. As a global leader in digital convergence products and leading semiconductor manufacturer, Samsung’s participation at 90nm is an endorsement of the common platform approach. We look forward to leveraging their breadth of experience and expertise to jointly provide customers with even greater levels of sourcing flexibility and more robust design enablement solutions."

* Cadence Design Systems, Inc. announced the next steps of its ongoing collaboration with IBM and Chartered Semiconductor Manufacturing to provide advanced solutions to enable SoC designs at 90 nanometer. The three companies are jointly developing a low-power design reference flow for the IBM-Chartered 90-nanometer common process platform. Based on the Cadence Encounter digital IC platform, this RTL-to-GDSII reference flow will enable higher productivity and improved quality-of-silicon (QoS).

Steve Longoria, Vice President, Semiconductor Technology Platform for IBM, is quoted: "IBM and Chartered continue to drive a common platform for 90-nanometer designs. This low-power reference flow is developed in collaboration with Cadence to tackle the complex design challenges of 90 nanometer and below. The combination of the IBM-Chartered 90-nanometer process technologies and Cadence's low-power design methodology will help address the challenges that designers are facing in doing power-efficient IC designs."

Jan Willis, Senior Vice President, Industry Alliances, at Cadence, is quoted: "Extending our collaboration with IBM and Chartered in support of their common platform exemplifies how Cadence is working across the design chain to provide solutions to accelerate 90-nanometer design for the mainstream."

Kevin Meyer, Vice President of Worldwide Marketing at Chartered, is quoted: "Cadence is providing advanced low-power technologies for 90-nanometer design that will enable customers to maximize the benefits of technology and choice offered by the common platform."

* Magma Design Automation Inc. announced its collaboration with IBM and Chartered Semiconductor Manufacturing to offer an RTL-to-GDSII reference flow for low-power designs targeting the IBM-Chartered 90-nanometer low-power common process platform. The low-power reference flow enables designers to develop low-power SoCs while leveraging the flexibility of dual-source manufacturing at IBM’s and Chartered’s 300-millimeter facilities and is expected to be available by the end of second quarter 2005. The IBM-Chartered 90 nanometer common platform is already supported by Magma’s IBM-Chartered Design Enablement Kit for the base process platform.

Kevin Meyer, vice president of worldwide marketing at Chartered, is quoted: "Our strong working relationship with Magma continues to play an important role in developing the ecosystem for the IBM-Chartered 90nm common process platform. Magma’s unified database approach and focus on complete integration is a key element of their low-power reference flow and compelling value proposition for SoC designers."

Steve Longoria, Vice President, Semiconductor Technology Platform for IBM, is quoted: "We are very pleased to expand our platform offerings with the Magma low-power reference flow. As our ecosystem continues to expand, it is critical that we offer our customers quality choices for their marketplace; low power is clearly a key element of our platform strategy."

* Synopsys, Inc. announced it is collaborating with IBM and Chartered Semiconductor Manufacturing to offer a low-power reference flow for the 90-nanometer common process platform. The Galaxy Design and Discovery Verification platforms are the foundation of the reference flow, extending the existing solution by addressing power reduction, signal integrity and DFM issues. The low-power Synopsys reference flow spans the complete design process, and then design sign-off is supported by the PrimeTime SI, Star-RCXT and Hercules tools using a common set of technology files available from IBM and Chartered.

Steve Longoria, vice president, Semiconductor Technology Platform for IBM. "The Synopsys low-power reference flow for our 90-nm common platform enhances customer choice and is further evidence of our intent to provide a comprehensive, open and broad-based offering to the marketplace."

Kevin Meyer, vice president of worldwide marketing at Chartered. "The 90-nanometer process platform we have developed with IBM is well suited to a wide range of applications. Synopsys provides key enabling design technologies that should help our customers quickly and confidently design their devices while realizing the full capabilities of the IBM-Chartered common process platform. In addition, Synopsys brings recognized expertise in timing closure, power optimization and DFM to the design effort with their low-power reference flow."

Glenn Dukes, vice president, Synopsys Professional Services, is quoted: "We have been working with IBM and Chartered for many years to provide complete solutions for our customers. This reference flow combines expertise from all three companies, allowing designers worldwide to more easily take full advantage of our advanced low-power technologies. This reference flow enables designers to become productive more quickly by leveraging the infrastructure we are providing. As a result, they get their parts to market faster and at a lower cost using flows developed by Synopsys Professional Services. We are now extending these techniques to the IBM-Chartered family of 90 nanometer processes on the common platform to give designers access to the full capabilities of these process technologies."

* Synopsys, Inc. announced that IBM and Chartered Semiconductor Manufacturing have chosen Synopsys' DesignWare Hi-Speed USB 2.0 and USB OTG physical layer (PHY) mixed-signal IP for their 90-nanometer common process. IBM and Chartered collaborated with Synopsys to ensure that the DesignWare USB IP solution, which includes mixed-signal PHYs, digital controller cores and verification IP, is optimized for the companies' 90-nm common process platform.

Walt Lange, Field Executive, Systems Solutions at IBM, is quoted: "Making Synopsys' USB 2.0 IP available to designers using the IBM-Chartered common process platform is an important part of our open platform strategy. Their ability to provide a competitive solution including verification IP within the design flow is a key enabler for our customers using USB 2.0 interfaces."

Kevin Meyer, Vice President of Worldwide Marketing at Chartered, is quoted: "The competitive die size and power consumption of the Synopsys DesignWare PHYs, combined with the complete USB digital controller IP offering, enable designers to quickly add cost-effective USB connectivity in applications like high performance game machines, office peripherals, and battery powered portable audio and video devices."

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* Synopsys, Inc. announced "new innovations in RTL synthesis" in the Design Compiler 2005 release that the company says eliminates synthesis dependency on wireload models. The Design Compiler 2005 release has "topographical technology" that is intended to allow designers to predict post layout timing and area during RTL synthesis without wireload model-based timing approximation. Synopsys says no physical design expertise is needed to use the tool, or changes to the synthesis use model.

Jeff Lukanc, Director of Engineering at Integrated Device Technology's Serial-switching Division, is pleased: "Timing convergence on our challenging designs often requires costly iterations between RTL synthesis and physical design. We are impressed with the results from the new topographical technology in the Design Compiler 2005. Without requiring wireload models, timing results were within four percent of post layout timing, which represents a 9x improvement in correlation. Area was within one percent of post layout, representing a 6x improvement in correlation. We look forward to deploying this innovative technology from Synopsys which will significantly reduce costly iterations and accelerate our time to results."

Keith Clarke, Vice President of Engineering at ARM, offers praise: "Accurate timing information in synthesis can significantly improve the productivity of our RTL designers as well as our customers. With the Design Compiler 2005 release, we have seen a 4x improvement in timing and area correlation between synthesis and layout on the ARM1136JF-S(TM) processor without having to use wireload models or change the recommended synthesis flow."

Eric Fischer, Physical Design Manager at SGI, is also quoted: "The design methodology at SGI is based heavily on physical information and real physical floorplan information is difficult to procure early enough to drive synthesis. This is where the new topographical technology in Design Compiler 2005 brings potentially great value to our design teams. Accurate timing prediction during synthesis enables our RTL designers to improve the design while still in the synthesis phase, generate a better starting point for layout and accelerate timing closure. We are encouraged to see that Design Compiler 2005's timing prediction was within 1 percent of post layout timing without requiring any physical information. Design Compiler 2005 is proving itself to be extremely valuable. We are eager to integrate it into our design methodology."

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* Accellera announced that its Board of Directors, representing systems, semiconductor and design tool member companies, has approved Accellera's Standard Co-Emulation Modeling Interface ( SCE-MI) 1.1 as an Accellera verification standard. The SCE-MI specification improves high-speed transaction-level verification between different hardware and software simulation and emulation systems. To further support designers and encourage continued adoption, SCE-MI 1.1 improves model portability between different verification acceleration tools.

Dennis Brophy, Accellera Chair, is quoted: "To increase the use and acceptance of the SCE-MI standard and the availability of models that work with it, our Interface Technical Committee has improved the portability of 3rd party models to make it worthwhile for more developers to support SCI-MI-based models."

Brian Bailey, Chair of Accellera's Interface Technical Committee (ITC), the committee charged with developing the SCE-MI standard, is also quoted: "We are pleased to see the early adoption and acceptance of our SCE-MI specification and are now beginning work on the next version, which will improve usability and coupling with design languages at higher levels of abstraction."

* Altium Ltd. announced release of Service Pack 2 for the company's P-CAD 2004 PCB design system. The company says this release has 130+ new features and enhancements "designed to give greater power and control over the PCB design process" and is a free download to all existing P-CAD 2004 customers.

Some of the new SP2 features include: Backward compatibility support; Integrated and enhanced variants; Improvements to Specctra/Situs exporter including translating tools; Improved glossing and hugging performance for Advanced Route tool; Copper pour improvements; Advanced Route tool expanded; Improvements to P-CAD’s Bonus Technologies featuring Altium Designer’s Situs Topological Autorouter; Ability to run multiple instances of P-CAD applications; Printer Setup in File Print dialog; Layer stackup improvements; Enhanced layer ordering in print; Support for drill table decimal precision.

Nick Martin, Founder and CEO at Altium, is quoted in the Press Release: "Service Pack 2 is a significant upgrade for our loyal P-CAD customers. We listened closely to the P-CAD community, addressed their issues, and are excited to make this Service Pack available today."

* Applied Wave Research, Inc. (AWR) has announced an agreement with Nera ASA (Nera) to supply Microwave Office and Visual System Simulator (VSS) software and support for the design of point-to-point high capacity radio link equipment.

Karl Martin Gjertsen, Vice President of Technology at Nera, is quoted: "We chose to replace most of our existing design software with AWR's Microwave Office and VSS design suites because the combination of professional software and good, customer-oriented support offers a significant improvement in overall design time. The ease-of-use means that less frequent users do not have to re-familiarize themselves with the suite each time they use it. In addition, the tight integration to Mentor Graphics Expedition software means that we can directly pass designs between the two design tools rather than manually re-enter data. This means faster design realization and elimination of the chance of translation errors."

* Arithmatica, Inc. announced it will now be providing EDA tools. The company announced its CellMath tools line that includes two standard cell-based design tools that the company says improve silicon efficiency by as much as 40 percent without requiring any change in design practices. These new tools include:

** CellMath Designer – "Provides a unique datapath design environment including support for integer, fixed-point and carry-save arithmetic, configurable floating-point functions, timing engine, auto-pipelining, logic optimization based on multiple proprietary microarchitectures, and operator merging and logic sharing across the entire datapath."

** CellMath Builder – "Configures a library of silicon-efficient, floating-point functions based on user performance goals and options such as bit width, internal accuracy and pipeline stages."

Per the Press Release: "The CellMath tools line complements Cadence, Magma, and Synopsys synthesis, physical synthesis, and verification flows. CellMath tools generate bit- and cycle-accurate C and Verilog models for simulation and formal verification, and technology-specific netlists for integration into chip-level netlists during physical synthesis. The models and netlists produced provide an efficient means to formally verify the netlist to the behavioral model, relieving the significant verification bottleneck typical in complex datapath design."

Mitsuo Saito, Chief Fellow in the Semiconductor Company at Toshiba Corp., is quoted: "Toshiba has licensed CellMath Designer to design ICs for consumer electronics applications with our 65nm process technology. After extensive evaluation of real designs, it was clear that CellMath Designer helped us achieve our aggressive performance goals and reduce die area. Our datapath results show an average 20% area savings. Learning CellMath Designer was easy; our design team was able to use the tool and achieve good results after two afternoons of training."

Dave Burow, Chairman of Arithmatica, is also quoted: "Datapath design is a critical and growing area in a host of applications required for the consumer electronics market, including 3D graphics, imaging, multimedia, embedded processing, and communications. We are pleased that technology leaders Toshiba, DMP and others are successfully deploying our new CellMath tools to improve the speed, area and power consumption of their next-generation products."

* Cadence Design Systems, Inc. announced new functionality in its PowerMeter dynamic power rail analysis tool. The company says that by using dynamic power calculation algorithms, PowerMeter "enables design teams to accurately calculate and distribute leakage, internal and switching power consumption for every instance of their design."

Also per the Press Release: "When used with the Dynamic Gate (DG) option to the VoltageStorm power analysis solution, PowerMeter calculates the distributed dynamic power used to drive the dynamic rail analysis of a design. This analysis determines the impact of voltage (IR) drop transients on the power and ground rails of a design. Designers can use this information to optimize their power routing widths and the size and location of de-coupling capacitors used to tame IR drop transients, gaining confidence that IR drop will not cause silicon failure."

Noam Benayahu, Director of VLSI at Metalink Ltd., is quoted: "We were establishing our 130 nanometer design methodology and wanted to ensure sufficient de-coupling capacitance on our power rails to avoid any significant dynamic IR drop issues. PowerMeter showed us how large transient power consumption spikes, associated with simultaneous switching during our scan testing, resulted in high dynamic IR drop through the power rails. Using VoltageStorm DG, we were able to better optimize both the location and size of our added de-coupling capacitors prior to tapeout."

Li-Siang Lee, Physical Design Manager at Cortina Design Systems, is also quoted: "We wanted to understand the effectiveness of the power rail de-coupling capacitors we added. VoltageStorm DG's vectorless approach using PowerMeter clearly showed us where power was being consumed, and where we could optimize our capacitance size and locations. We are now confident that IR drop transients will not be a cause of silicon failure for our latest tapeout."

* Celoxica announced Version 4 of its DK Design Suite, DK4. The company says enhancements improve memory utilization and synthesis optimization, and link ESL to physical SoC design.

Per the Press Release: "DK4 introduces new VHDL and Verilog output optimizations for interfacing with Design Compiler from Synopsys. In addition to RTL input for the SoC flow, DK4 also supports automatic scripting for SoC test bench generation. … The advanced memory utilization technology in DK4 supports designer productivity with synthesis of larger and more complex designs 30-50% faster over previous versions. This speed enhancement allows DK4 to produce FPGA implementations directly from large software models."

"Not limited to small single-block, single-clock modules like competing tools, DK4 can synthesize complete systems including complex algorithms, system interfaces and multiple clock domains. The silicon coverage in DK4 has also been extended to include the latest Xilinx devices – the high density Spartan 3E and the lower power Spartan 3L. Algorithm designers can target all popular FPGA devices using a new GUI that offers a more intuitive and easy-to-use software-to-silicon flow … Finally, Celoxica has extended DK Design Suite availability to users of the Linux OS."

* Denali Software, Inc. announced its Dataplex data-subsystem IP product for DRAM, Flash and hard disk drive interfaces. The company says this product gives chip designers "access to a single IP solution that controls off-chip storage devices and optimizes the dataflow from these devices to the SoC. Dataplex supports a variety of SoC bus interfaces and provides multi-port arbitration for optimal system-level data access, and leverages Denali’s Databahn IP technology to provide component-level configurability, effectively insulating SoC designers from fast-changing protocols and details associated with interfaces such as SATA, Flash and DDR memory."

Features in the new IP product include: a DRAM Controller Core; support for a variety of memory and storage devices; multi-port arbitration; integrated DMA engines; and assistance with firmware development;

Brian Gardner, Denali’s Director of IP Product Marketing, is quoted: "Our customers view this data-subsystem IP as a critical piece of the SoC design puzzle. They can get IP for processors, DSPs and embedded memory. Until now, no one has been able to provide a configurable, high-quality solution that bridges the gap between off-chip data storage and the needs of the system design as a whole. By integrating the control of these various storage interfaces, we’re able to offer value in data flow optimization, design quality, configurability and overall cost of ownership."

* 4DSP Inc. has released a new floating point Fast Fourier Transform IP core that is IEEE-754
compliant. The company says the core was designed for use in the newer generation of high performance programmable devices, now available from FPGA vendors like Xilinx and Altera. The FFT core performs and transforms on data ranging from 256 points to 1M points with external memory, if necessary, such as QDR SRAM, closely coupled to the internal logic of the FPGA. It allows users to change the transform length "on the fly", without having to reconfigure the programmable device.

Pierrick Vulliez, 4DSP CTO, is quoted: "We did not expect to reach this level of performance in an FPGA. This has typically been done in an ASIC, which is increasingly more expensive to develop and requires a specific board architecture. To produce a flexible and lower cost device, that is capable of performing a 1024 points Floating Point FFT in 11.4 microseconds using a single core, is far beyond our original expectations. For example, when applied to Video 2D transforms with 1024x1024 images, a single core can process 42 frames per second."

* eASIC Corp., Magma Design Automation, and Flextronics Semiconductor announced the availability of the Easy eFlow tools suite, which the companies say incorporates the Blast Create SA tool for the FlexASIC product family. The Easy eFlow features a complete, high performance RTL-to-GDSII solution designed specifically for the FlexASIC product with its unique single via programmable architecture and SRAM based Look Up Tables. The three companies established the partnership behind this announcement to provide what they describe as "an optimal Structured ASIC product addressing the deep-submicron design issues of cost, time to market and performance. FlexASIC devices, manufactured in 0.13-micron CMOS process, are offered by both eASIC and Flextronics Semiconductor. The Easy eFlow tool suite, which includes Blast Create SA, is a unified design flow that allows for a seamless and fast path to affordable, high performance programmable ASIC designs.

Jerry Worchel, Principal Analyst, ASIC/ASSP and IP Service Semiconductor Research at In-Stat, defends the move: "In-Stat’s Current projections for the structured ASIC market indicate a 64.5% CAGR between 2004 and 2009, or from a dollar perspective, dollar shipment value will grow at a rapid pace, going from $209.8 million in 2004 to $2,520.9 million by 2009. Included in this category is eASIC’s unique via configurable technology, which is as close as one can get to a zero time-to-market approach, at least from the RTL-to-tapeout perspective, as recently announced by STMicroelectronics. The FlexASIC product might take a while for broad-based acceptance to occur, but as design engineers get accustomed to the technology and the advantages it affords, this will become their preferred ASIC design methodology."

* EMA Design Automation announced a new service to help companies satisfy the European Union’s restriction of the use of certain hazardous substances for electrical and electronic equipment (RoHS) directive and other similar legislation. The first level of service offered creates a CIS database with the following RoHS information: Is this part RoHS compliant? What is the RoHS compliant alternate part number? Planned component availability if no alternates are found. Did the manufacturer’s part number change? (Yes/No) Does the manufacturer provide a "Manufacturer Certification" (Warranty) for RoHS compliance?

Manny Marcano, President of EMA Design Automation, is quoted: "Conventional thinking implies that you can solve the problem in manufacturing, but by then it is very expensive to fix, and there is a much higher risk of delays, which means lost market opportunities. At that point the options are limited, and a complete design iteration may be required. In addition, changes at that point create ECNs, which create more work in documentation. Our unique approach offers a design methodology that accomplishes compliance at the intellectual property point in engineering. We’re offering a service and design methodology that solves the problem early in the design phase before components are selected or costs committed."

* Mentor Graphics Corp. announced its IP core based on the PCI Express architecture has been selected by the Microprocessor Development and Research Center (MPRC) of Peking University.

MPRC serves as China’s primary research center for computer science, technology and microelectronics and it has established a joint laboratory with Mentor Graphics for system-on-chip (SoC) verification, chip prototyping and hardware-software debugging. This joint laboratory also supports IP applications for chip design, which is why MPRC selected Mentor Graphics’ fully compliant IP for the PCI Express standard.

Xu Cheng, Director of the MPRC at Peking University, is quoted: "We selected Mentor Graphics based on its history and expertise in certified, standards-based IP and its ease of integration for complex SoC designs. PCI Express is an emerging standard and our latest microprocessor design will support applications for networking connectivity."

* Mentor Graphics also announced that SANYO Electric Co., Ltd. has selected the Mentor's Catapult C Synthesis tool "after an evaluation comparing leading high-level synthesis tools." SANYO says the decision was based on "quality of results, time savings, ease of use, product maturity, and the tool’s compatibility with the company’s C/C++ design flow."

Hideki Yamauchi, Senior LSI Design Technical Manager at Sanyo's Digital Systems Research Center, R&D Headquarters, is quoted: "We found Catapult C’s quality of results and ease-of-use to be very convincing. Using the tool, we were able to start at a higher level of abstraction and produce concise RTL code more quickly than before. Automatically producing ASIC and FPGA hardware from an algorithmic description will enable our hardware designers to spend less time coding details and more time optimizing the more meaningful areas of the design,"

* Mentor Graphics also announced that its 10/100/1000 Mbps Ethernet Media Access Controller (MAC) IP by has been licensed by Stretch Inc. Stretch says its new S5620 processor which was developed using Mentor’s 10/100/1000 Ethernet MAC (PE-MCXMAC). Per the Press Release: "As the first company to embed programmable logic within its processor, Stretch uses familiar C/C++ programming tools that systems developers can automatically configure which dramatically boosts system performance. By enabling application customization using only C/C++, the S5620 delivers a flexible and intelligent system processing solution where time-to-performance is critical for applications such as high-end imaging, networking and office automation. "

* Mentor Graphics announced as well it is the first third-party IP vendor to get PCI Express specification compliance on the NitAl PExBuilder-X254 Platform. NitAl PExBuilder hardware adapters are based on Xilinx Virtex-II Pro FPGAs Compliance includes interoperability testing and validation, and enables designers to develop high-performance computing, storage and communications systems that support the PCI Express standard.

Nitin Sarangdhar, President at NitAl, is quoted: "Mentor Graphics was able to smoothly port their design to our PExBuilder-X254 technology and provide an independent validation, proving that we can offer a stable PCI Express development environment to design engineers."

Meanwhile, Mike Frazier, Director of Engineering for IP Solutions at Xilinx, is thrilled: "We are thrilled to see that Mentor Graphics has achieved compliance on the Xilinx Virtex-II Pro platform. Our customers will benefit from the broad availability of Mentor Graphics IP solutions and from the confidence that when they build Xilinx-based products, they can achieve rapid success."

* NVIDIA Corp. and ARM that NVIDIA has licensed the ARM11 MPCore processor.

Warren East, CEO at ARM, says: "NVIDIA has made a strategic decision by selecting ARM processor technology for use in their next-generation digital media products. The ARM11 MPCore processor, combined with NVIDIA industry-leading graphics and media technology, will deliver new levels of entertainment and innovation to the consumer market, and represents further support for the award-winning ARM11 family of processors."

* Prosilog SA announced release 3.0 of its Magillem platform based design tool. The company says this release combines advanced features to enable faster platform based designs with the support of the Eclipse open development environment. Per the Press Release: "Magillem V3.0 is leveraging the powerful plug-ins capabilities from the Eclipse framework combined with an internal data structure API in order to deliver a consistent user interface for the designer. Within Magillem V3.0, developers still benefit from the SPIRIT Packager module that provides capabilities to generate a SPIRIT 1.1 compliant XML from their current VHDL/Verilog IPs source and specifications files. Moreover, as a SPIRIT based design environment, Magillem V3.0 ensures that all requirements for IP reuse and integration are being taken into account. Creating and manipulating SPIRIT attributes of a design is handled through schematic or scripting interfaces."

Marcel Saussay, CEO of Prosilog, is quoted: "With the latest release of Magillem, our customers have a solid and powerful multi-platform environment which allows them to package, interconnect IPs and generate their design."

* S2C Inc. announced what the company describes as "a revolutionary TAI IP technology that promises to accelerate innovation of IP and SoC time to market by 3 to 6 months. The patent-pending TAI IP (Testable, Analyzable, and Integratable) interconnect technology enables SoCs to be designed using plug-and-play IP modules. This not only speeds up the design and validation process, but also enables software development to begin concurrently with system design. In addition, the plug-and-play IP modules are encrypted, giving IP vendors a new freedom to widely distribute IP without fear of reverse engineering."

Thomas Huang, Chairman and CEO at S2C, details the technology: "Electronic hardware innovation depends on architecture, components, ASSP, IP modules, and SoCs, while software innovation depends on stable hardware and operating environments. Consequently, prototyping is a must step in the development of any electronic product; it provides an early demo of the hardware innovation to customers and provides an implementation platform for software developers prior to production. The step from concept to prototype hardware must be repeated numerous times during the iterative design process. We targeted this step as a bottleneck to eliminate since it is just a time-consuming mapping of one representation to another that is unrelated to innovation. To accelerate innovation, the designer must be able to easily access IP and quickly assemble a prototype that enables hardware and software to work together to demonstrate system functionality. TAI IP technology and our FPGA-based ESL design solution are the breakthroughs that achieve this objective. Current beta partners who have applied our technology conservatively estimate a time savings of 3 to 6 months."

* Sequence Design announced that the company's CoolTime on-chip dynamic voltage drop analysis tool was selected by NEC Electronics Corp.

Technical details per the Press Release: "Eliminating the need for multiple point tools and iterations, CoolTime renders accurate and convergent analysis of interdependent electrical effects for multi-million gate designs. CoolTime performs fast transient current analysis to incorporate dynamic effects resulting from RLC parasitics of power-grid, package, decoupling capacitors and non-switching cells. For designs under 130nm, these dynamic effects can contribute to as much as 30 percent to 50 percent of the total voltage drop. CoolTime can handle a full-chip dynamic analysis overnight, and delivers SPICE-like accuracy on dynamic voltage drop, with 5 percent correlation on peak voltage drop and ground bounce, half-width of voltage waveform, and time of peak."

* SIGMA-C announced SOLID+, which the company calls a "new DFM technology that bridges the gap between design and printed wafer results to enable silicon accuracy and help prevent mask failure at 65 nanometers and below. Acting as a virtual exposure tool, this micro-lithography simulation/image verification technology for the first time accurately simulates larger areas and instantly identifies hot spots during the chip/cell design process, letting designers know if their patterns at smaller process nodes can be accurately produced by a photo resist. SIGMA-C believes this upstream approach for transferring an electronic design onto a chip can dramatically reduce mask and engineering wafer costs, as well as improve chip yield and time to volume manufacturing. By helping to prevent respins, it can save millions of dollars per design.

Christian Kalus, CEO and President at SIGMA-C, is quoted: "The lithography process is very complex and costly – representing 40 percent of the total cost of a chip – so we’re pleased to offer this technology with previously unheard-of accuracy to help designers bulletproof their designs against yield loss caused by lithography imperfections. We believe SOLID+ precision is a compelling alternative to running experiments on multi-million-dollar equipment to bridge the gap between what designers intend and the actual result."

* Sigrity, Inc. announced two products, PowerDC PKG and PowerDC PCB software for system-level IR drop analysis.

Per the Press Release: 'As the only standalone tool optimized for IR drop analysis for packages and boards, it helps designers budget end-to-end voltage margins for every device on the package and board to ensure designs are operational. PowerDC complements Sigrity's comprehensive power integrity analysis solutions by providing highly efficient and accurate DC analysis of IC packages and boards to show voltage drops at various component locations. It also finds hot spots that potentially could cause problems. In addition, it identifies possible neckdowns that could adversely impact electrical and thermal performance in the routing. The solution is ideal for today's low-voltage, high-current designs, which require IR drop analysis to optimize the voltage margins for every device on the distribution."

Jiayuan Fang, President of Sigrity, is quoted: "Voltage margins are extremely tight for designs at 90 nanometers and below, making off-chip analysis imperative for achieving operational designs. PowerDC ensures that designers can get accurate system-level IR drop analysis for packages and boards in a very efficient manner."

* Stone Pillar Technologies Inc. announced that National Semiconductor Corp. has adopted Stone Pillar's TestPlanManager for test plan creation for parametric test chips. Per the Press Release: "One of the most time consuming tasks in the development of a semiconductor technology is test flow creation. The process of applying dozens of tests to hundreds of devices and creating test programs consumes costly engineering time. In the event that there is a last minute change to the test chip being analyzed, the entire test plan can potentially require re-tooling. Prior to the availability of Stone Pillar TestPlanManager, this process has been largely unsupported by software tools. TestPlanManager provides intelligent automated test flow creation as part of the complete semiconductor technology development support within Stone Pillar Suite including algorithm library management, procedure scaling, and GUI-based capabilities for applying tests to test chips."

Mark Poulter, Electrical Test Manager for National Semiconductor's Advanced Process Technology Development Group, is quoted: "At National Semiconductor, we are constantly seeking new ways to improve the level of automation used in developing our leading edge analog and mixed-signal processes. We have benefited tremendously from the use of Stone Pillar's TestPlanManager in automating our test flow creation. With the automated capabilities provided by TestPlanManager, we have reduced the engineering effort for the creation of test flows that previously took a week down to a half day, a savings of 90 percent."

* Synopsys announced that UMC has adopted Synopsys' i-Virtual Stepper system for photomask inspection qualification. The i-VSS tool is designed to enhance mask inspection turnaround time and yield and is part of Synopsys' Design for Manufacturing tool suite.

Per the Press Release: "i-VSS has a unique Web-based architecture designed to help leading semiconductor foundries such as UMC connect multiple fab sites to centralize the mask qualification process. With the i-VSS software, all sites can collaborate to create a 'virtual mask qualification portal.' The Web-based system can also allow foundries to be closely linked with supplier mask shops for even greater streamlining."

Simon Tarng, MES Division Director at UMC, is quoted: "The i-Virtual Stepper system is a welcome addition to our fab automation equipment as it helps simplify and automate our incoming mask inspection process through a Web-based architecture for wafer-level simulation and automated-defect dispositioning. For 90 nanometer manufacturing and below, simulation-based mask qualification has become increasingly important to ensure accurate qualification and reduced processing time for high-end photomasks."

* Synopsys also announced it's advancing VCS by incorporating a number of new capabilities so engineers can find design bugs faster and get 5x faster verification performance. The VCS 2005.06 release includes the new VCS Assertion IP Library, which includes protocol checkers for industry standards such as AMBA 2 AHB/APB protocols and PCI interfaces; includes a SystemVerilog testbench capability and native SystemC language simulation.

Manoj Gandhi, Senior Vice President and General Manager of the Verification Group, is appropriately proud: "Synopsys has always been committed to delivering industry standards support in our VCS solution. The latest release now combines our proven, Native Testbench and assertion-based verification technology with SystemVerilog and SystemC languages to deliver higher verification throughput with the flexibility provided by open standards."

* Synopsys also announced that Huawei Technologies has adopted Synopsys' VCS. Huawei says it has achieved "multiple first-pass silicon successes with VCS NTB and has accelerated verification closure with NTB for up to five times faster performance over stand-alone testbench solutions." Nice.

* Tensilica, Inc. announced that it received the highest score ever reported on the Networking Version 2.0 benchmark suite of the Embedded Microprocessor Benchmark Consortium (EEMBC), and that Tensilica’s Xtensa LX processor is the "first licensable processor core to complete certification on this challenging benchmark suite."

Per the Press Release: "EEMBC benchmark scores, based on simulation, show that an optimized Xtensa LX processor core is significantly faster on a per-MHz basis than the only two other processors certified to date, the 1GHz PowerPC 750GX and 1.4 GHz PowerPC MPC7447A, both of which are full-chip, standard product processors."

* TransEDA announced its Assertain Verification Closure Management (VCM) tool that the company says delivers "total measurement and control of the digital design verification process" in a single environment.

Per the Press Release: "Assertain monitors, measures and manages the verification process in one integrated environment. The tool seamlessly brings together rule, protocol and assertion checking; code and assertion coverage; design and assertion coverability analysis; test grading and optimization, linked to specification coverage using proven requirements traceability techniques … Deploying comprehensive and unique assertion coverage metrics such as structural, step and variable coverage, TransEDA’s solution enables precise measurements of how well assertions have been exercised by simulation, and how well they cover the intended behavior. The cross-linked results from assertion coverage and code coverage are combined in a single, unified database that provides a clear view of how design verification is progressing"

The company says it has embedded its formal engine in Assertain, to be used where formal algorithms are best suited to address a verification problem. The engine augments the capabilities of the tool’s integrated rule checking with advanced formal verification of design consistency rules, such as bus contention and high impedance, FSM deadlock and livelock, array out-of-bound, etc. Formal technology is also used to automatically check protocol coverage and compliance with bus standards such as OCP, AHB and AXI.

* VaST Systems Technology Corp. announced the addition of Virtual Processor Model Transformer (VPM-T), phase 1, to its line of virtual system prototyping tools. The company says VPM-T enables VaST users to modify the instruction set of a VaST seed virtual processor model, a capability that up until now only VaST had possessed. The VaST seed model consists of the instruction set, micro-architecture, pipelining and other behavior of a specific microprocessor.

Graham Hellestrand, VaST Founder and CTO, is quoted: "With the transformer, VaST customers can generate a new VPM in the same microprocessor family by adding, removing or replacing instructions in the VaST seed VPM instruction set. The behavior, timing and mnemonic aspects of an instruction can be changed independently. The VPM-T enables our users to quickly enhance or change a VaST virtual processor model and make it available to software and hardware developers within their own organizations and their customer base. This capability has never been available to chip designers before, and can be a large competitive advantage."

* VeriEZ Solutions, Inc. announced SystemVerilog support for the company's EZVerify tool. The EZVerify product provides static analysis and automatic knowledge extraction for OpenVera and SystemVerilog-based verification flows. EZVerify supports the verification constructs included in SystemVerilog 3.1a, and the emerging IEEE standard (P1800). Its single kernel engine reads and analyzes OpenVera and SystemVerilog modules by loading information into a common object format. It consists of two primary components, EZCheck and EZVerify.

Sashi Obilisetty, President and CEO of VeriEZ Solutions, is quoted: "The SystemVerilog extension to EZVerify enables customers to reuse existing OpenVera modules with new SystemVerilog development. "Solving customer problems remains our top priority. We believe our valued customers would like to use our tools in a SystemVerilog environment, and we have made it possible with our current offering".

* Verific Design Automation announced that Jasper Design Automation, has selected Verific’s Hardware Description Language HDL Component Software as the SystemVerilog, Verilog and VHDL language parser for its JasperGold formal verification tool.

Nafees Qureshy, Vice President of Engineering at Jasper Design Automation, is quoted in the Press Release: "Verific made choosing its HDL Component Software easy for us. Verific has a reputation for product quality, reliability and customer support. The software saved us at least six months of development time. In this demanding economic environment, that’s an important advantage."

* Xoomsys Inc., announced "significant progress" in circuit simulation. The Xoomsys technology partitions large tightly coupled circuits and the distribution of the resulting partitions for simulation decouples the problem onto multiple independent processors. The company says its distributed processing technology delivers 15x to 20x higher throughput on a 10-processor Linux cluster and that the results were achieved using customers’ "trusted simulators" with no loss of accuracy in the results and no changes to inputs or outputs. [In other words, all gain and no pain.]

Per the Press Release: "The Xoomsys solution uses industry-standard circuit simulators and low-cost Linux-based computers to offer a cost-effective way to speed up simulations. In using the Xoomsys solution no changes are needed to the existing designs, design flows, tools, or methodologies. Xoomsys has been working with the leading circuit simulator vendors to speed up existing customer simulation flows."

Jim Hogan, General Partner at Telos Ventures, is quoted: "Ensuring correct functionality of sub-100 nanometer designs in the presence of effects such as coupling, noise and IR drop often requires accurate simulation at the transistor level. A high-capacity transistor-level simulation capability that does not compromise accuracy is ideal for addressing these requirements. Xoomsys is on the right track in developing such a capability."