* Aprio Technologies announced its Halo-View data viewer, which the company says makes its DFM product suite "more readily accessible for the IC industry. The new product will offer Halo users more efficient and sophisticated viewing and navigation capabilities for optical proximity correction (OPC) generation and silicon verification results."

Randy Smith, Aprio's Vice President of Marketing and Sales, is quoted: "With the addition of Halo-View, which speeds up data display to accommodate today's high-data volume, extremely complex designs, Halo users now have a very efficient layout viewer to support large-scale data, super high-speed display and multiple formats - all in one product suite."

* Accelerated Technology, a Mentor Graphics division, announced the release of a configurable version of the Nucleus RTOS with its corresponding middleware package for the Nios II family of embedded processors from Altera Corp.

Per the Press Release: "A major new feature of the Nucleus RTOS is the software's ability to automatically configure itself using Altera's Hardware Abstraction Layer (HAL) and adjust to any hardware changes using Altera's SOPC Builder system-level development tool. Using the HAL developers can move hardware components in the FPGA without having to hand-code the addition, deletion or address changes into the Nucleus code."

Chris Balough, Director of Software and Nios marketing at Altera, is quoted: "The addition of Accelerated Technology's configurable RTOS to the Nios II processor's growing ecosystem gives embedded developers even more flexibility in designing their systems. The ability to easily reconfigure the FPGA gives embedded developers the ability to focus on their core competency and get their application to market quickly."

* Actel Corp. has introduced CoreFFT, which the company describes as "an IP core generator that produces optimized fast Fourier transform (FFT) cores for use with Actel's flash- and antifuse-based families of FPGAs. CoreFFT is designed for high-reliability applications requiring resistance to high temperature, firm-error immunity and radiation tolerance, such as radar, ground and air communications, acoustics, oil production, and medical signal processing. CoreFFT produces FPGA-optimized modules that perform FFTs to convert a signal from the time domain to the frequency domain in order to show the spectral content of the signal."

Yankin Tanurhan, Senior Director of Applications and IP solutions at Actel, is quoted: "Fourier transforms provide a powerful analysis tool for a broad range of applications. CoreFFT, in conjunction with an Actel FPGA, is an excellent option for designers of high-reliability applications that also want to benefit from the features of Actel's single-chip devices, including firm-error immunity, radiation tolerance and live at power-up capabilities."

* Actel Corp. also announced immediate availability of the ProASIC3 starter kit and sampling of its 250K-gate A3P250 FPGA. The company announced dual versions of the starter kit to ease design, both a prototyping and a low-cost evaluation version.

Per the Press Release: "The starter kit is available in two versions. The EVAL kit includes an A3P250 FPGA soldered directly to an evaluation board, providing customers a low-cost solution to validate the performance of the device. The PROTO kit includes a socket-equipped evaluation board, allowing 9 of the 10 devices in the ProASIC3/E family to be evaluated with the PROTO kit."

Meanwhile: "The single-chip 250K-gate A3P250 FPGA contains 1024 bits (128 bits x 8 pages) of on-chip user nonvolatile flash memory and six clock conditioning circuits, one with on-board phase-locked loop (PLL). The A3P250 supports four I/O banks with up to 157 I/Os and advanced I/O standards including PCI, LVDS and LVPECL. For power-conscious customers, the A3P250 devices deliver stand-by power consumption of only 3mA under typical conditions."

* Agilent Technologies Inc. introduced a WiMAX design exploration library for use with the company’s Advanced Design System (ADS) EDA software. The library provides fully coded bit-error rate analysis and therefore helps wireless systems designers and verification engineers with the development of communications products for broadband wireless access (BWA) applications.

* Aldec, Inc. announced a site license for 10,000 Riviera HDL simulators to be installed at Renesas Design Vietnam Co., Ltd. – a subsidiary of Renesas Technology Corp., which in turn is a semiconductor vendor established as a joint venture between Hitachi, Ltd. and Mitsubishi Electric Corp. Renesas says it has purchased Riviera-SNA (Simulator for Networking Applications) to be used for parallel verification of their microprocessor based system-level designs.

Per the Press Release: "The Agreement between Aldec and Renesas covers a three-year period, is renewable and provides a virtual site license with access to 10,000 HDL simulators simultaneously. Aldec will be working directly with Renasas on set-up and configuration and will provide direct on-site support throughout the design lifecycle. The partnership will be analyzed quarterly and adjusted based on further verification requirements and implementation of other Aldec products such as hardware acceleration and co-verification."

Tsuneo Sato, President of Renesas Design Vietnam Co., Ltd., is quoted: "Our best strategy for developing new technology is to work very closely with a company such as Aldec who is dedicated to providing solutions to our verification problems."

* Ansoft released Q3D Extractor v7, the company's 3D quasi-static electromagnetic parasitic extraction tool. This release has new features to help import 3D CAD models and IC, PCB and package layouts from third-party tools. A new fault-tolerant meshing algorithm has been added to make the meshing process tolerant to anomalies that occur in geometric data from CAD/EDA software programs. The new release also provides automatic and interactive model healing techniques that allow users to detect and repair errors in imported geometry.

Q3D Extractor v7 also introduces a Distributed Analysis option, which allows users to expedite design space studies by using multiple computers on a network to analyze different design variations. Users define parametric sweeps of design variables, and the software automatically sends each instance off to separate machines to be solved. The results are then automatically reassembled for post-processing.

* Ansoft Corp. also announced Optimetrics v4. The company says this release "introduces SNLP (Sequential Nonlinear Programming) and SMINLP (Sequential Mixed-Integer Nonlinear Programming) optimization algorithms. Applying Response Surface Modeling (RSM) techniques, these complementary methods allow engineers to optimize over a continuous design space and/or to specify discrete steps between instances, respectively. The new discrete step optimization can be configured to ensure that the resulting optimized design is realizable for a given manufacturing process."

Nancy Lambert, Vice President of R&D, is quoted: "Optimetrics enables engineers to automate the design optimization process for even the most challenging high-performance electronic devices, identify desirable design features early in the development cycle and intelligently seek optimal values for design parameters that meet design targets, all while reducing engineering design time."

* Cadence Design Systems, Inc. and Semiconductor Manufacturing International Corp. announced that HiSilicon Technologies Co., Ltd. produced a high-performance communications device, using the Cadence Encounter design platform and targeted to SMIC's process. In addition, Cadence and SMIC say they are now providing a digital reference flow to mutual customers that includes support for low-power requirements.

James Sung, Senior Vice President of Marketing and Sales at SMIC, is also quoted: "HiSilicon's success is an ideal example of how SMIC collaborates with Cadence to address our customers' most pressing design challenges. We are pleased to continue our work with Cadence to facilitate SoC design for customers in the growing consumer handheld and portable device markets."

Jan Willis, Senior Vice President of Industry Alliances at Cadence, is quoted as well: "Working closely with SMIC to deliver solutions for leading design centers such as HiSilicon provides customers with enhanced value, a greater chance for design success and a competitive edge for speeding their time to market."

* Next – Cadence Design Systems, Inc. and Cray Inc. announced that the companies completed a project to migrate the full-custom layouts of the memory arrays and cell libraries for Cray's next-generation vector processing technology to Texas Instruments' latest 90-nanometer process technology.

Per the Press Release: "During this development, the Cray-Cadence team was tasked with migrating the custom layouts for five memory arrays within the CPU, as well as the layout for more than 1,000 cell library elements used to implement other portions of the CPU. Cray engineers provided detailed knowledge of the CPU architecture, original technology process characteristics and previous implementations, while Cadence engineers contributed deep expertise in device/cell layout migration in 90-nanometer geometries using automation."

Dave Kiefer, Vice President of Engineering at Cray, is quoted: "Given how hard we've been pushing the process technology and the CAD tools on this development, that's a real accomplishment. Leveraging Cadence's advanced technology and expertise for device/cell layout migration enabled us to achieve some major technology breakthroughs."

Tim Henricks, Vice President for North American engineering services at Cadence Design Systems, is also quoted: "Cray and the advanced machines they develop are a national treasure, and we appreciate such opportunities to utilize our technology and our design expertise. This project with Cray showed the value of complementing technology with engineering services. Some advanced technologies have very steep learning curves, making them difficult for customers to adopt while 'flying solo' in time-critical projects. Our collaborative engineering approach enables customers to apply and build expertise using latest-generation design technologies on current projects without compromising their development schedules."

* Cadence Design Systems also announced the Cadence Allegro system interconnect design platform, which the company says has been "enhanced with improvements in the Cadence constraint-driven IC Packaging co-design flow and enhanced power and signal integrity (SI) analysis accuracy."

Steven Lowder, Amkor's Vice President of Worldwide Design, is quoted: "These latest advances in Cadence IC packaging technology provide Amkor and our design customers with significant opportunities for savings in design cycle time while maintaining and improving overall quality. As a leading provider of packaging and test solutions for complex multi-die designs, Amkor and our customers benefit from the Cadence commitment to enabling IC package co-design and analysis."

Kevin Roselle, CTO of Bayside Design Inc., is also quoted: "As we move into the next era of packaging, this kind of support from our design automation software partners is extremely important, especially in the area of power delivery design and analysis."

Finally, our good friend Edward Wan, Senior Director of Design Service Marketing at TSMC, is quoted: "Dynamic IR drop is a major concern for both chip and package design. Without package IR loading, high-speed digital designers may have incomplete dynamic IR drop margins that severely reduce chip performance. Reference Flow 6.0 incorporates the Allegro Package Designer's integrated flow that helps designers simultaneously evaluate these effects in an automated and efficient manner."

* Finally – Cadence Design Systems announced that SensorDynamics used Cadence's Virtuoso design platform for its latest chip designed for intelligent sensor interfaces. The chip was produced in STMicroelectronics' BCD6 process technology and happily achieved first-pass silicon. Good news also that SensorDynamics "achieved significant time savings for analog top routing and analog assembly – [and] the use of the VHDL-AMS verification environment helped identify and solve a number of design bugs, which SensorDynamics claims would not have been discovered with a traditional methodology."

Hubertus Christ, CEO SensorDynamics, is quoted: "The Virtuoso platform was the most intrinsic part of this design flow, which helped us to move from first chip and block ideas to final silicon with a minimum number of design cycles. In spite of using a design flow which was yet not released from the foundry, we were able to produce a first-pass silicon success in a fast and efficient way."

* CoWare Inc. announced that SANYO Electric Co., Ltd. has purchased LISATek Processor Designer and Processor Generator software, as well as consulting services from CoWare. Be it known that CoWare has worked with SANYO to develop a LISA 2.0 model of its SANYO DSP core. The three-year purchase agreement will enable SANYO to replace its current manual design methods with a LISATek-based methodology to reduce its DSP core design cycle time by fifty to sixty-six percent.

Hideki Ohashi, Manager, DSP Development Section, IP Development Department, System Solution Central Business Unit, SANYO, is quoted: "We evaluated a number of products, but LISATek was an easy choice. The range of capabilities that LISATek provides was far superior, and the result was a dramatic decrease in our development time."

* Incentia Design Systems, Inc. announced that NEC Electronics Corp. has selected Incentia's TimeCraft as a signoff static timing analyzer for 90-nanometer designs.

Hiroshi Sakuma, General Manager, Design Engineering Division, Technology Foundation Dev. Op. Unit, NEC Electronics Corporation, is quoted: "Timing analysis and signoff for nanometer designs are facing severe challenges in runtime, capacity, and particularly accuracy caused by statistical process variations. We have closely worked with Incentia to establish its TimeCraft as a timing signoff tool."

Ihao Chen, President & CEO of Incentia, is quoted: "We are very pleased that TimeCraft has passed NEC Electronics' rigorous qualification process to become a standard signoff static timing analyzer for nanometer designs."

* Interra Systems announced the integration of its Verilog-Cheetah and VHDL-Jaguar analyzers into Carbon Design Systems new VSP, virtual system prototyping, product.

Alan Swahn, Vice President of Marketing and Business Development at Carbon Design Systems, is quoted: "Interra's expertise in hardware description languages accelerated our time-to-market with proven Verilog and VHDL language front-ends. Interra's technology, integration services, and Beacon test suites were a valuable asset to our product development."

* Impulse Accelerated Technologies announced that its CoDeveloper C-to-FPGA tools now integrate with PGA synthesis and verification tools from Synplicity. The company also announced that Impulse has joined the Synplicity Strategic Access Partner Program. The partnership emphasizes C-to-hardware tools as a powerful addition to HDL-based design methods.

Alan George, Director of the High-Performance Computing and Simulation (HCS) Research Lab at the University of Florida, is endorsing the announcement: "Tools such as Impulse-C for software-to-hardware mapping can be an effective component in an HDL synthesis methodology. The ability to rapidly generate FPGA hardware from C-level behavioral descriptions encourages experimentation and helps bridge the gap between software and hardware design, targeting platforms ranging from reconfigurable supercomputers to high-performance embedded systems."

Joe Gianelli, Vice President of Business Development at Synplicity, is also quoted: "With the increased use of FPGAs for embedded software acceleration, the ability to compile standard, untimed C code directly into synthesizable HDL capability is of great importance creates a user friendly flow for a wider audience of FPGA users."

* Mentor Graphics Corp. announced that its Calibre physical verification and extraction tools are now fully integrated into the Cadence design creation environment. Per the Press Release: "By extending Calibre Interactive to include the Calibre extracted view, designers working on analog and analog/mixed-signal chips can now perform post-layout analysis and simulation for accurate nanometer silicon modeling. It also allows designers to adopt a single physical verification and parasitic extraction flow using the Calibre tool suite."

"Designers can cross probe results, debug quickly and easily, and locate and simulate parasitics using Calibre's extracted view output format. The pairing of Calibre LVS and Calibre xRC is especially significant, as these tools extract actual device parameters and interconnect parasitics for back-annotation to the source schematic. This results in an electrical model that faithfully reflects the circuit's physical design and ensures the accuracy of subsequent post-layout simulation and analysis."

Jeanne Hermsen, Senior Technical Staff Member for the Imaging Systems Division (ISD) in Agilent Technologies' Semiconductor Products Group, is quoted: "The combination of Calibre tools and TSMC design kits gives us best-in-class options for building analog/mixed-signal circuits for our sensor products. Because Calibre is the sign-off standard at most foundries, we have a set of tools that is always qualified and current."

Joe Sawicki, Vice President and General Manager of Mentor's design-to-silicon division, is also quoted: "The integration of Calibre in Agilent's image sensor design creation environment gives their designers easy access to a streamlined suite of tools validated for advanced manufacturing processes."

* Mentor Graphics Corp. announced the immediate availability of the HyperLynx 7.5 tool suite for pre- and post-layout signal integrity (SI) simulation and analysis. HyperLynx 7.5 includes significant productivity and technology enhancements targeted at emerging SERDES interconnect standards such as PCI-Express, Hyper Transport, XAUI and SATA/SAS.

Dr. Howard Johnson, author of High-Speed Digital Design: A Handbook of Black Magic is euphoric: "The new free-form schematic editor and advanced high-speed analysis features in HyperLynx 7.5 elevate this tool to stratospheric levels of utility and ease of use. To all digital designers: Buy it, learn it, and use it."

* Novas Software, Inc. announced that Toshiba America Electronic Components, Inc. (TAEC) has adopted Novas’ Verdi Automated Debug System as its debug platform. The companies say the Verdi system will be used across internal design teams and in TAEC SoC Design Centers. TAEC says "Novas’ second-generation Verdi debug system is being deployed as an integral part of TAEC’s custom chip, soft IP platform approach to SoC design to support its internal design team and customers."

Shigenori Imazato, Vice President of Engineering at TAEC’s SoC Design Centers, is quoted: "Our teams work on extremely complex designs with advanced process technologies, often involving very large gate counts and significant amounts of third-party IP. These factors increase the magnitude of the verification challenge and impose additional time and cost constraints on our engineering efforts. With the Verdi system, we are able to implement a much more effective, automated debug methodology for finding problems faster and earlier in the development cycle."

Scott Sandler, President and CEO of Novas, responds: "We’re pleased that TAEC has adopted Verdi’s powerful approach to debug that gives engineers more visibility into their designs and improves overall verification productivity."

* Sequence Design announced KPIT Cummins Info Systems has chosen Columbus-AMS for RLC extraction. Sequence says, "KPIT joins a growing list of Sequence customers in India, and the first signed by new distributor, D'gipro."

Vic Kulkarni, Sequence President and CEO, is quoted: "KPIT Cummins is the first Indian customer signed by D'gipro since we named them our exclusive distributor there and marks a major milestone in Sequence's India operations. KPIT's focus on complex designs gives us a sense of where the future of chip design is going for the Indian design community, and we look forward to working closely with them through our India Center of Excellence."

Praveen Acharya, Vice President for VLSI at KPIT Cummins, is quoted: "It is necessary for our valued clients to get the benefits of our advanced design flow and design quality at the most competitive cost. The adoption of Sequence Columbus-AMS into our design flow has further strengthened our services portfolio for key customers."

* SMSC has introduced its USB3450 UTMI+ stand-alone device/host transceiver that the company says "has passed Hi-Speed USB compliance testing with the USB Implementers Forum (USB-IF). The USB3450 provides a flexible, stand-alone Hi-Speed PHY solution that provides the highest level of UTMI+ support (Level 3). Interoperability has been proven through extensive testing with industry leading Hi-Speed USB host IP providers."

Steve Nelson, Vice President of Marketing for Connectivity Solutions at SMSC, is quoted: "SMSC now provides a solution with the industry’s smallest footprint UTMI+ device/host PHY. Our customers can also count on low power consumption and the industry’s best Hi-Speed eye diagrams, which they’ve come to expect from SMSC’s family of Hi-Speed USB PHYs."

* Synopsys, Inc. announced that it is "the first to demonstrate a device controller based on USB-IF's Certified Wireless USB specification, the new wireless extension to USB that combines the speed and security of wired technology with the ease-of- use of wireless technology … Multimedia files [have been] transferred to and from a PC platform based on the Certified Wireless USB technology and on a device controller IP reference design from Synopsys. Synopsys' IP reference design is based on the Certified Wireless USB specification. These transfers are similar to transfers done today between a PC and an MP3 player or digital camera. The demonstration uses no wires. The transfers use Wireless USB protocols (based on the Certified Wireless USB spec) over WiMedia common ultra-wideband (UWB) radios."

Jeff Ravencraft, Chairman of the USB Implementers Forum, is quoted: "As a contributor to the specification, Synopsys has been working closely with the earliest implementers of the Certified Wireless USB specification. Their progress with this demonstration shows the maturity of the standard. Synopsys' work in the interoperability lab is a great example of how to successfully develop products based on the specification."

* Let's read this one verbatim:

"A breakthrough processor architecture for high-definition (HD) video encoding was announced today at Hot Chips 17 by Telairity Semiconductor. Harnessing multiple independent vector/scalar cores, the multicore Telairity-1 architecture is specifically designed to handle the demanding computational requirements of the H.264 (MPEG-4 Part 10) HD codec. H.264 is set to supersede MPEG-2 as the standard by which HD video is compressed in the professional broadcast environment for transmission, storage, and editing, where the new standard will deliver the same or better picture quality with a lower bit rate. Beginning with the T1P2000 multicore video processor, the first SoC to be built using the new architecture, H.264 encoding solutions implemented with Telairity-1 will offer the smallest footprint and lowest cost for broadcast-quality H.264 video compression, requiring typically less than one quarter the number of chips of general-purpose DSP solutions."

Howard Sachs, Founder, President, and CEO of Telairity Semiconductor, says the consumer will be happy: "Lower prices for HD equipment, ramping sales of HDTV receivers and monitors, and the availability of HD-DVD and Blu-Ray DVD players mean that HDTV has arrived. Now the industry is positioned to ensure that the reality of HDTV will live up to the audience’s expectations. Encoders designed with Telairity-1 processors will play a major role in making this happen."

Hot chips indeed!

* Tensilica, Inc., announced that its Xtensa processors have been proven in 90-nanometer design flows to reach the "highest clock rate of any licensable 32-bit processors available, reaching over 600 MHz in commercially available, high-performance foundry process technology and up to 700 MHz from Tensilica’s value-added silicon partners, such as STMicroelectronics."

Chris Rowen, Tensilica’s President and CEO, knows of what he speaks when he says, "These outstanding results prove that our basic Xtensa architecture is a superior platform for embedded applications, compared to the vintage RISC architectures originally designed for 1980’s desktops. With the performance we can provide in 90nm flows, Xtensa processors are the best choice for both control tasks and compute-intensive applications requiring the further performance advantage of configurability and extensibility."

* Tensilica also announced that it has enhanced its automated configurable processor design methodology to account for common integrated circuit design challenges with 90-nanometer process technology. The company says these enhancements support the latest capabilities of the Cadence and Synopsys tools and include automated generation of physical design flow scripts that significantly lower power consumption, automate the input of user-defined power structures, and support crosstalk analysis."

Steve Roddy, Tensilica’s Vice President of Marketing, is quoted: "90 nanometer design presents significant new challenges for IC designers. By automating the script development for the best-in-class design tools, we can speed our customers’ designs to market."

*****************************

His master's voice …

Bismarck, North Dakota – "It's a product that has already shown its prowess at venues like the Country Music Hall of Fame, select national museums and even the Mayo Clinic. Now Dakota Audio is aiming to bring its innovative speaker technology to many other venues worldwide. Focused Sound is a compact product from Dakota Audio that controls sound in a unique manner so listeners can experience high quality sound directed to a specific area without being distracted by large, obtrusive speakers."

"Multiple small, high-quality loudspeakers comprise Focused Sound, which provides excellent sound quality and control in thin, almost inconspicuous packages. Patent-pending technology allows Dakota Audio to design arrays for specific situations and provide coverage patterns not available with other technologies."

"Dakota Audio mounts the multiple loudspeakers on a flat surface, eliminating the sonic coloration of domes. By strictly controlling the 'launch' time of the sound from each loudspeaker, all speakers act together in concert at the target location. This control, known as correlation, allows Focused Sound to deliver well-controlled sound dispersion, adjustability and coverage patterns that are not physically possible with a dome."

"Typical focused arrays give a reduction in volume of more than 20 decibels as a listener steps from the sound's 'target zone' to the untargeted area just a few feet away. By varying the design of the array and the timing of the speakers, different patterns and focal lengths may be obtained. The thin (3 inches thick) arrays are much less conspicuous than a 'flying saucer convention' of dome speakers. The 36-inch square arrays can be customized to almost any shape or size."