Altium Ltd. announced the release of the P-CAD 2004 PCB design system, which the company says includes 50+ new and enhanced features. Per the Press Release: "This version offers upgraded technologies for layout and automatic and interactive routing, improved support for CAM file editing and circuit simulation, as well as a host of enhancements designed to give greater power and control over the PCB design process."

Features include a new interactive Advanced Route tool that allows designers "to start routing from any net object, regardless of grid or connection line position. Designers can choose to hug the routing around existing objects, plow around copper pours, board edges, cutouts and keepouts, as well as move existing traces and vias. Designers also have complete control over all interactive routing features, including the level of 'glossing' or trace cleanup the tool attempts during interactive routing." Other changes in this release are the inclusion, as standard, of Altium's CAMtastic 2004 CAM file editor, and updated P-CAD's supplied board-level component libraries in compliance with the ISO 9001:2000 standard.

Infineon Technologies has good news in that their 150-MHz TriCore TC1130 microcontroller, which the company says is a 32-bit chip capable of running the Linux OS, has achieved an "exceptional score of 95.2 Automarks in tests against EEMBC's automotive/industrial benchmark suite." Infineon says the test results were certified by the EEMBC Certification Laboratory, and "represent a threefold improvement over the TriCore TC11IB-96, which was tested against the same automotive/industrial benchmarks in 2002."

Markus Levy, EEMBC President, is quoted: "This impressive boost in performance arises from the addition of a hardware floating point unit, increased frequency, and an enhanced external bus interface."

The Joint Development Project (JDP) between Silterra Malaysia Sdn. Bhd. and IMEC announced functional SRAM chips at Silterra's wafer fabrication facility in Malaysia. Per the Press Release: "The device, an 8-megabit SRAM, was fabricated in the all-copper, foundry compatible 0.13-micron CMOS process technology jointly developed by both companies."

Bruce Gray, President and Interim CEO of Silterra, is delighted: "We are thrilled that the device works so well on the very first 0.13-micron wafer we ran in our fab. The project is right on schedule with this demonstration of the phenomenal capabilities of both companies. We are now fine tuning the process, putting the customer design kit together, and we should be ready to start production in 2005 as planned."

Magma Design Automation Inc. announced that NEC Electronics America, Inc. has "successfully verified a multimillion-instance nanometer design using Version 4.2 of the Blast Fusion physical design system that incorporates Magma's third-generation routing technology."

John Fallin, General Manager at the Design Solutions Center for NEC Electronics America, is quoted: "We used Blast Fusion and its new routing technology on one of our most complex designs that the previous router had difficulty with, due to our challenging die size and metal layer requirements. Blast Fusion completed the routing quickly and delivered DRC-clean designs in a single pass. The new router also delivered better results in via count and wire length. We plan to use this new router on future nanometer designs." That should make Magma and NEC very happy.

Mentor Graphics Corp. announced that NEC Electronics has adopted the Mentor's analog mixed-signal simulator, ADVance MS tool. The companies said that the tool is being used in the development of large, high-speed I/O interface circuits for NEC Electronics' analog and mixed-signal SoC products.

Kunio Mori, General Manager of the Server Systems Division at NEC, is quoted: "Co-verification between digital and analog circuits is necessary when developing high-speed I/O interfaces where performance is very complicated. In particular, the final verification, which includes parasitic extraction and LPE, is essential, not only to assure product quality but also to reduce total turn around time. We have also expanded the capacity limit of the simulation using Mach, FastSpice simulator, based on ADVance MS technology for the circuits with LPE."

Silicon Dimensions, Inc. announced Chip2Nite 2.0, whose features include a new DRC suite, auto-macro placement and block floor planning capability, improved statistics reporting, and what the company says is a 5x to 10x improvement in "typical database load times critical to perform rapid prototyping and what-if analysis. The additions and enhancements eliminate costly iterations between logic design and physical design reducing the overall design time by at least 20 per cent."

Don Zereski, President and CEO Silicon Dimensions, is quoted: "Logic designers can no longer perform their job without knowledge of the physical parameters associated with nanometer design. The complexities of nanometer design are increasing exponentially. Chip2Nite hides the complexities and intricacies of physical design. Logic designers benefit from knowledge of the physical design that was previously unknown to them." That's good news.

Synopsys, Inc. announced that it is "the first EDA software company to support the Intel Xeon processor with Intel Extended Memory 64 Technology (Intel EM64T) for 64- and 32-bit computing with the Red Hat Enterprise Linux version 3 operating system using its Galaxy design and Discovery verification technology."

Guru Bhatia, director of engineering computing at Intel, is quoted: "The Intel Xeon processor-based platforms with Intel EM64T provide large memory support, Demand Based Switching for power consumption optimization, and PCI-Express-based advanced I/O along with higher performance. That combination of features and performance, coupled with Synopsys' suite of semiconductor design and verification tools, gives a technical advantage to the EDA engineering community to design complex silicon products." And so, the march to Linux continues.

Synopsys also announced that Sasken used Synopsys' Galaxy Design Platform to develop a reference flow "to enhance the implementation and signoff process for its complex designs - accelerating design convergence and delivering a time to market advantage for customers."

Vilas Bhade, Director at Sasken Communication Technology, is also quoted: "With Synopsys' Galaxy Design Platform, Sasken has further enhanced its ability to handle complex designs from various foundries using different process technologies to tape out. The Synopsys Galaxy solution enables Sasken to deliver to its customers a time-to-market advantage."

TransEDA announces version 2.5 of its imPROVE-HDL formal property checker. The company says this new version brings improvements to enhance the use of assertion-based verification (ABV) methodologies for SoC design. Per the Press Release, "In addition to reading PSL assertions from an external file, imPROVE-HDL v2.5 now supports PSL in both VHDL and Verilog flavors embedded in the design. Among the tool’s improvements, early customers have also reported a performance increase of 25% in average."

Yaron Wolfsthal, Manager of Formal Verification and Testing Technologies at the IBM Haifa Research Lab, is optimistic: "The growing adoption for PSL across the industry is a very positive trend for design and verification engineers. This trend and support for PSL from companies like TransEDA, gives engineers more weight to meet the SoC verification challenge."

Verific Design Automation announced that it is shipping what the company describes as the first commercially available SystemVerilog parser. Per the Press Release: "Verific’s SystemVerilog Parser supports the entire SystemVerilog 3.1 language definition, with the exception of SystemVerilog Assertions, for which it supports 3.1a."

Rob Dekker, President of Verific, is quoted: "The market is quickly moving to SystemVerilog and we respond immediately to market demands. Supporting SystemVerilog with our SystemVerilog Parser gives EDA developers the means to support this powerful language inside their design tools, and hence providing a large group of end-users, essentially design engineers, with access to the language. If the end users want it, their EDA tools provider can now deliver."

Simon Davidmann gets the last word: "As the key driving force behind SUPERLOG, which became SystemVerilog, it’s heartening to see the ecosystem develop around the SystemVerilog language. The existence of Verific’s SystemVerilog Parser will further speed adoption of the language and allow new tools to be created sooner, as EDA companies can focus on their added value. Verific is leading the way in helping the industry race forward in developing SystemVerilog tools."