** Actel Corp. and Prover Technology, Inc. announced that the Prover eCheck equivalence checker has been "validated for design verification" in Actel’s Libero Integrated Design Environment (IDE). In addition, Prover says it has joined Actel’s Alliance Program.

Here's an interesting bit from the Press Release: "Prover eCheck provides designers with an automated solution to identify implementation inconsistencies for Actel’s antifuse- and flash-based FPGA devices within a range of high-reliability designs, including military, aerospace and communications applications. The flow is appropriate for Actel customers that produce mission-critical space and/or military designs where functional inconsistencies can have severe consequences. One such customer is Tesat-Spacecom, a leader in advanced FPGA-based designs for critical space applications in communication satellites."

** Actis Design, LLC says it has begun shipping AccurateC Release 2.4, the company's static C++ code analyzer for SystemC that Actis calls "the first software tool used in the SystemC code development flow."

Per the Press Release: "Where previous versions were used post compilation, AccurateC Release 2.4 now analyzes SystemC code prior to compilation, simulation or synthesis, and offers designers the ability to analyze either one module or the entire SystemC design. Designed to increase productivity by analyzing code prior to complicated downstream processes, AccurateC enforces coding guidelines for high-quality, maintainable code while simplifying debugging with code correction hints for every rule violation. "

Joan Bartlett, President of Actis Design, is quoted: "Way too often, design teams complain that getting started with SystemC is far more complicated than it should be. AccurateC is easier to use than a C++ compiler, plus it gives users feedback on their design in terms of SystemC methodology specifics."

** Atsana Corp. announced that Samsung Electronics selected Atsana’s J2211 media processor for its 2 Mpixel SCH-M309 camera phone. Per the Press Release: "Samsung’s recent launch in China of the M Series camera phones, including the SCH-M309 model, represents an unprecedented leap in functionality and performance, with professional camera features such as 2 Mpixel DSC, MPEG4 video Camcorder and Player, Auto-focus and TV-Out. Samsung Electronics is a market leader in delivering excellent multimedia features to the cell phone market, producing over 100 handset models each year and has shipped 86 million handsets in 2004 in 45 countries."

** Mentor Graphics Corp. announced that its TestKompress embedded deterministic test (EDT) tool has been embraced by UMC for use in the foundry's 90 and 130-nanometer reference flows. The companies say that TestKompress tool has "proven to reduce manufacturing test time by up to 100x compared to other test alternatives, helping users increase test coverage and test quality on their complex devices without compromising test time or test cost."

Ken Liou, Director of the IP Development and Design Support Division at UMC, is quoted: "TestKompress has shown that it can deliver outstanding test performance for complex devices while maintaining reasonable cost. TestKompress adheres to our commitment to provide customers with services and methodologies for optimal silicon development, and we are pleased to offer it to customers using our 130 and 90nm flows."

** Mentor Graphics Corp. announced the release of its next-generation constraint editor system (CES) into its Expedition Series and Board Station RE PCB design flows. The company says, "CES tightly integrates with the entire systems design flow from schematic entry through physical layout, facilitating multi-disciplined communication of high-speed design rules and constraints between engineers, designers and their tools … Constraints can be entered in terms familiar to team members through a common GUI and then automatically accessed by individual tools in their native formats. Productivity gains can be realized through usability features such as automatic differential pair identification and constraint templates, which make entering complex constraints much easier. Advanced automatic topology and an interactive tuning meter are enabled when CES is used in the design flow… CES also supports bi-directional cross probing, which highlights and selects between a spreadsheet-based constraint interface and the schematic capture and layout tools, enabling designers to view nets and constraints in their native environment. In addition, constraint values are fully synchronized during the forward and backward annotation process with intelligent handling of connectivity changes. "

Clint Harames, Senior Hardware Design Engineer at F5 Networks, offers up a testimonial: "Because of topology awareness, CES has made it much easier to constrain complex, high-speed circuitry. Our constraint entry time has been tremendously reduced, allowing us to get products to market faster and we are only scratching the surface of its capabilities. I look forward to exploiting CES’ scripting capabilities, which will further reduce our constraint entry time."

** Nassda Corp. – which is in the process of being acquired by Synopsys – announced the release of version 6.0 of its HSIMplus, HANEX and CRITIC verification products.

Per the Press Release: "Highlights of this release include new HSIMplus integrations with hierarchical parasitic extraction and digital simulation software that can enable faster and higher-capacity IC verification for designs that combine analog, mixed-signal, digital and memory IP components."

"HANEX Version 6.0 enhancements include coverage of a wider range of design types, improved analysis of manufacturing variations on circuit performance and increased speed of analysis. Silicon-on-insulator (SOI) MOS semiconductor devices are now supported for low-leakage designs. CRITIC version 6.0 supports a streamlined crosstalk analysis flow and can utilize aggressor-only timing window data or can analyze worst-case path delay if timing windows are not available. For early analysis of timing behavior, before layout is complete, idealized clock analysis with balanced delay and slope is now available."

** In the integration area, Nassda and Mentor Graphics say they have collaborated to develop "the industry's first full-chip solution for hierarchical extraction and full-chip simulation of nanometer circuit behavior, signal integrity, power integrity and electromigration effects. Because hierarchical techniques are used, the long runtimes, extremely large netlists and limited capacity of flat parasitic extraction are avoided. The combination of Mentor Graphic's Calibre xRC extractor and Nassda's HSIMplus simulator provides improved capacity and efficiency for verifying the impact of nanometer silicon on design performance and can lead to improved chip yield."

An-Chang Deng, President of Nassda, is quoted: "We believe our version 6.0 release further strengthens our technical leadership in nanometer circuit simulation and analysis. By integrating HSIMplus with Calibre xRC, full-chip post-layout simulation is practical for verification of nanometer effects in complex designs. HANEX's support for multiple process corners and new design types such as SOI provides further improvements in both speed and accuracy for post-layout analysis. Crosstalk analysis with CRITIC is now even easier. Nassda continues to strive to enhance the capacity, performance and ease-of-use of its product line with each new release in order to support our broad customer's requirements."

** Rambus Inc. and Cadence Design Systems, Inc. announced that Open-Silicon has licensed multiple Rambus RaSer serial link "offerings" through the Cadence-Rambus reseller program. The companies say that under the agreement, "Open-Silicon gains access to a portion of the portfolio of Rambus's silicon-proven, industry-standard RaSer PHY cells for applications such as PCI Express, 10-Gigabit Ethernet/XAUI and Serial RapidIO."

Naveed Sherwani, President & CEO of Open-Silicon, is quoted: "Our customers are looking for the most predictable and reliable ASIC turnkey solution available. Integrating Rambus's serial links into multiple customer designs has been incredibly successful. As an IP aggregator, Open-Silicon can provide this silicon-proven IP to our customers, hence simplifying the transfer of Rambus's IP to ASIC designers."

** Tensilica, Inc. happily announced that it has posted "the highest score ever recorded for a licensable processor core, and the highest absolute score ever published for any processor, on the Office Automation benchmark suite of the Embedded Microprocessor Benchmark Consortium (EEMBC). The EEMBC benchmark scores, independently certified by the EEMBC Certification Laboratories (ECL), confirm that the Xtensa LX processor is nearly four times faster than the much larger PowerPC 440GX core, and more than 4 times as powerful as the 64-bit MIPS 20Kc processor… In addition to having a significant advantage in the OAmark scores, Tensilica’s Xtensa LX processor demonstrated much lower code size, which means it requires less memory."

In case you're interested, the certified EEMBC OAmark scores are: 4.19523 – Optimized Xtensa LX processor, 1.07999 – Out-of-the-box PowerPC 440GX processor, 0.98880 – Out-of-the-box Xtensa LX processor, 0.89033 – Out-of-the-box MIPS 20Kc processor, 0.75975 – Out of the box ARM 1026EJ-S processor.

Please note that EEMBC scores for licensable synthesizable processors are expressed on a "per-MHz" basis. The optimized configuration of Xtensa LX used in this Office Automation benchmark certification achieved a 454 MHz operating frequency in 90-nanometer ASIC technology.