* Accelerated Technology, a Mentor Graphics division, announced availability of the Nucleus RTOS for the Texas Instruments' OMAP5912 processor.

Greg Mar, Worldwide SoC Platform Manager at TI, is quoted: "Accelerated Technology enhances the capabilities of the TI OMAP processors and meets the need for a robust and real-time operating system in the PDT market by providing the Nucleus RTOS on the OMAP platform,"

* Altium Ltd. announced the release of Service Pack 4 (SP4) for Altium Designer, which the company calls "the single, unified application that incorporates all the technologies and capabilities necessary for complete electronic product development.

SP4 features include: improved design team support with the new file locking option, better project management and portability with the new ‘Archive Project’ wizard, a new default document feature, full 3-D component clearance checking, enhanced PCB editing, enhanced schematic hierarchy management, improved global editing capabilities, and extended HDL design capabilities.

* Celoxica Ltd. announced that Tadiran Communication Ltd. has adopted the Celoxica DK Design Suite of C-based design and synthesis tools. The companies say the evaluation looked oat military tactical radios and systems in the HF, VHF, and UHF bands, and that Celoxica's DK Design Suite will be used to implement very complex signal processing and communications algorithms in FPGA hardware.

Per the Press Release: "Israeli-based Advanced Semiconductor Technologies (AST) supported Tadiran through the evaluation and procurement process providing local expertise in electronic system level C-based design and synthesis."

Danny Koenig, Modems Director for Tadiran, is quoted: "The type of design work we undertake is becoming more complex and more time critical, and we needed a design tool that would enable us to achieve increased flexibility, faster development and easier maintenance. We believe that the new generation of high-level language design tools give us these capabilities and consider the DK Design Suite to be the most proven and best available solution."

* Denali Software, Inc. and TaraCom Integrated Products Inc. announced availability of "comprehensive IP solutions for Serial ATA (SATA) design, verification, and deployment. The integrated solution provides developers with Denali’s Databahn design IP for controlling SATA devices, TaraCom’s TRC3002 SATA physical layer (PHY) IP, and Denali’s PureSpec verification IP for ensuring compliance, interoperability and system performance.

Technical background per the Press Release: "Serial ATA is quickly replacing parallel ATA in hard disks in desktop and mobile PCs. The SATA hard drive connector is smaller than the equivalent parallel connector, and enables data transfer rates of 1.5Gb/s, with next-generation speed increases of 3Gb/s and beyond. Design teams are now using IP from Denali and TaraCom as building blocks for rapidly deploying high-quality SATA designs for next-generation electronics products."

* Mentor Graphics Corp. says it will "leverage the speed-of-thought analysis of Hyperion Essbase 7X to perform high-speed query, reporting and analysis within its worldwide operations … Other anticipated benefits include reduced storage requirements, faster availability of information, reduced total cost of ownership and the ability to expand hierarchy sizes and add dimensions."

Jan-Willem Beldman, Team Lead for Analytical Applications and Data Quality at Mentor, is looking at the time clock: "Hyperion Essbase 7X provides the analytical power we need for the integration of data, with fast load and calculation times. Within finance alone, we've already seen dramatically increased retrieval times in some of our very complex P&L spreadsheets. They've gone from seven minutes to seven seconds."

[Leave early – take the rest of those 6 minutes, 53 seconds as comp time.]

* Semiconductor Manufacturing International Corp. SMIC) announced the availability of a new Advanced Design System (ADS) design kit for its 0.18-micron CMOS process for microwave, RF, mixed-RF, analog, and digital IC design. The company says the new kit contains sets of both passive and active elements, for simulation using ADS, and is designed for use with Agilent Technologies' ADS EDA software.

Paul Ouyang, Vice President of Design Services at SMIC, is quoted: " Having ADS inside our kit gives our customers the advantage of using Agilent's proven expertise in microwave and RF IC design. Our customers can be confident about the accuracy of their designs when they use this new kit with the powerful ADS simulation technology."

* Sequence Design announced CoolPower, which the company says is "a power optimization toolkit for leakage power, dynamic power, and voltage drop optimization in SoC designs."

The Press Release continues: "CoolPower features multiple power optimization techniques including the industry’s first capabilities for optimizing leakage power using MTCMOS power-gating, and voltage drop reduction with decoupling capacitor insertion and placement optimization. MTCMOS power gating is a circuit technique for reducing leakage power by 10X to 100X, but is difficult to implement without advanced design automation. CoolPower completely automates the design and implementation of MTCMOS power gating with minimal effects upon circuit area, circuit performance, and design time. CoolPower also automatically repairs voltage drop problems by modifying the layout to move dynamic voltage drop aggressors to less critical positions and by inserting, sizing, and optimizing the placement of decoupling capacitors. CoolPower has achieved, on customer designs with decoupling capacitors inserted by other tools, improvements of 47mV in worst-case voltage drop, as well as similar worst-case voltage drop using only 15 percent of the previously inserted decoupling capacitors."

* Silicon Dimensions, Inc. announced that TeraRecon Corp. has purchased its Chip2Nite tool.

Michael Munsey, Vice President of Marketing for Silicon Dimensions, is pleased: "TeraRecon's image processing technologies advance the performance, quality, functionality, and integration of image processing and 3D visualization systems. Their designs push the envelope of physical chip design making them perfect candidates for the early design-planning capabilities of Chip2Nite."

* Stone Pillar Technologies Inc. announced Version 4.0 of its Stone Pillar Suit.

Per the Press Release: "Within Version 4.0, the latest release of Stone Pillar TestChipBuilder adds improved support for collaboration by test chip development teams. Object-oriented capabilities now available within TestChipBuilder enable the creation of shared libraries that can be used by entire test chip development teams. In addition, the new version provides process mapping to allow parameterized devices to be used across different process technologies. Version 4.0 also adds support for Keithley test equipment to the automated test plan generation capabilities offered by Stone Pillar TestPlanManager … Version 4.0 also provides enhanced capabilities for process flow management through recipe library support. The impact of changes to library recipes can quickly be analyzed and modifications can be propagated into all process flows where they are used. "

* Synopsys Inc. announced that Renesas Technology Corp. has taped out a 90-nanometer SoC design for wireless applications using Synopsys' Galaxy Design Platform.

Teruaki Harada, Department Manager of the DFM & EDA Technology Development Department in the Design Technology Division at Renesas, is quoted: "With this being our 90-nanometer wireless design, we were concerned about DFM issues. The yield enhancement techniques in Synopsys' Galaxy Design Platform, particularly the Astro product's ability to insert redundant vias and efficiently enforce antenna rules, helped us significantly optimize our design and achieve our 90-nm yield targets."

* Synopsys also announced its VCS RTL verification tool was used by STMicroelectronics "to achieve its verification quality goals in half the time for its next-generation 90-nanometer STD2000 family of HDTV processor chips." The companies says it was a 10 million-gate design targeted at television applications.

Sebastien Francois, Verification Manager at STMicroelectronics, is quoted: "We chose the VCS solution because it delivers the highest performance for the implementation of our coverage-driven verification environment. Our comprehensive regression suite tracks various coverage metrics to determine verification progress. With built-in, comprehensive coverage metrics, the VCS solution provides the performance and the breadth of coverage technologies required to achieve our verification goals in the given time."

* Virtio Corp. announced a joint effort with Freescale Semiconductor to model several of Freescale’s processor platforms for cellular convergence applications. Freescale's VPMX31 Virtual Platform for the i.MX31 and i.MX31L multimedia application processors is now available.

Please note per the Press Release: "Virtual Platforms provide software developers with a functional-level model that can boot an OS and run application code long before hardware becomes available, speeding new system software development. In addition, Virtio’s Virtual I/O technology allows developers to connect external hardware such as display panels, microphones and speakers to the platform through the host PC and evaluate software in a full system configuration. The platform can also simulate peripherals such as memory modules that contain the program code."