** TTP Communications plc. and ARM announced a "strategic collaboration" to design and develop next-generation 3G IP platforms, which use ARM processors and TTPCom Cellular Baseband Engine (CBEmacro) technology. The companies says the new platforms will "significantly reduce engineering effort and time-to-market for semiconductor vendors developing 3G SoC solutions." TTPCom says it will distribute this combination of technologies to semiconductor manufacturers. Meanwhile, .ARM says it will be responsible for licensing the processor core to its silicon partners "whilst TTPCom will license the CBEmacro technology."

** TDA Systems Inc. announced a new S-parameter tool, which allows differential S-parameter measurements based on Time Domain Reflection and Transmission (TDR/T) data. The company says the new tool is available as a stand-alone product or bundled with TDA’s IConnect software, and is designed to provides a way to establish differential S-parameter measurements in "the digital design, electrical-compliance testing and signal integrity communities." The company says this will provide "cost savings up to 2X over traditional differential S-parameter measurement techniques for test engineers who need to ensure electrical standard compliance for Serial ATA, PCI Xpress, Infiniband, and XAUI/Gigabit Ethernet, or need to perform differential S-parameter measurements for signal integrity analysis."

Richard Yates, TDA Systems Director of Sales, is quoted in the Press Release: "This capability provides a low-cost solution for differential S-parameter measurements for digital designers, while giving the customers a potential upgrade path to full signal integrity analysis and modeling capabilities that IConnect provides. Many of our customers requested this capability and I am extremely proud of the work done by our design team to make it a reality."

** TDA also announced version 3.5 of its IConnect and MeasureXtractor TDR and VNA software, which the company says includes the new S-parameter functionality. Per the Press Release: "IConnect and MeasureXtractor allow engineers to accurately predict the complete effect of the gigabit interconnects on the design signal integrity with minimum amount of effort and time, reducing design time and cost."

** Taiwan Semiconductor Manufacturing Company (TSMC) announced what it calls "a full suite of internally developed libraries that support its industry-leading Nexsys 90-nanometer technology. The TSMC libraries provide the most accurate links to TSMC technology, supporting design methodologies represented by major EDA, package and IP vendors. Developed collaboratively between TSMC library development and process development teams, the libraries support the Nexsys general-purpose (G), high performance (GT) and low power (LP) processes. … Already in volume production, the libraries are TSMC Reference Flow 5.0 proven and (DFM) compliant."

Please note: "TSMC's 90-nanometer libraries feature gate densities of 420K gates per mm2, about double the density of the 0.13-micron generation libraries. The tapless options allow designers to further reduce leakage power with a back-biasing technique, making them ideal for long battery-life applications. The standard cell libraries also come with a set of engineering change order (ECO) cells that allow for metal-only chip design updates."

Per Ed Wan, TSMC Senior Director of Design Service Marketing: "TSMC's high-density libraries and unique circuit under pad (CUP) I/Os allow designers to build functionality in the smallest possible chip area. These libraries are free of charge and can be downloaded from TSMC's library distribution partners, Cadence Design Systems, Synopsys, Artisan, and Virage Logic. They provide easy, no-hassle integration, maximum cost savings, faster time to market and, ultimately, faster time-to-revenue."

** Synplicity, Inc. announced enhancements to its Synplify DSP software, which include "new DSP synthesis optimizations for performance and area, additional Blockset functionality, including support for saturation / rounding, and a customizable DSP block library, allowing designers to quickly add custom DSP IP to their library. The Synplify DSP software provides users of the Simulink design environment from The MathWorks with the industry's only technology-independent DSP synthesis path from Simulink to hardware, enabling designers to select their FPGA of choice for hardware implementation. Synplicity's Synplify DSP software optimizes Simulink designs by quickly producing circuits that can deliver faster performance and smaller area than alternative DSP implementation tools." That probably says it all.

Ken Karnofsky, Marketing Director for Signal Processing and Communications Products at The MathWorks, is quoted: "Synplicity provides the only DSP synthesis tool that takes advantage of Simulink Fixed Point, which gives users access to the full power of the Simulink design and analysis tools. By leveraging the fixed point data types, data is automatically propagated through the Synplify DSP block set in Simulink without the need for designers to insert gateways into their Simulink design."

** Sonics, Inc. announced that Toshiba Corp. will design the SonicsMX and Sonics3220 SMART Interconnects "into its family of wireless handheld products." The companies say that Toshiba currently uses Sonics’ Silicon Backplane SMART Interconnect and Sonics’ MemMax Memory Scheduler in its processor-based digital consumer products, so this announcement marks Toshiba’s endorsement of the entire Sonics product offering for deployment into its SoCs for wireless and digital consumer applications.

Takashi Yoshimori, Technology Executive, SoC-Design of Toshiba’s Semiconductor Company, is quoted in the Press Release: "Leveraging pre-designed and pre-verified internal interconnects is a big part of our overall SoC development strategy and Sonics adds strategic value in this regard. We had confidence in Sonics given the significant benefits we have already realized using the company’s other products. The decision to use SonicsMX was based on its unparalleled feature sets when compared to other interconnects we investigated. MemMax was selected to enable us to use conventional DRAM controller designs while increasing the data throughput so we can maintain high utilization of Sonics interconnect IP."

** SilTerra announced it will provide Virage Logic Corp.’s IPrima Foundation Platform to Its 130-nanometer process customers The companies say that IPrima Foundation contains memory, logic and I/Os that are optimized to SilTerra’s 130-nanometer process in order to attain "superior performance and manufacturability." Under the terms of the agreement, SilTerra customers will be able to download design kits containing Virage Logic’s IPrima Foundation IP Platform from the "Members" section of Virage Logic’s website.

Bruce Gray, President and interim CEO of SilTerra, is quoted in the Press Release: "We were very impressed with Virage Logic’s silicon-proven IP at the 180nm node and liked their superior customer support. We wanted to provide our customers with the most robust design libraries so their products can take full advantage of our 130-nanometer process capability and ramp up for volume production quickly. By leveraging Virage Logic’s expertise as a leading semiconductor intellectual property provider, our customers will have access to the highest quality libraries in the industry."

** Meanwhile, Virage Logic also announced it is extending its distribution model from a customer-paid licensing and royalty-bearing model to include a new "Foundry Pays" option in which foundries can license Virage Logic IP directly and provide it to their customers.

Adam Kablanian, CEO and President at Virage Logic, is quoted: "SilTerra is on a fast-track to growth, and we believe their decision to provide our IP to their customers under our new Foundry Pays model will help them escalate that growth further by providing a differentiator that will allow them to penetrate their desired markets quickly."

** Silicon Dimensions, Inc. announced support for AMD's 64-bit Linux platforms in its Chip2Nite suite, so now Chip2Nite users can have access to "64-bit computing with applications involving large data sets and computationally intensive tasks." The company says that Chip2Nite currently supports Red Hat 7.2, 7.3, and 8.0 and Red Hat Enterprise Edition 2.1 and 3.0.

** QuickLogic Corp. announced the company’s Eclipse II family of "ultra low power FPGAs is now available for applications requiring components that operate over the industrial temperature range. All Eclipse family members are qualified for operation at the extended industrial temperature range (-40 degrees to +100 degrees Celsius device junction temperature)."

"Many applications require operation over the industrial temperature range, including ruggedized handheld devices, portable instrumentation and test equipment, as well as avionics and civil aerospace systems. Along with the benefits of ultra-low power consumption, Eclipse II also provides small form-factor packaging, instant-on capability and bulletproof design security from IP theft and reverse engineering."

Brian Faith, QuickLogic’s Director of Logic Products, is quoted: "With industrial temperature qualification, many new applications are available for QuickLogic’s popular Eclipse II family of low-power FPGAs. With minimal power dissipation, systems using Eclipse II components benefit from less heating and, if battery operated, the ability to employ smaller battery systems, reducing system size, weight and cooling requirements."

** EMA Design Automation announced that RadiSys Corp. has adopted the Cadence Allegro system interconnect design platform 600 series for "company-wide usage. RadiSys has design centers worldwide and develops advanced embedded solutions for the commercial, enterprise and service provider markets. These complex designs demand that the software tools employed handle high-speed design requirements and very dense, refined designs. RadiSys required a tool to support complex constraint-driven designs, front to back, with seamless integration throughout all facets of the design process."

Bob Brady, Manager, Global Infrastructure at RadiSys, is quoted: "The speeds of our applications are too fast and the designs too complex to insure high quality, consistent, reliable output, without a world-class tool infrastructure in place," said "The Allegro 600 series, coupled with EMA’s level of support and dedication to its customers, made this a win-win decision for us."

** Chartered Semiconductor Manufacturing says it has begun prototyping customer products at its first 300mm facility, Fab 7, at multiple advanced technology nodes. The company says the 300mm pilot production activities are currently running on Chartered’s 0.13-micron process, the 90-nanometer cross-foundry platform jointly developed by Chartered and IBM, and the 90-nanonmeter SOI process "tuned to IBM’s high-performance product needs."

More importantly, the Press Release says that, "To date, Chartered’s Fab 7 has demonstrated functional silicon results from its 0.13-micron, 90nm and 90nm SOI processes that out-perform or are on par with industry benchmarks. The initial defect density metrics from Chartered’s 300mm pilot lines are meeting or exceeding customers’ expectations. [And], additionally Chartered is implementing PDF Solutions’ Characterization Vehicle Infrastructure across Fab 7’s processes to optimize design rule to process margin sensitivity.

** Celoxica has announced an agreement with Toshiba Corp. to "provide its DK Design Suite of C-based ESL design and synthesis tools for application design and development using Toshiba’s Media Embedded Processor (MeP) digital media SoC. The multi-year deal covers C-based design entry, simulation, co-simulation and synthesis, as well as development hardware, through the availability of a MeP RapidPlatform developers’ kit, and worldwide marketing and promotion in key market segments … Complete system simulation between custom IP and library IP is enabled through a dedicated co-simulation framework that unites Celoxica’s DK simulator, Toshiba’s MeP ISS and RTL simulators … The hardware implementation code generated by the DK Design Suite is directly equivalent to the source simulation models, dramatically reducing design risk and the burden of verification."

Tohru Furuyama, General Manager, SoC R&D Center, at Toshiba, is quoted: "MeP provides a powerful and flexible digital-media SoC platform and it is necessary that our development flow and tool chain is also powerful and flexible. We chose to work with Celoxica as it has the proven tools in C-based design and synthesis that enables our internal and external customers to design more quickly, with lower risk."

** Arithmatica, Inc. announced an integrated, front-end flow for mutual customers of Arithmatica and Cadence Design Systems, Inc., which the companies say will improve quality of silicon for "math-critical" chips. The new flow was developed as part of the Cadence OpenChoice Program and includes Arithmatica CellMath silicon IP and Cadence Encounter RTL Compiler synthesis and Conformal formal verification tools. Users of the flow will be able to verify equivalency to design specifications.

Per the Press Release: "The new integrated flow improves silicon end-results for math-critical chip design in two key ways. First, Arithmatica's work with Cadence ensures that CellMath IP, delivered typically as a gate-level netlist, is proven against the bit-accurate Verilog simulation model with the aid of Cadence's Conformal formal equivalency checking technology, which includes unique data path capabilities to verify equivalence of the behavioral model and netlist. Second, use of Encounter RTL Compiler ensures that the CellMath IP architectures are efficiently integrated and optimized within an overall chip design."

Jan Willis, Senior Vice President of Industry Marketing at Cadence, is quoted in the Press Release: "Cadence's growing strengths in the RTL design and verification space are leveraged by integrating quality IP with Encounter RTL Compiler. Our collaboration with Arithmatica will enable customers to bring their designs to market faster and with higher quality of silicon."

Chris Malachowsky, Co-founder and Vice President of Hardware Engineering at NVIDIA, is also quoted: "NVIDIA relies on this type of collaboration to help us reach new thresholds of graphics performance within very aggressive design cycles. Gaining the performance of CellMath IP while using multiple synthesis vendor flows has helped us set the bar for GPU performance with the NVIDIA(R) GeForce(TM)6 series GPU, which some have called 'a gamer's dream.'"

** Applied Wave Research, Inc. announced that the company will provide its Microwave Office design suite to Eagle Test Systems (Eagle) to simulate performance of RF boards that are part of the Eagle’s ATE products.

Steve Dollens, Vice President of Product development for Eagle Test Systems, is quoted in the Press Release: "After evaluation of competing solutions, we chose AWR’s Microwave Office design suite for its ability to correctly predict our RF measurements. The speed, ease-of-use, and unique model validation tools (in particular the "SMODEL" measurement) offered in the AWR software will enable us to accurately simulate our designs, eliminate product issues prior to incurring the expense of fabrication, and minimize issues at the test bench."