Things - tools & technology November 28, 2005
************************************ The Dawn of a New Age … "The unprecedented, rapid support the EDA industry has shown for this standard indicates a new age of improved interoperability among EDA tools." * The IEEE announced that it has approved SystemVerilog, IEEE Std 1800-2005, as a new standard and has approved Verilog, IEEE Std 1364-2005, as a revision to Verilog. The SystemVerilog IEEE Std 1800-2005 and Verilog IEEE Std 1364-2005 will be available for purchase under the IEEE store. Per the Press Release: "SystemVerilog extends the Verilog language, the predominant language used for chip design, to address the growing complexity of electronic system and semiconductor designs. SystemVerilog is a unified language for hardware design, specification, and verification that was developed within the IEEE Standard Association's Corporate Program. The revision to the Verilog language standard resolves several ambiguities and corrects minor errors." * Meanwhile, Accellera issued its own commendations in a separate Press Release. "Accelera welcomes the IEEE announcement that it has approved the SystemVerilog hardware description and verification language as IEEE Std.1800-2005, 'Standard for SystemVerilog Unified Hardware Design, Specification and Verification Language.' The rapid approval by the IEEE through its Corporate Standards Program finalizes the accreditation process and provides design and verification engineers assurance that their SystemVerilog SoC designs are based on a single, stable standard." "SystemVerilog was developed as an extension to the widely used Verilog hardware description language. It began in Accellera with donations from Accellera member companies BlueSpec, Mentor Graphics, Motorola, Novas, Real Intent and Synopsys, as well as user-driven enhancements. It was transferred to the IEEE for ratification under its new Corporate Standards Program and took only a little more than one year to move from transfer to ratification by the IEEE. This timeline is in striking contrast to the three-to-five years that EDA standards typically used to require." "Thanks to the fast ratification process, EDA companies are now able to introduce even more tools that support SystemVerilog. All tool developers can feel comfortable developing products that support the full standard. To date, there are more than 75 announcements of tools and services for SystemVerilog from Accellera member companies and the industry at large." "The unprecedented, rapid support the EDA industry has shown for this standard indicates a new age of improved interoperability among EDA tools." Shrenik Mehta, Accellera Chair, is quoted in the Press Release: "The approval process was expedited due to close cooperation among EDA tool providers, semiconductor and system companies, Accellera and the IEEE. The approval of this standard is a sterling example of how an industry can work towards a common goal for the benefit of the entire design and verification community." The Accellera Press Release also included quotes and kudos for the IEEE from Synopsys, Mentor, Cadence, and Real Intent. ************************************ Veril-e I say unto you … * Cadence Design Systems announced that it has "stepped up its support for the IEEE P1647 e standardization effort." The company says has contributed resources for technical editing and program management to ensure the standard is of the highest quality and completed on time. The Cadence contribution comes as increased participation and interest in the IEEE working group has enabled a dramatic compression in the schedule for completion. Technical content of the standard was completed June 6, 2005 - four months ahead of schedule. Per the Press Release: The e language is an extremely powerful and mature system-level verification language that is in use today by an overwhelming majority of industry leaders in consumer electronics, telecommunications, semiconductors and IP. By standardizing the language within IEEE and opening it up to development, customers will benefit as market-leading products such as Specman Elite, which has been used to verify thousands of designs, are joined by a burgeoning marketplace of e-based tools. Jeff Vanderlip, Director of ASIC Marketing at LSI Logic, was first in line: "LSI Logic applauds Cadence's increased support for the IEEE P1647 e standardization effort, and would like to see standardization of the e language so that it is open and available to everyone." Then John Goodenough, Director of Design Technology at ARM, said: "e has been an integral part of our verification methodology, and it is good to see it move closer to standardization. We expect that this process will encourage the proliferation of competitive tools based on the e language and will be extremely positive for our partners since it ensures the stability of e and provides them with a choice of tools." Scott Sandler, CEO of Novas, said: "We fully support open standards. Faster standardization of e will benefit our customers and the language itself." Finally, Victor Berman, Director of Language Standards at Cadence, said: "With project and process level automation becoming more and more critical, Cadence has come to the realization that the best way to support customers is to offer support for standards that address the needs of each specialist in the verification process. We don't subscribe to the approach that dictates to users the language they must use for a given task. The bottom line is we support choice." The e functional verification language is expected to be standardized by the IEEE by March 2006. ************************************ Embedded in the field … * ACE Associated Compiler Experts say a group of software tools and library vendors have announced support for the Embedded C language extensions in their products. After having been officially approved by the ISO/IEC Technical Committee in early 2004, TR 18037 Programming Languages - C - Extensions to support Embedded Processors now is backed by a substantial range of supporting tools, paving the path for broad acceptance in the embedded applications realm. * CoWare has announced support for automated generation of Embedded C compilers integrated in its LISATek product range. * Byte Craft Ltd. will provide full support for the Embedded C language extensions in its C cross-compilers. * The Edison Design Group now provides support for Embedded C in its EDG C/C++ compiler front-end technology. * ACE Associated Compiler Experts provides the capability for generating Embedded C compilers. * Japan Novel and Perennial each now offer specific features in their products and services for testing, measuring and validating Embedded C compliant compilers. * Dinkumware provides implementation of the Embedded C library plus the associated runtime code included in its Dinkumware C libraries. * Per the Press Release: "Based upon these technologies, more Embedded C compilers and support tools can be expected in the foreseeable future." ************************************ In related news … CoWare Inc. and ACE Associated Compiler Experts announced a "multi-year strategic alliance in which CoWare continues to deliver ACE's C-Compiler technology deeply integrated into the CoWare LISATek processor design tool suite. In addition, CoWare and ACE will closely cooperate on future technologies to address multi-processor system design." Alan Naumann, CEO of CoWare, is quoted: "Over the last several years, our processor design customers have confirmed that ACE has the strongest technology for C-Compiler development, which they enjoy as part of our LISATek tool suite." Martijn de Lange, Chairman of the Board at AC, is also quoted: "We are pleased to continue and expand our successful relationship as it will broaden the impact of our technology as part of a new design paradigm." ************************************ 65 nanometers on the move * Cadence Design Systems, Inc. announced the Encounter digital IC design platform helped Silicon & Software Systems (S3) to tape out a new production 65-nanometer design. The companies say the 500-MHz consumer computing device, which was designed under contract for a "major European customer," will be manufactured in a "leading European" 65-nanometer silicon wafer fab and is expected to reach very high production volumes. The names have been withheld to protect the innocent. * Cascade Microtech announced the company "expanding its capabilities in the semiconductor failure analysis market." Cascade says it has entered into a business and technology partnership with Credence Systems Corp. to "expand its failure analysis market penetration. The terms of the relationship were not disclosed." John Pence, Vice President of the Engineering Products Division at Cascade, said: "As process development costs soar due to shrinking process nodes, accurate failure analysis is more critical than ever to semiconductor manufacturers. The partnership continues Cascade Microtech’s reach into the semiconductor failure analysis market. We intend to expand our failure analysis solutions through strategic relationships and unique products. Credence’s leadership in complete offerings of proven 65-nanometer debug and diagnostics equipment is strategic to Cascade’s launch of our Failure Analysis product line." * Infineon Technologies AG and Chartered Semiconductor Manufacturing announced an agreement for the manufacturing of 65-nanometer logic products. Infineon says that Chartered will manufacture its low-power mobile-phone products, with initial prototypes expected in Q1 2006 and production scheduled to begin in Q4 2006. The Press Release says, "This announcement builds on the joint 65nm technology development efforts between IBM, Infineon, Chartered and Samsung … During the next few months, employees from Infineon sites in Europe and the U.S. will deploy to Chartered to ensure the seamless integration of the process technology into Chartered’s 300-millimeter facility, Fab 7. Meanwhile, more than 200 engineers from the four participating joint development companies continue to work together on the development of next-generation technologies, including 45 nanometers, in East Fishkill, New York." In recognition of the significance of the announcement, the heavy hitters for both Infineon and Chartered are quoted in the Press Release: Wolfgang Ziebart, President and CEO of Infineon: "The traditional positioning of semiconductor companies along the entire value chain from development through to production and sales for logic products is in the process of changing and is therefore subject to optimizing capital investment and business development. Infineon has decided to have the 65-nanometer technology, developed together with Chartered, IBM and Samsung, produced by Chartered in order to further expand its leading position in customized products while achieving profitable growth" Chia Song Hwee, President and CEO of Chartered: "Chartered and Infineon already have a strong development and manufacturing alliance, and this is an exciting next step. As a joint development alliance, Chartered, Infineon, IBM and Samsung are realizing significant economical and technological advantages by pooling resources and broad expertise. In this latest step, Infineon will benefit from a seamless transition from development to manufacturing with one of its development partners, leveraging the manufacturing flexibility Chartered offers. Infineon can continue to focus on differentiating itself through development of low-power and customized products, while Chartered provides a reliable and cost-effective outsourcing solution to address Infineon’s manufacturing needs." ************************************ Other teeny tiny transistors … * eASIC Corp. announced that Fujitsu as a foundry supplier for the company's 90-namometer structured ASIC devices. The companies say eASIC's programmable ASIC manufacturing flow utilizes maskless direct-write eBeam technology, so Fujitsu is an ideal foundry partner with its in-house eBeam machine. Following initial tape-out of the 90-nanometer structured ASIC array, the product is currently under further testing and development and is scheduled to be released in the first half of 2006. * Ponte Solutions, Inc. that Renesas Technology Corp. has adopted its model-based yield analysis technology for critical area analysis and enabling reduction of yield-loss due to random defect-limited yield issues. The two companies will work together on more advanced analysis, addressing systematic defect issues for 65-nanometer technologies. Dr. Nakaya, Executive GM at Renesas, is quoted: "We anticipate Ponte’s potential to deliver a comprehensive solution for our yield analysis and enabling enhancement for defect-limited yield issues." Alex Alexanian, Ponte’s President and CEO, also is quoted: "Renesas has advanced nanometer technologies and we are very excited that Ponte’s model-based yield analysis technology was chosen by Renesas in 90-nanometer and 65-nanometer design nodes for pro-active analysis of silicon yield sensitivity, enabling yield enhancement at the design stage." * S3 Graphics says it is using Sequence Design's CoolTime for dynamic voltage drop analysis and optimization of its 90-nanometer products. Michael Shiuan, Vice President of Engineering for S3, is quoted: "CoolTime replaces point analysis tools that can only analyze one electrical effect at a time. By integrating the analysis of power, electromigration, voltage drop, timing, and signal integrity into a concurrent database, it reduces design and analysis iterations up to four times." * Synopsys, Inc. and UMC announced a 90-nanometer reference design flow that the companies say is optimized for low-power SoC designs. Per the Press Release: "The validated RTL-to-GDSII design flow is based on Synopsys’ Galaxy Design Platform, ARM Artisan SAGE-X standard cell library, and UMC’s 90-nanometer process. It addresses leakage power challenges at 90 nanometers and provides advanced DFM capabilities for faster yield ramp and lower development costs … The reference design flow also features multi-threshold (MVth) optimization to take advantage of the available UMC 90-nm multi-threshold libraries for leakage power reduction. In addition, the flow supports advanced signal integrity capabilities to perform analyses for electromigration and voltage drop (IR) that are crucial in avoiding design failure in 90-nanometer and below designs." Ken Liou, Director of the IP and Design Support Division at UMC, is quoted: "At UMC, we recognize the importance of working with leading EDA companies such as Synopsys to deliver silicon-validated reference design flows that address the SoC design challenges encountered at nanometer technologies." Rich Goldman, Vice President of Strategic Market Development at Synopsys, is also quoted: "Our close relationship with UMC helps ensure that the reference flow will satisfy the demands of even the most advanced designers dealing with 90-nanometer process design issues in power optimization and design for manufacturing and yield." ************************************ 0.18 micron still lives … * Tower Semiconductor Ltd. announced a collaboration with Cadence Design Systems, Inc. to deliver a reference flow targeting SoC designs at 0.18-micron using Tower's CMOS mixed-signal process. In addition, Tower has joined the Cadence foundry partner program. ************************************ There's no future in old age … * Pyxis Technology announced it is developing "new IC and SoC routing software for complex nanometer IC designs. The new software will have an architecture optimized for the challenges of sub-100 nanometer manufacturing process technology. It is expected to reduce design-based yield limiters by optimizing designs for a given manufacturing process, reduce the time spent on timing closure, simplify the post-tapeout flow, and improve design yield." Naeem Zafar, President and CEO at Pyxis, is quoted: "Current chip design flows are aging, and they are breaking at 90 namometers and below. Current routers are not architected to pass design intent forward, cannot optimize designs for manufacturability and are unable to make trade-offs, so yield suffers. Chip designers need new routing architectures that can scale with the new nanometer technology nodes." Per the Press Release: "Pyxis’ new architecture is centered on DFM. With novel algorithms that make it aware of the manufacturing flow, the software enables designers to trade off between design and manufacturing constraints during design – not after the chip is in the hands of manufacturing. Design intent is passed forward to mask data preparation steps, which simplifies manufacturing cost and time … Passing thousands of constraints from manufacturing to design has become far too complex, requiring a change in approach from design rule checking (DRC) rules to DFM models. Not only are there too many rules for sub-100nm designs, but also many of the 'rules' are really guidelines or suggestions – 'soft rules' rather than 'hard rules.' New routing architectures must understand the new DFM models and be able to handle all the constraints intelligently." Jim Solomon, Founder of Cadence Design Systems, EDAC Kaufman Award winner, and a member of the Pyxis Board of Directors, gets the final word: "Yield is no longer just area and random defects. Design drives yield, and design must be done differently to address all types of yield – parametric, systematic, and statistical. Pyxis has the experience, the long-range vision, and the team to execute on their goal of providing a routing architecture that is truly optimized for sub-100 nanometer technology nodes." ************************************ In other news … * Agilent Technologies Inc. announced an agreement with Auriga Measurement Systems to jointly develop and market integrated device-modeling systems. The companies plan to pair Agilent’s IC-CAP parameter extraction and device-modeling software and instrumentation with Auriga’s test instrumentation. The first system planned is a pulsed-bias/pulsed-RF solution for isothermal characterization and modeling. Auriga also says it plans to develop software modules for Agilent’s IC-CAP software, providing measurement and hardware drivers to allow data acquisition, and new device-model extraction routines for Auriga device models. Auriga will port its Tajima advanced FET model into Agilent’s ADS and IC-CAP device-modeling software. * Meanwhile, Agilent and Mentor Graphics Corp. announced an "integrated solution" enabling high-volume diagnosis for logical and physical failure analysis in the semiconductor manufacturing test flow. The companies say Agilent's 93000 Pin Scale test system and the Mentor Graphics YieldAssist diagnostics software together will provide manufacturers working at 90 nanometers and below an integrated online diagnostic capabilities, enhanced initial design debug, ongoing yield improvement, process control and quality assurance throughout the manufacturing process.
Robert Hum, Vice President and General Manager for the Design Verification and Test division at Mentor Graphics, says he likes it: "As manufacturers go into volume production with 90-nanometer designs and below, the initial yield ramp and the detection and isolation of design-specific systematic defects is a key challenge. The open third-party interface of the 93000 Pin Scale system enabled smooth collaboration based on a standardized exchange format." * Altium Ltd. announced the release of Designer 6.0, which the company says is a "new and significantly upgraded version of its groundbreaking unified electronic product development system." Per the Press Release: "Altium Designer 6.0 strengthens Altiums unified approach to design by addressing the challenges posed by the increasing use of programmable design elements to create smarter products that process data at ever-increasing speeds. Altium Designer 6.0 provides a single, unified application that incorporates all the technologies and capabilities necessary for complete electronic product development. It integrates board- and FPGA-level system design, embedded software development for FPGA-based and discrete processors, and PCB layout, editing and manufacturing within a single design environment. This, combined with enhanced support for modern design data, document and project management capabilities, makes Altium Designer 6.0 the first complete solution for electronic product development." Nick Martin, Altium CEO, is quoted: "In the development of Altium Designer 6.0 we’ve taken a strategic approach to addressing industry trends and the current and future needs of our customers. The electronics industry is changing rapidly in response to demands for smaller, faster and more intelligent products. We are committed to providing our customers with the capabilities they need – not only today, but moving into the future." * Applied Wave Research, Inc. (AWR) announced that the company's Analog Office design suite, which the company says was developed specifically for analog and RFIC design, has recently been used by a "major Japanese electronics manufacturer" to successfully design a 5.8GHz RFIC in an SiGe BiCMOS process from Jazz Semiconductor. * Cadence Design Systems announced that Toshiba Corp. and Toshiba Microelectronics Corp. taped out the first UniversalArray (UA) chip with Cadence's Encounter digital IC implementation. Per the Press Release: "Toshiba's UA is a new type of ASIC in which wafer sign-off is accomplished after the floorplan is fixed. Pursuant to wafer sign-off, mask making and place and route are processed concurrently, helping reduce total turnaround time from the design stage through manufacturing." * Cadence Design Systems also announced immediate availability of a high-performance design flow for the new ARM Cortex-A8 processor. The companies say the flow uses the Cadence's Encounter digital IC. In addition, the company announced availability of Cadence support and services to improve TTM for ARM Partners implementing high-performance Cortex-A8 processor-based designs. Mike Inglis, Executive Vice President of Marketing at ARM, says the potential is huge: "The capacity and optimization of the Cadence Encounter platform, combined with the ARM Artisan Advantage-CE library for the Cortex-A8 processor, provides a complete front-to-back flow in high-performance, low-power design." * Cadence Design Systems also announced that Hitachi Communication Technologies, Ltd. has adopted the Cadence Palladium II for emulation and acceleration. * Cadence Design Systems also announced a collaborative agreement with UMC to develop a comprehensive reference solution for complex wireless designs. The jointly developed reference solution will target UMC's RFCMOS processes, and will also include a reference design and other key technology from UMC. The reference design consists of Digital Baseband Physical Layer Blocks, Mixed-Mode 1GHz AD/DA converter blocks, RF components, along with several pieces of enabling IP from UMC. The companies plan to complete development of the reference flow over the next several months and then harden the reference design into silicon. Customers will ultimately be able to access a complete wireless reference design package from UMC. The package will include the reference design, the design flow, compatible process design kit and silicon-validation results from the reference design. Per the Press Release: "The collaboration's first key milestone -- the verification of the reference design -- has been completed using the Virtuoso platform." * Celoxica and Sundance Multiprocessor Technology Ltd. announced availability of a software-defined radio (SDR) Developers’ Kit for what the companies describe as "rapid design of next-generation wireless communications applications in the defense, civilian and commercial market sectors." Technical details abound: "The kit provides Celoxica ESL software for C-based design of SDR waveforms and Sundance COTS development boards populated with DSP and FPGA chips. The solution combines C-based and model-based design methodologies with pre-configured IP and programmable FPGA and DSP modules to enable rapid implementation of the very complex signal processing tasks required by SDR. Open application programming interface (API) specifications are provided with the kit to support the fundamental open architecture of SDR and enable creation of SDR models and IP to a single set of interfaces, independent of board level detail … The SDR Kit, supplied with interchangeable modules mounted with Xilinx FPGAs and TI DSPs is available immediately. Design software support includes Celoxica’s DK Design Suite and system level APIs, the Mathworks Simulink, TI’s Code Composer Studio and System Generator from Xilinx." * Chronology announced that it has expanded its TimingDesigner interactive timing analysis and timing diagram product to include "tighter integration with vendor-specific board design and FPGA flows. TimingDesigner version 8.0 is available immediately and also includes new timing diagram functions aimed to increase productivity, along with new usability enhancements tailored for datasheet creation and revision." New features include hand-off of timing analysis results are used as constraints to drive Quartus II place and route to increase timing accuracy. Also, post-route timing information from Quartus II is now imported by TimingDesigner for validation and visual confirmation of critical internal FPGA signal timing relationships. And, TimingDesigner 8.0 provides enhanced interfaces for board-level designers using Cadence's OrCAD Capture and Allegro PCB design tools. Finally, TimingDesigner 8.0 offers a "seamless" way to import net propagation delay information from Allegro PCB design tools.. * Chronology has also announced efforts with Altera to "increase accuracy and expedite the FPGA design process by allowing users to better manage the timing challenges inherent with high-speed design. Chronology's TimingDesigner now works closely with Altera's Quartus II, providing a smooth hand-off of critical timing data between high-density FPGAs and board-level designs, so users can identify and resolve timing issues and validate that timing constraints have been met." * Cradle Technologies says it has developed an in-house design style to minimize power consumption and uses Sequence Design tools. Amjad Qureshi, Cradle’s Director of Hardware Engineering, is quoted: "I would recommend anyone serious about minimizing power consumption use PowerTheater as early as possible in the design cycle to properly architect the RTL code, essentially designing with power in mind from the very start." * Denali announced availability of advanced simulation models for Samsung multimedia cards – MMCplus, MMCmobile, and MMCmicro. Per the Press Release: "Jointly developed with Samsung Semiconductor Inc., the new MMC memory card models use Denali's proven modeling technology, which enables system designers to deploy the models in virtually any commercial simulation or verification environment. The Denali models for Samsung MMC devices are now available online." Andy Yang, Strategic Marketing Manager at Samsung, is quoted: "We regard Denali as a key enabler for memory system design and verification. By working with Denali, we are ensuring that our customers have the highest-quality simulation models to enable rapid design and verification of new products using the most competitive standards for removable cards today." * Denali Software also says its PureSpec verification IP has been selected by Alliance Semiconductor Communications. Paritosh Kulkarni, Director of ASIC Engineering for Alliance Semiconductor, says it's great: "Denali has a product well architected to support our directed and random testing. We are now leveraging that same product architecture to address the functional verification of industry standard interfaces in our chips." * Helic S.A. and EdXact S.A. announced a joint development which the companies say will result in an extension of Helic's VeloceRF inductance modeling, verification and synthesis tool. The new offering, called VRFJ, will be based on EdXact's Jivaro netlist reduction technology. Marketed as an option to Helic’s VeloceRF, VRFJ is based on EdXact’s Jivaro technology, which comprises the most advanced netlist-reduction technology available today. RFIC designers will use VRFJ to reduce by as much as 80% the element count of inductor-heavy model netlists extracted by VeloceRF. Simulation results of "VRFJ-compressed" model netlists that are extracted at the post-layout phase of the design cycle will exhibit negligible discrepancy compared to the original "uncompressed" ones even for the most demanding non-linear analyses. Yorgos Koutsoyannopoulos, Helic CEO, is quoted: "We are about to offer to our customers superior technology that will expedite even more the RFIC design cycle. VeloceRF has been renowned for the extraction speed and accuracy of its models. Combined with VRFJ, simulation time is slashed by more than 90% even in the most demanding analyses." * IMEC says its new coarse-grain processor, ADRES (Architecture for Dynamically Reconfigurable Embedded System), supports a broad range of embedded applications. Per the Press Release: "ADRES beats the performance of state-of-the-art DSP processors, while offering the same flexibility and having the power efficiency of state-of-the-art ASIPs. The core can also be used in a multi-core context for high-performance applications … The ADRES core is a flexible architecture that consists of a tightly coupled VLIW (Very Long Instruction Word) processor and a coarse-grain reconfigurable array. The core is fully programmable from C, thanks to the co-developed C-code compiler." * Intellitech announced immediate availability of its SystemBIST IC for FPGA configuration and embedded PCB self-test. Per the Press Release: "SystemBIST provides the function of loading designs into RAM based FPGAs at power-up, it replaces the need for using serial configuration PROMs or developing software for CPU based FPGA configuration. SystemBIST provides major capabilities not found in any of the other configuration methods, that is the ability to re-program non-volatile CPLDs in-system, decision making on what FPGA bitstreams to load, and embedded PCB Self-Test using JTAG/1149.1 manufacturing test patterns embedded into the PCB." CJ Clark, Intellitech CEO, is excited but isn't naming names: "Our solutions continue to gain market share as they provide the most cost effective method to design, manufacture and support a FPGA based electronic product from cradle to grave. We've been working with an early adopter, a well-known company in the medical products field with this next generation SystemBIST since the beginning of the year. Having success during prototyping, they are going into production this month with several of their PCBs having SystemBIST designed in. While we think of SystemBIST as performing configuration for a large number of FPGAs, this customer found it cost effective on PCBs with just a single FPGA. At a later date we will report on this success story." We'll be waiting! * Kawasaki Microelectronics, Inc. (KME) and Cadence Design Systems announced that KME has completed 30+ production tapeouts of ASIC chips with Encounter RTL Compiler global synthesis. The companies says that on average, Encounter RTL Compiler achieved greater than a 10 percent timing improvement, a reduction in area of up to 20 percent, and lower power consumption due to area reduction over previously used methodology. Ah yes, that mysterious "previously used methodology" * Macraigor Systems says it has ported its on-chip debug technology, OCDemon, to the ARM 1136, iMX31 and Intel Dual XScale 81342 processors and is now offering GNU toolsets for use with these processors and Macraigor Systems interfaces. The company says engineers developing applications for these new processors can control and debug their hardware designs and application software without the use of other system resources such as UARTs, Ethernet channels or parallel ports. Macraigor is also offering a free port of the 6.3 version GNU toolkit for these processors. GDB performs four main functions to help catch bugs in the act: · Starts a program, specifying anything that might affect its behavior · Makes a program stop when predetermined conditions exist · Examines what has happened when a program has stopped · Changes variables in a program so a developer can experiment with correcting the effects of one bug and go on to learn about another. * Magma Design Automation Inc. announced that Mellanox taped out a 4-million-gate, high-performance, flip-chip device in just four days using a bunch of Magma tools – Blast Create, Blast Fusion, Blast Rail and Blast Noise. To quote the Press Release: "With Magma's integrated RTL-to-GDSII flow and a small design team Mellanox was able to significantly reduce the area of the device and achieve noise and power sign-off without additional point tools, resulting in significant production and manufacturing cost savings." * MatrixOne, Inc. announced support of the industry-standard OpenAccess 2.2 for its design collaboration and management solution. Jan Willis, Senior Vice President of Industry Alliances at Cadence, says it's a win-win situation: "Managing OpenAccess data produced by Cadence’s digital IC and custom design platforms with Synchronicity Developer Suite allows users to benefit from two complimentary solutions." Of course, you all know that: "OpenAccess is an industry-standard EDA design database specification and reference implementation published by the Si2 and supported by a wide range of leading EDA industry tools. The new improvements in version 2.2 extend the OpenAccess data model support further into digital design as well as manufacturing, providing significant levels of maturity and completeness." * MatrixOne also announced availability of a new version of the Synchronicity Developer Suite, which the company says is already in use at 12 of the top 15 semiconductor companies. Per the Press Release: Significant enhancements to Developer Suite Version 4.2 include the following: • DesignSync User Interface: includes new tools to access capabilities of HCM to create a hierarchical file structure for large SoC designs. • Broad EDA interoperability: production-level integrations to multiple data formats from any EDA tool including "home-grown" proprietary tools, and support for the latest four releases of Cadence OpenAccess, Cadence CDBA, and the latest three releases of Synopsis Milkyway database. • Tight integration to data-driven enterprise project management: enhanced integration to MatrixOne's Program Central application. * National Semiconductor Corp. and Xilinx have introduced an integrated development platform that the companies say "accelerates the design of complex, gigahertz-speed communications and test and measurement systems. The platform includes the world's highest performance Xilinx Virtex-4 FPGA, which is optimized for reduced power and superior signal integrity, and the ADC08D1500, National Semiconductor's best-in-class, low-power, 3 Giga-samples per second (GSPS) analog-to-digital converter (ADC). The board is also available with any of the other converters from National's gigahertz-speed ADC family." * Sonics Inc. announced MemMax Memory Scheduler Version 2.0. MemMax schedules and manages multi-threaded pipelined accesses to external DRAM. Per the Press Release: "Among the new features in MemMax 2.0 is support for version 2.0 of the Open Core Protocol International Partnership (OCP-IP) specification. Other features include asynchronous boundary crossing in the memory buffers of MemMax, and an increase in operating frequencies to 333 MHz based on eight threads at the memory interface." Drew Wingard, Sonics CTO, is quoted: "With the introduction of multiple processors on an SoC, and only one port to access memory, ensuring all processors have equitable access to memory presents a very complex data flow task. MemMax is a royalty free, drop-in solution providing an alternative to developing costly and time consuming in-house solutions to address this problem." * Starbridge Systems announced a strategic relationship with Silicon Graphics, whereby SGI will provide Starbridge's Viva development software under a temporary license as part of its RASC (Reconfigurable Application-Specific Computing) development kit. The companies say, "The combined solution is capable of drastically decreasing compute time for computationally intensive applications over non-optimized systems." * Synfora says the latest release of PICO Express "raises the bar on the Quality of Results (QoR) that SoC designers can achieve in real-life production designs." Per the Press Release: "The new release of PICO Express (05.02) delivers up to 29 percent area reduction on complex designs, further empowering the designer to rapidly complete a design with a QoR that is comparable with manual design. The new release of PICO Express is based on ... Synfora's D4 technology, which links compiler scheduling decisions with QoR targets (performance, area, power)... In addition, PICO Express 05.02 provides a streamlined architecture schema that allows optimal sizing and placement of boundary registers, stalling buffers, and muxing based on application or designer needs."
* Synopsys, Inc. announced that Agere Systems Inc. used IC Compiler to tape out a 90-nanometer multi-core DSP SoC for telecom applications. Jill Bennett, Engineering Director in Agere’s Telecommunications Division, is quoted: "We were able to easily deploy IC Compiler and produced better results than we could achieve before. We are encouraged by these excellent results, and are now pursuing IC Compiler deployment across multiple designs." * Tensilica, Inc. announced a new version of its Xtensa processor family, the Xtensa 6 configurable and extensible processor core for SOC design. The company says the new core is a replacement for Tensilica’s Xtensa V processor, and that adds "three major enhancements" – the ability to automatically customize it from a C/C++ based algorithm using Tensilica’s proven XPRES Compiler; approximately 30 percent lower power than Xtensa V; and advanced security provisions in MMU-enabled configurations through a "no execute" bit that provides enhanced protection against malicious code. * Virtio Corp. announced that Texas Instruments has entered into a one-year agreement with Virtio to use Virtio’s Virtual Platform for several of TI’s products, including its OMAP platform for mobile devices. Per the Press Release: "TI uses Virtio's products and services to accelerate embedded software development and system-level validation of TI OMAP application processors, reference designs and development systems. Both TI and Virtio will work together to proliferate this model for developing complete solutions to TI’s OEM customers and third parties." Avner Goren, Marketing Director of TI’s Cellular Systems Business, is quoted: "By using Virtio’s Virtual Platforms, TI is able to develop software and silicon in parallel, which enables us to deliver mature code and drivers to customers faster and speeds their time to market. This software development schedule savings equates with significant bottom-line benefits for TI and our customers." * Xpedion Design Systems and Jazz Semiconductor announced a partnership to deliver a qualified model and simulation environment for next generation RFIC design. Paul Colestock, Director of Technical marketing and Applications Engineering at Jazz, lays out the challenges: "One of the biggest challenges in completing functional RF transceiver design is the multi-tone simulation of full transmit and receive chains post layout parasitic extraction. Delays of weeks, if not months, are incurred due to either simulator capacity limitations or simulations that just fail to converge. Failure to properly account for these parasitics usually translates into multiple re-spins of the product to achieve full functionality. Jazz and Xpedion have been collaborating to validate Xpedion's GoldenGate Multi-tone Simulation capability and have seen a dramatic improvement in completing tape outs on schedule and achieving first time design success on sophisticated RF Systems on a Chip." Pete Rodriguez, CEO at Xpedion, responds in kind: "Jazz, a leading RFIC foundry, has continued to support both the quality of models delivered to customers as well as reliable manufacturing capabilities for high volume ramp. Xpedion is pleased to work with Jazz to combine modeling and simulation expertise to provide our customers the environment needed for complex consumer RFIC designs." * Zuken announces its CADSTAR 8.0 PCB design solution, which the company says includes improvements in schematic design and library management, support for variants, lead-free component technology and jumpers, and major enhancements to placement, routing, and advanced signal integrity analysis tools. The company also says the new release includes "the latest in functionality for dealing with new technology that has evolved from the introduction of new legislation such as the European WEEE and RoHS Directives and continued innovation in design processes and fabrication such as lead free soldering, soon to be mandatory in most electronics equipment in the European Union." ************************************ Ending with Best of Show … Freescale Semiconductor and Cadence Design Systems announced a multi-year agreement designed to help Freescale realize competitive advantages by boosting new product design efficiency and speeding the delivery of advanced silicon products to market. Both companies say tehy will benefit through more effective development of "products and technology solutions that better address current and future requirements of their respective markets." The agreement, which calls for the consolidation of design flows and methodologies, will enable Cadence to develop solutions to Freescale's upcoming design challenges in a more timely manner. It also provides Freescale with access to the full range of Cadence software, hardware and services products from across Cadence's various design and verification platforms, and DFM technologies. The companies say they will also collaborate on the development of new, highly advanced EDA technologies. Freescale, in particular, says the collaboration is part of a larger effort to "streamline design technology operations and establish common tools and flows across the organization." Of note: Freescale says it is reducing its roster of third-party EDA vendors to eliminate redundancies, increase efficiency and minimize costs. Cadence will be Freescale's primary supplier of EDA tools and services. However, Freescale will continue to incorporate select, specialized EDA technology from other suppliers as appropriate. Hmmm – that last bit's sort of a show-stopper. Not surprisingly, Chekib Akrout, Vice President of Design Technology for Freescale, says things are complex: "The complexities of deep submicron CMOS process technology demand new classes of tools and flows, especially below the 65-nanometer node. By collaborating with Cadence, we will overcome these complexities and realize competitive advantages that reinforce Freescale's reputation as a pioneer in the design and manufacture of highly advanced semiconductor products." Mike Fister, President/CEO at Cadence, also says things are complex, but they're pleasing as well: "Cadence is extremely pleased to have this level of relationship with Freescale and we look forward to collaborating on innovative solutions for the next generation of design and manufacturing challenges. As the complexity of design increases, strategic relationships between industry leaders are increasingly the only way to ensure mutual success." Mutual success indeed! |