Mentor Graphics Corp. and UGS announced that they have signed a joint cooperation agreement to deliver interoperability between their products, to provide "solutions" to meet the emerging needs of complex electromechanical platforms such as automobiles, airplanes and trains. The companies say the signing of this agreement represents a milestone in cooperation between leading vendors from different domains – electrical and mechanical. Both companies are investing resources to develop this integration and plan to deliver the first stage of integrated products in the second half of 2005.

Per the Press Release "UGS will enhance Teamcenter and NX product lines to further its 'mechatronics' initiative – the synergistic integration of mechanical, electrical, electronics and software technologies into electro-mechanical products. The joint cooperation agreement will lead to enhancements in Teamcenter, the world-leading product knowledge management and lifecycle collaboration platform and NX, the world-leading digital design and analysis solution. Teamcenter will provide the integrated design of an electro-mechanical product, with electrical architecture and mechatronics sub-systems definition tied together with the overall system design. NX provides an environment to do associative electrical routing through an integrated design environment."

"The collaboration will also enable more efficient management of the unique change process throughout the entire product lifecycle, leveraging the skills, data, knowledge and experience of the extended enterprise, allowing customers to work collaboratively across every stage of the electro-mechanical product lifecycle."

Chuck Grindstaff, Executive Vice President for Products at UGS, is quoted: "This is an important initiative that we have embarked upon and a key step in fulfilling our pledge to deliver industry leading solutions that work across the mechanical, electrical and software domains in Mechatronics."

** Altium Ltd. announced version 2.2 of its TASKING TriCore VX-toolset. New features are aligned to Infineon’s 32-bit TriCore microcontrollers. New features include: "Code performance improvement of up to 25%; Configurable MISRA C messages and support for MISRA-C:2004; Support for new derivatives: TC1100, TC1115 and TC1796; Build speed improvements – compiler time reduction of 55% and overall assembler improvements of around 80%, Extensive support for Infineon’s Debug Access Server (DAS) solution, and TCP/IP stack reference design as sample project."

Gerd Punsmann, Tool Line Manager at the Automotive, Industrial & Multi-Market business group of Infineon Technologies, is quoted: "Version 2.2 of the new TriCore VX-toolset clearly demonstrates Altium is continuing to set new standards as a tool partner, particularly in terms of code optimization and execution speed. With high performance automotive applications top of mind, Altium incorporated many additional optimization suggestions from our key accounts, including improved loop unrolling and conditional instructions, in the compiler to drive optimization performance levels even higher. We anticipate, under specific conditions, code performance improvements up to 25 per cent can be achieved."

** Apache Design Solutions announced the RedHawk-EV next-generation dynamic power analysis and verification tool. The company says that RedHawk-EV provides: increased coverage for design weakness identification and exploration, automatic supply noise repair for power closure sign-off, and higher capacity for transient simulation of SoC designs. Per the Press Release: "By identifying the precise locations of design weaknesses and their impact on dynamic voltage drop and ground bounce, RedHawk-EV allows designers to not only verify potential power-related functional and timing behavior, but also avoid excessive over-design."

Shinichi Kozu, Senior Engineering Manager for the Broadband LSI Technology Strategic Business Unit at NEC Electronics America, Inc., is quoted: "We have used RedHawk-SDL for complex ASIC designs over the past year. The new network-aware vectorless capability in RedHawk-EV enabled us to quickly identify several potential power structure issues in a current high-performance tapeout, which may have been more difficult to find with static-only analysis."

** Applied Wave Research, Inc. (AWR) announced an agreement with TriQuint Semiconductor, to add AWR’s Microwave Office and Visual System Simulator (VSS) software to the company’s EDA tool set.

Paul Litzenberg, Engineering Manager at TriQuint., is quoted: "TriQuint is committed to a philosophy of continuous improvement in our products, in our processes, and in our design tools. AWR’s products have proven to be a welcome part of our design approach to delivering cutting-edge products, in a timely fashion, to our customers. The seamless integration of Microwave Office and VSS software in one platform gives us the ability to simulate and lay out our power amplifier designs. We can use traditional microwave techniques, and then co-simulate with actual, complex system signals to look at adjacent channel power ratio (ACPR) and error vector magnitude (EVM)."

** Brion Technologies, Inc. announced its Aerion microlithography aerial image sensing technology platform. Per the Press Release: "The company is developing products [capable] of capturing full-field, in-scanner aerial images at resolution and at the wafer plane for 193-nanometer and 248-nanometer wavelengths, under exact production conditions such as illumination scheme, lens settings and stage speed."

Fabian Pease, who heads Brion’s Technical Advisory Board and is on the faculty at Stanford University, is quoted: "Aerion represents a major technology breakthrough in microlithography. Until now we have been able to treat the aerial image only as a modeled entity in the world of simulation. Now we can observe directly the aerial image at the wafer surface in the scanner, and as a result we have many new opportunities for significantly improving the entire microlithographic process."

** Brion Technologies also introduced its Tachyon RDI (RET Design Inspection) model-based, full-chip verification tool for the production flow of post-RET design verification. The company says the Tachyon RDI 1100 is a hardware accelerated, image-based data and simulation engine for lithography modeling and database handling.

Per the Press Release: "Tachyon alters the exponential scaling of cycle-time, yield and cost-of-ownership for various RET (Resolution Enhancement Technique) applications. The innovative technologies implemented in the Tachyon platform represent a fundamental departure from the polygon-based approach for lithography simulation and database handling. Unlike conventional edge-based sampling methods, Tachyon simulates and inspects 100 percent of the chip area with an image-based approach. Using the post-RET design data, Tachyon RDI simulates the exact wafer pattern contours across the entire chip. Wafer patterning is verified and failures are identified by comparing the simulated contours with the pre-RET design target."

** Cadence Design Systems, Inc. announced that its Encounter digital IC design platform helped Silicon & Software Systems design multiple 90-nanometer designs over the past 18 months. The companies say the designs ranged in complexity and size from 1 million to 10 million gates, and exhibited performance metrics "in excess of 600MHz."

Dermot Barry, General Manager of the System IC Business Unit at S3, is quoted: "S3 has made a substantial investment in developing flows and expertise to minimize the risks for our customers in 90-nanometer system IC design, with a focus on performance and high quality of results The SoC Encounter digital IC design tool provides the early feasibility testing and budgeting we require for our complex designs, and a rapid timing and signal integrity closure with the CeltIC and NanoRoute."

** Cadence also announced that the Cadence Encounter platform has helped GUC tapeout seven 130-nanometer designs. The companies say the most sophisticated designs – with 3 million gates and 400 MHz clock speed – were closed with all timing and signal integrity requirements met. The Press Release says, "With much of the region still at 0.18 micron or larger process nodes, GUC is pioneering 130-nanometer design in Taiwan."

Jim Lai, President and COO at GUC, is quoted: "We believe we are the first company in Taiwan to execute multiple tapeouts at 130 nanometers or below. Through our tapeout successes, we have demonstrated that Taiwanese companies are capable of doing leading-edge digital designs. Encounter is a viable and production-proven world-class technology that continues to deliver the fastest route to silicon for both mainstream and advanced process technology nodes."

** Cadence and Virage Logic Corp. announced results of a collaboration to provide library views to "better address low-power, multi-voltage nanometer design needs." Virage says it has generated and qualified timing library views that include the Cadence effective current source model (ECSM) extensions for supply-voltage delay prediction and noise library views (cdB) for signal-integrity analysis. The companies say that when used with the Cadence Encounter digital IC design platform, the new library views will allow design teams to account for crosstalk, IR drop, voltage and frequency scaling, and multiple voltage-island support required for nanometer process technologies.

Tom Chanak, CAD manager at MIPS Technologies, is quoted: "Our customers demand fast timing closure when they take our synthesizable cores to silicon. At high frequencies, SI has become a critical variable that needs to be built into any hardening flow. Having SI library views readily available allows us to get the best out of Cadence Encounter's automatic SI closure flow, enabling our customers to get to market faster."

** Celoxica Ltd. announced the availability of a new programmable SoC prototyping and development platform. The RC250 package gives designers a HW/SW desktop environment for complex system development, which is designed for the creation of high-performance, high-throughput multimedia and communications applications. The RC250 has an array of peripherals including analog and digital video I/O, two channel gigabit Ethernet and USB2.0. There is a platform support library (PSL) that allows access to the board-level features from the ESL. System level APIs supplied with the RC250 enable HW/SW co-design and architectural exploration of partitions, and assist with IP reuse by abstracting the specific board level detail away from the application code.

Jim Smith, Director of EDA Vendor Relations for Altera, is quoted in the Press Release: "Altera and Celoxica have been working together to provide embedded system developers a powerful method for accelerating software algorithms written in C to hardware functions that typically run many orders of magnitude faster. Celoxica's RC250 is the ideal environment for rapid prototyping and development of performance-optimized systems-on-chip."

** Magma Design Automation Inc. announced that Texas Instruments Inc., and Sun Microsystems will use design software from Magma as part of a collaboration on a next-generation computer system chip set. Steve Sutton, Vice President of ASICs for TI, is quoted: "TI has a long-standing relationship with Sun Microsystems producing their UltraSPARC microprocessors and now we look forward to extending that success into the ASIC arena. By collaborating with Magma on the design tools side of the equation, TI is well equipped for challenging designs within systems based on Sun's next generation of chip multithreading (CMT) SPARC processor."

Jeffrey Thomas, Vice President of CMT Systems at Sun, is also quoted: "Based upon TI's experience with the Magma software, Sun has decided to use Magma for this project. This chip set will enable Sun to maintain its leadership position in the throughput computing market."

** Magma Design Automation also announced that Enuclia Semiconductor has selected Magma’s front-end tools, Blast Create and Blast Plan Pro, to prototype designs in FPGAs and structured ASICs, and then move them into to Enuclia’s ASIC/COT (customer-owned tooling) design flow. Carl Ruggiero, CTO of Enuclia Semiconductor, is quoted: "Enuclia has been impressed with the ability of Magma’s products to provide for seamless design transitions from FPGA prototyping to structured ASIC, and ultimately to our ASIC/COT design flow. We are using Magma’s unique tools to achieve a high quality, low power design on schedule and with a smaller die size."

** ProDesign announced the availability of the CHIPit Gold Edition Pro high speed ASIC design verification platform for multimedia ASIC and SoC design. Uses range from the initial phases of design algorithm creation, through the basic IP development and debugging, to the validation of complex SoC designs and early "quasi prototyping" for firmware and software development. The first public demonstrations of the new platform will be at DATE 2005.

Joseph Rothman, Head of ProDesign USA operations, is quoted: "Many of our CHIPit customers are designers of multimedia applications who place a high value on the speed at which they can run their ASIC verification. To meet their needs our Gold Edition Pro platform allows a blazing system speed of over 200MHz. The new platform is cost effective, flexible and based on innovative methodologies that make it applicable wherever functional ASIC design verification is required."

** Prosilog SA announced the integration of Yogitech’s OCP eVC in Magillem, which is Prosilog's platform based design environment. The companies say that eVC is imported, configured and connected to the DUT (Design Under Test).

Per the Press Release: "Yogitech’s eVC is registered in the Magillem Verification IPs list, and the user can select and parameterize the OCP interfaces required for the test (OCP 2.0 or 1.0, master or slave). Then Magillem provides an assistant, compatible with the eRM (e Reuse Methodology), which generates the e configuration code. It allows to easily set all the parameters of the verification agents (master, slave or monitor) for configuration, monitoring and BFM behavior; the mapping of the e variables on the HDL signals can also be changed. Magillem generates the platform interconnection code (in VHDL, Verilog or SystemC), and the bus matrix, bridges, protocol wrappers or multi abstraction levels adapters, provided by Prosilog both as synthesizable or simulable models.

** Pulsic Ltd. announced that Elixent has licensed its Lyric Physical Design Framework. Elixent says it will use Lyric for automatic and interactive routing of its advanced cell designs for its D-Fabrix RAP cores. The D-Fabrix array is automatically compiled from a library of cells designed at the transistor level to optimize possible speed and power performance in the smallest possible area.

Kenn Lamb, CEO of Elixent, is quoted: "We believe that we will transform our approach to physical design and reduce time-to-market significantly by applying Lyric as part of our overall design flow. Lyric delivered high quality results in our detailed evaluation, reducing typical manual routing times from ten days to a few minutes and allowing us to run multiple iterations for optimum performance and silicon area. This has significantly enhanced our engineering productivity at a time when we are engaged in multiple process ports to proprietary silicon processes. Elixent has some very specific requirements for routing at transistor level within our library cells to deliver the aggressive performance and area metrics that make D-Fabrix the most competitive reconfigurable processing platform available. Lyric provides the level of flexibility and control we need to handle complex process rules and cope with all of our exacting design criteria."

** Synopsys, Inc. and Oki Electric Co., Ltd. announced that Oki has standardized on the new HSPICE high voltage MOS (HVMOS) model for the design of Oki's LCD TV driver SoC. Oki achieved unparalleled accuracy using this HVMOS model with HSPICE technology, the "Gold Standard" in circuit simulation. This high correlation between device model and silicon enables Oki to accurately design complex, high-voltage drivers that deliver vivid, ultra high-resolution images for large-screen LCD TVs and other advanced integrated circuits in its telecommunications, automotive, computer and consumer product lines. Oki has jointly validated the newly developed HVMOS model with Synopsys. The model incorporates all of the necessary and critical physical effects of various high voltage transistor technologies that are in use today.

Ichiro Yamamoto, Senior Manager, Design System Department in the LSI Design Division of Oki Electric's Silicon Solutions Company, is quoted: "We were able to obtain excellent accuracy, performance and convergence using Synopsys' HSPICE technology with the new HVMOS model and the Aurora model parameter extraction tool. Other commercial simulators with HVMOS models typically produced large variations of up to 30 percent when compared with measured data from silicon. This variability made it difficult to fit the model parameters within an acceptable accuracy range, causing several expensive and time-consuming chip re-spins. While correlating silicon within a few percent with the new HSPICE HVMOS model and the Aurora tool, Oki has reduced the model parameter extraction time from several days to two hours."

** Synopsys and ARM announced the jointly developed low-power reference methodology (RM) for implementing ARM Intelligent Energy Manager (IEM) technology in silicon. Per the Press Release "The two companies have proven that IEM technology, when used with the ARM Artisan(R) low-power library, can reduce the ARM processor energy consumption by up to 60 percent. The ARM-Synopsys Galaxy RM for IEM (IEM RM), co-developed by ARM and its Physical IP group (formerly Artisan) and Synopsys Professional Services, and is part of a multi-year collaboration between the companies for the development and delivery of ARM processors and Intellectual Property (IP). The IEM RM includes an enhanced methodology guide and scripts as "best practices" for IEM technology-enabled cores and multi-voltage design techniques in Synopsys' Galaxy Design Platform and the Artisan Metro(TM) low-power libraries."

Mike Inglis, Executive Vice President for Marketing at ARM is quoted: "Our ongoing partnership with Synopsys has spanned several years and produced comprehensive reference methodologies, protocol standards and IP to address our joint customers demands for ways to speed innovation. Synopsys provides a complete front-to back silicon-proven flow in low-power design, and is a standard in our development and delivery of ARM IP. With the Artisan Physical IP now a part of the total ARM product offering, we can offer our partners a comprehensive low-power IP solution for the entire SoC not just the ARM processor."

Sung Bae Park, Vice President of Processor Architecture Lab at Samsung Electronics, is also quoted: "Our close collaboration with ARM and Synopsys will speed the design of our next-generation low power devices for mobile applications based on the ARM1176JZF-S(TM) processor with IEM technology. Early access to the advanced low-power techniques such as IEM can give us the potential of significant power reduction with increased design productivity."

** Synopsys also announced that Virage Logic Corp. has standardized on Synopsys' ESP memory equivalency checker for the embedded memory components of its IPrima Mobile semiconductor IP platform. The companies say the resultant increase in productivity "enabled Virage Logic to trim the engineering time needed to complete functional verification of the circuits in its Area, Speed and Power (ASAP) Memory compilers from days to hours."

Alex Shubat, CTO and Vice President of R&D at Virage, is quoted: "ESP provides a tremendous productivity boost to our verification team, enabling them to complete functional verification with less effort. In addition, ESP helps us debug the functionality in our models."

** Synopsys also announced that Synopsys and Hitachi Global Storage Technologies have demonstrated 3Gb/s Serial ATA (SATA) II interoperability between Hitachi's high-performance Deskstar hard drives and the Synopsys DesignWare SATA Host Controller core.

Becky Smith, Vice President of Marketing at Hitachi GST, is quoted: "3Gb/s hard drive transfer rates will help support the growing number of applications that stream video, music and other digital content. In enterprise environments, where SATA drives are often clustered together for nearline applications, the effect of the higher transfer rate is even more important. We are pleased that our new Hitachi Deskstar drives are operating seamlessly with Synopsys' DesignWare SATA Host core."

** VaST Systems Technology Corp. announced the release of CoMET 5.7. New features in CoMET 5.7 include: Support for VaST’s models, plus integration and co-simulation with previous generations of VaST models; Support for SystemC models, standalone and integrated into full platforms; Enhanced GUI interface and configuration capabilities in VaST’s Metrix tool. Metrix 5.7 supports probes for VaST’s StdBus, StdLogic, StdVector and StdClock nets; Enhanced CoMET Platform Constructor; and Peripheral Device Builder (see below).

Alain Labat, VaST CEO, is quoted: "We are putting great emphasis on making our tools increasingly easy to use and rich in their ability to provide unparalleled visibility for designing and optimizing architectures, for concurrently developing hardware and software, and for verifying integrated systems."

** VaST Systems Technology also announced the addition of Peripheral Device Builder (PDB) to its line of virtual system prototyping tools. The company says PDB helps VaST users to develop peripheral devices such as interrupt controllers, DMA VaST engines, timers, clocks, and memory controllers. The company says that PDB provides a "common code base for VaST-generated peripheral models and enables users to create models from a high level behavioral description. The process has three main steps. First, users specify the device in terms of its external interfaces (ports), registers, and functions invoked by external or internal actions. They next generate the model from the device specification, and then contribute the behavioral code to model, if required."

Alain Labat is also quoted in this Press Release: "Many of our users rely on VaST to create their entire virtual system for them. We model the core processor, the buses and bus bridges and the peripherals, giving the user a turnkey system that runs at hardware speeds and is cycle accurate. However, some of our users want to control more of the modeling themselves. In response to this need, we have created a class of what we call 'constructor' tools. Peripheral Device Builder is the latest in a number of tools planned to give users this flexibility."

** Zuken and LogicSwap have launched a new migration offering that allows users of P-CAD to transfer PCB design data, schematic databases and incorporate libraries to CADSTAR. Users will also be able to convert back to P-CAD if required using the CADSTAR to P-CAD solution. The companies says, "This is a move to address migration concerns related to the preservation of customers' legacy EDA data, by providing solutions and services that accurately and reliably migrate design data, including EDA libraries. New tool evaluation decisions such as whether or not to abandon legacy data and fears about the loss of investment made in previous designs are no longer an issue, as the constraining factors that previously locked companies into a single supplier solution have been removed."

Werner Rissiek, Zuken Engineering General Manager, is quoted: "Robust migration tools are absolutely paramount in ensuring that our customers achieve one hundred per cent design integrity when migrating. LogicSwap's knowledge of companies' design migration requirements enables them to provide a customized solution for specific data translations."