Magma Design Automation Inc. and ChipX announced availability of a unified RTL-to-GDSII design flow based on Magma's Blast Create and Blast Fusion. The companies say they have worked together to test and customize the Magma flow to support the ChipX CX5000 family and future structured ASIC product families. Per the Press Release: "The flow will be used by mutual customers and by ChipX to deliver low-cost structured ASIC designs or to migrate FPGA designs to ChipX's structured ASIC platforms."

Fujitsu Limited, Fujitsu Microelectronics America, Inc. , and Synplicity, Inc., have announced a joint development and marketing agreement to develop a custom physical synthesis product for Fujitsu AccelArray structured/platform ASIC devices. Fujitsu and Synplicity say they will work closely to produce an optimized version of Synplicity’s Amplify physical synthesis software, specifically targeting the AccelArray architecture and enabling performance and faster overall timing closure for Fujitsu’s devices.

Catch up on the times by paying close attention to the following, extracted from the Press Release: "Under the terms of this agreement Fujitsu and Synplicity will jointly define and Synplicity will develop the customized Amplify software for the AccelArray physical synthesis product. Upon its completion, Fujitsu will offer the Amplify software as the preferred physical synthesis solution to AccelArray customers. Fujitsu and Synplicity believe that bundling the Amplify physical synthesis software with the AccelArray platform will provide customers with a more complete ASIC solution."

"According to market research firm Gartner Dataquest, the structured/platform ASIC market will experience substantial growth in the next four years. In the company’s recent report entitled 'Platform ASICs Jump-Start Market,' Bryan Lewis, research vice president and chief semiconductor analyst, contends that: 'ASIC platforms have the potential to jump-start the ASIC industry because they can now serve an increasing number of customers that had been left behind because of the rapidly rising design costs of traditional ASICs.' In addition, Gartner Dataquest predicts there will be more than 1,000 structured ASIC design starts by 2007, representing 25 percent of all ASIC design starts."

Synplicity Inc. announced that the company's newest version of the Synplify Pro synthesis software provides full support for Xilinx's Virtex-4 FPGAs. Steve Lass, Director of Software Product Marketing at Xilinx, is quoted: "The new Virtex-4 family of FPGAs is a revolutionary step in programmable device architecture, technology and system design capability, and we recognize that optimized design tools must be available to our customers in order for the unprecedented design capacity of Virtex-4 to be fully realized. Because Synplicity is committed to such advanced levels of innovation in the FPGA industry, we work closely with Synplicity to provide our mutual customers with best-in-class synthesis support that is needed to design today's advanced FPGA devices."

Synplicity also announced the latest version of its FPGA synthesis and physical synthesis software solutions. The Synplify Pro 7.7 synthesis tool includes enhancements, including support for the latest FPGA devices from Xilinx and Lattice Semiconductor. Synplify Pro software now include timing-driven synthesis support for Xilinx's Virtex-4 FPGAs and support for Lattice Semiconductor's LatticeECP and LatticeEC FPGA device families. Enhancements have also been added to the Amplify FPGA 3.7 physical synthesis software.

Meanwhile, Xilinx announced "immediate worldwide shipments" of the 6.3i release of its Integrated Software Environment (ISE), which the company says is optimized for the Xilinx Virtex-4 family of Platform FPGAs. "The new ISE 6.3i solution takes full advantage of the Virtex-4 architecture to support up to 200,000 logic cells and 500 MHz performance for twice the density and up to 10 times better performance-price ratio than previous generation FPGAs. This combination of ISE 6.3i and Virtex-4 FPGAs makes programmable systems design easier than ever across multiple domains, including high performance logic, embedded processing, high performance digital signal processing and high-speed connectivity." This last bit from the Press Release should be good news who are banking their products on Xilinx products.

Xilinx also announced the version 6.3i of the Platform Studio for system-level embedded processing design on Xilinx Platform FPGAs. Again per the Press Release: "The Platform Studio tool suite automates a host of architecture-level design steps and offers a powerful new software environment based on the industry-standard Eclipse integrated design environment (IDE). The Platform Studio 6.3i release supports the Xilinx processor solutions, including the MicroBlaze and the immersed PowerPC cores, the industry’s most popular soft and hard processors. The new 6.3i release enables system-level design for the newly introduced Virtex-4 LX, SX, and FX device families, and supports the Xilinx Virtex and Spartan-3 Series Platform FPGAs."

Meanwhile, Mentor Graphics Corp announced that its "suite of advanced synthesis products will support the newly introduced Virtex-4 FPGAs from Xilinx. Customers who use the Precision RTL or LeonardoSpectrum tools can now immediately request software that supports the full range of Virtex-4 devices, while the Precision Physical tool is offering beta-level support."

Not surprisingly, the Press Release also says, "Xilinx and Mentor Graphics have collaborated over the past year to ensure mutual customers will have support from both companies upon the release of the ISE 6.3i place and route software for Virtex-4 from Xilinx."

In the category of not wanting to show favorites, Mentor Graphics also announced the availability of the Altera Stratix GX design kit for ICX. The new design kit allows engineers using the Mentor Graphics ICX signal integrity (SI) analysis tool to perform full-board analysis on designs featuring the high-speed serial I/O technology of the Altera Stratix GX devices hundred of times faster than previously possible with SPICE-based simulation techniques.

Catalytic Inc. announced the first of what the company says will be a series of DSP design automation software products. Per the Press Release: "Catalytic's Fixed-Point DSP Studio software speeds floating-point to fixed-point conversion for users implementing systems using C or RTL. It shortens implementation time for fixed-point DSP algorithms by providing fixed-point variables in MATLAB from The MathWorks, accelerating MATLAB verification simulations up to 20X."

The Press Release includes a quote from Paul Zorfass, Senior Analyst with IDC/First Technology: "The Catalytic Fixed-Point DSP Studio has the potential to significantly improve the software engineering development cycle for products exploiting DSP capabilities. The Studio product has the ability to provide increased value and improvements in productivity, efficiencies and documentation for DSP-centric solutions."

CoWare Inc. announced a new version of the company's SPW DSP application "solution" - SPW 5-XP for Windows. CoWare says the new release "offers radical new features and functionality to make DSP application design faster and easier. These include unmatched integration with MATLAB that accelerates implementation starting from MATLAB algorithms; a Windows look & feel and GUI; and an open, extendable, standard XML database .. along with SPW's core strengths: the speed of its simulation engine and its library of more than 4,000 proven DSP application models."

Bill Lawton, Staff Engineer at InterDigital Communications Corp. is quoted in the Press Release: "SPW 5 has the potential to put our proven design methodology using 'polymodeling' onto an exciting new foundation," said : "The new user interface and the more powerful scripting have the capability to enable us to further streamline the design cycle and increase our productivity. SPW 5-XP installed smoothly just like any other Windows application," said Masao Watanabe, assistant manager, Digital TV & STB Digital Project, Digital Audio/Visual Systems Division, NEC Electronics. "The new GUI is much more streamlined than previous SPW releases. It is easy to navigate, and even has-thanks to CoWare's strong presence in Japan-built-in Japanese character support."

BAE Systems, Celoxica Ltd., and Medius Inc. announced what the companies are calling a "novel software approach to sensor integration that allows for optimized performance and dramatic cost reduction for cruise control, collision avoidance and other automotive safety systems." The new technology comes in release 2.0 of the companies' sensor-fusion technology demonstrator series, which includes a "self-aligning intelligent sensor that can automatically line up with the frame of reference of the vehicle it is attached to ... a system that minimizes factory alignment issues, avoiding the need for complex, expensive and time consuming manual tasks when the system is first installed. Furthermore, the system stays accurate for its lifetime, since disturbances under normal operating conditions that may misalign the sensor are automatically detected and intelligently corrected."

Also from the Press Release: "Automotive sensor systems are increasing in complexity as functionality becomes more demanding; radar, lidar, ultrasound and video components are typically used to provide the vehicle with a view of what is happening around it. This 'situational awareness' picture needs to be both comprehensive and accurate - take adaptive cruise control (ACC) as an example. Forward looking ranging sensors must look ahead up to 200m in order to anticipate the actions of the vehicles in front. At this range, even very small alignment errors can correlate to errors greater than the width of the lane - enough to cause massive confusion as the device may mis-read street furniture, bridges or oncoming traffic as valid signals. What is needed is a solution that will allow sensors to align and lock-on to the axes of the vehicle, and maintain lock under software control. This powerful feature allows new levels of trust and confidence in safety systems like collision avoidance and pre-crash."

How about that automotive!

Mentor Graphics Corp. announced it has established "business agreements" with Optimum Design Associates (Optimum) and PCB Libraries to make their libraries available for use with Mentor's PADS PCB design flow. The agreements are living under "Mentor's policy of open endorsement," and are intended to provide "production-ready, integrated and fully documented library of symbols, decals (footprints) and a large parts database will allow PADS users to significantly reduce the task of library creation and proceed to design and layout processes as quickly as possible. For current PADS customers using Mentor's DxDesigner, or PADS Layout (formerly PowerPCB) the new partnerships offer economical, production-tested, high-quality resources to quickly expand existing libraries."

Apache Design Solutions announced that Toshiba has adopted Apache's "full-chip dynamic power integrity solution" to their SoC power closure flow. Tamotsu Hiwatashi, Senior Manager of the Planning Department, System LSI Design Department, System LSI Division 1 of Toshiba (breathe), is quoted: "By adding [Apache's] RedHawk in our sign-off flow, we expect to ensure silicon success while reducing production costs through improved yields."

Pulsic Ltd. has announced that Hynix Semiconductors has adopted Pulsic's shape based place & route flow "to reduce the turnaround time for leading-edge designs." S.K.Hong, CIO and Vice President at Hynix is quoted: "We have completed a detailed evaluation of Pulsic’s groundbreaking shape-based tools over the last few months and concluded that we can improve productivity in several key areas by applying this technology as part of our overall design flow."

ARM and Sun Microsystems has announced a long-term collaboration to integrate and "distribute optimized Java solutions for mobile devices." The companies say the "integration of software and hardware optimizations will enhance the end-user mobile experience by significantly boosting computing power behind mobile Java applications." They also say they'll streamline access to the integrated product by establishing one single distribution source through Sun, "thereby improving integration efficiency and reducing time-to-market for handset manufacturers and carriers. The integrated product will be distributed by Sun; commercial deployment of the integrated product will be subject to the separate licensing terms of Sun and ARM respectively."

Mentor Graphics Corp. announced that it has "enabled the industry's most accurate simulation of nanometer technology with the introduction of new resistance and capacitance engines for its full-chip, transistor-level parasitic extraction solution, Calibre xRC. Based on the new resistance engine, Mentor Graphics has also developed hierarchical netlisting and optimized back annotation capabilities between Calibre xRC and Nassda's high-performance simulation platform HSIMplus."

Mentor Graphics also announced that the Calibre product line is now accepting OASIS files and supporting OASIS output in the upcoming 2004.3 production release scheduled for September 2004. It includes the GDS-to-OASIS translator, which was previously made publicly available for validation and verification of the new format. The company says it has provided more than 160 downloads of the GDS-to-OASIS translation utility, which is available free of charge, and is generally used as a reference for OASIS-related development activities in the industry. Mentor adds that now that the tool is production proven, the OASIS translator will be an included feature in the Calibre releases, and available to all Calibre customers.

Stone Pillar Technologies Inc. announced TestPlanManager, which the company describes as the newest addition to its Silicon Insight family of products for developing semiconductor process technologies.

Per the Press Release: "TestPlanManager automates the creation of test routines for device characterization and provides capabilities for test library management. Large technology development test chips require significant engineering effort in the implementation of test plans that are used to characterize dozens, or even hundreds, of devices present on a chip. Manually creating test plans for technology development test chips is a painstaking, error-prone, and labor-intensive task. By automating this process, TestPlanManager improves test plan readability, reduces errors, guarantees consistency between test plan documentation and executable, and reduces engineering effort by as much as 75%."

Applied Wave Research, Inc. announced their Microwave Office 2004 design suite for RF and microwave circuit designs. The company says this new version provides RF and microwave engineers with "significant improvements in power and usability to increase design accuracy and shorten design cycle time."

Technical details per the Press Release: "Traditionally, a large gap exists in the product development process between the electrical and physical design domains. Microwave Office 2004 software fully integrates three-dimensional (3D) planar electromagnetic (EM) simulation with circuit simulation and layout tools, permitting arbitrary physical structures to be embedded within linear and nonlinear circuit simulations."

"AWR has improved the capacity of its industry-leading EMSight EM simulator by over 5X. The simulator uses a full-wave spectral-domain approach based on the method-of-moments (MoM), and is multi-threaded to take advantage of multiprocessor computers. Through the AWR EM Socket interface, more third-party EM solvers are integrated with, and directly accessible from, the AWR unified data model, including: Sonnet Software’s EM product, Zealand Software’s IE3D, MEM Research’s EM3DS, Simulation Technology and Applied Research’s Analyst, and Optimal Corp.’s O-Wave."

It goes without saying that hands across the [corporate] water is always good news.

Wolfson Microelectronics plc announced that the company has purchased software from Verific Design Automation and is using it as part of its internal design environment. Wolfson said they had to because "the increasing digital complexity of Wolfson’s advanced mixed-signal products has motivated a transition of its digital design flow from a partly schematic, partly Verilog hardware description language (HDL), flow to a fully Verilog HDL based flow. Verific’s HDL Component Software provides a ready-made field-proven Verilog parser and analyzer, which Wolfson is incorporating into its proprietary mixed signal design software. This enables control and manipulation of digital HDL modules in a common framework together with the analogue aspects of the circuit designs."

Synopsys, Inc. announced that Atheros Communications, Inc. has adopted Synopsys' NanoSim for the RF front-end circuits verification of Atheros' AR5005G single-chip wireless product. The company says the chip is a multi-million-gate IC that supports the IEEE 802.11b and 802.11g protocols, and that using NanoSim 2004.06, Atheros engineers can now perform RF front-end circuits verification of their complex mixed-signal devices to help ensure first silicon success.

Rick Bahr, Vice President of Engineering at Atheros, is quoted: "With NanoSim, we were able to verify the entire synthesizer behavior of our AR5005G, the world's first single-chip IEEE 802.11g solution. We chose NanoSim as a verification tool because it could handle the size and complexity of our leading-edge, mixed-signal chip."

Also from Synopsys - The company announced that its Proteus optical proximity correction (OPC) software has been adopted by NEC Electronics Corp. for use in NEC's 90-nanometer production.

Here's the scoop on the technical details ala the Press Release: "As process geometries continue to shrink to 90-nm and below, the ability to efficiently optimize the application of OPC plays an increasingly critical role in accelerating time-to-yield. In addition, OPC correction at smaller geometries requires significantly more processing time. Proteus' unique architecture provides near-linear scalability, when using clusters of inexpensive Linux based central processing unit (CPUs) that allows customers to reduce turn-around-time. Several leading-edge semiconductor companies have deployed Proteus to reduce mask synthesis turn-around-time from days to hours."

Per the Press Release: "Specific activities included in the collaboration will be efforts to improve the design flow from layout to mask for alternating aperture phase shift masks (AAPSM), improve the yield and cycle time for masks using strong resolution enhancement techniques (RET), and reduce the turn around time for mask inspection using Synopsys' suite of DFM software tools."

Finally this from Mentor Graphics Corp. - The company announced it has established business agreements with Optimum Design Associates (Optimum) and PCB Libraries to make their libraries available for use with the Mentor Graphics PADS PCB design flow. Per the Press Release: "These agreements, under Mentor's policy of open endorsement, will allow PADS customers to choose from major suppliers of component libraries in order to assure the highest quality and selection of components when creating their electronic products."