** Actel Corp. announced its ProASIC3 and ProASIC3E families, which the company describes as its "third-generation of flash-based programmable logic solutions and the world’s lowest-cost FPGA. With the ProASIC3/E families, Actel addresses strong market demand for full-featured, cost-effective FPGAs for consumer, automotive and other price-sensitive application areas. This "value-based" segment represents the fastest growing component of the FPGA market and is estimated to be $500M this year … Actel’s new single-chip devices deliver 64-bit, 66 MHz PCI performance and are the industry’s first FPGAs with on-chip user flash memory. The devices range in density from 30,000 to 3-million system gates and deliver technology leading integrated secure in-system programmability (ISP). "

The main features of ProASIC3: 30k to 1 million system gates; 18 to 108kbits of true dual-port SRAM; 81 to 288 user I/Os; 3.3V, 64-bit 66MHz PCI, up to 350 MHz external system performance; 1.5V core voltage for low power; 1.5V, 1.8V, 2.5V and 3.3V I/O voltage operation; and bank-selectable I/O voltages – up to 4 banks per chip.

The main features of ProASIC3E: 600k to 3 million system gates; 108 to 504kbits of true dual-port SRAM; up to 616 user I/Os; 3.3V, 64-bit 66 MHz PCI; up to 350 MHz external system performance; 1.5V core voltage for low power; 1.5V, 1.8V, 2.5V and 3.3V I/O voltage operation; and bank-selectable I/O voltages – 8 banks per chip.

John East, President and CEO of Actel, is quoted: "Over the past 10 years, flash technology has evolved into a disruptive technology, dramatically impacting every application it has touched," said "For example, flash technology has transformed cell phones, cameras and video recorders into revolutionary variants of their predecessors. Flash is now poised to do the same for the programmable logic market. Indeed, the paradigm for mainstream FPGA technology platforms has changed forever, and Actel is in a position of leadership."

** In related news, Actel Corp. announced the availability of 90 IP cores to support its new ProASIC3 and ProASIC3E device families, which the company says demonstrates its commitment to the deployment of its new FPGAs. The ported cores leverage take advantage of the features of the ProASIC3/E devices, including 66 MHz 64-bit PCI performance, on-chip user flash memory, enhanced I/O and memory, and secure in-system programmability (ISP).

** Actel also announced a low-cost device programmer and starter kit to support its flash-based ProASIC3 and ProASIC3E FPGA. The company says its new ProASIC3 Starter Kit allows designers to examine, design and program the nonvolatile ProASIC3/E devices.

** Finally, Actel announced that its Libero 6.1 Integrated Design Environment (IDE) provides complete support for the company’s ProASIC3 and ProASIC3E devices.

** Aldec, Inc. announced the release of Active-HDL 6.3, Altera Edition with direct support and automation for Altera’s Quartus II design software version 4.2, Stratix II FPGAs and HardCopy II structured ASICs. Aldec says it has developed "a Tcl-based script that automates the design flow interface between Active-HDL and the Quartus II software. This automated solution from Aldec and Altera provides the engineer with a closed design environment while delivering complete access to compile and simulate FPGA and HardCopy structured ASIC devices from a single design environment."

Chris Erwin, Product Marketing Manager for Aldec, is quoted in the Press Release: "Active-HDL’s Altera Edition with Quartus II software support provides the designer with full access to unlimited simulation and debugging capabilities for FPGA and structured ASIC designs in an easy-to-use environment. The automated Design Flow Manager, along with precompiled Altera libraries and access to several popular synthesis tools, completes the solution."

** Altium Ltd. announced the release of Service Pack 1 for P-CAD 2004, which is Altium's PCB design system for layout professionals that was released several months ago. The company describes the current release, SP1, as a "minor update initiated in response to feedback from customers via Altium's P-CAD Forum."

** AMD, Analog Devices, Freescale, and IBM announced that they are the first companies to publish certified scores for processors tested against the new DENbench suite, EEMBC’s new Digital Entertainment benchmarks. The first processors to be evaluated under the new benchmarks are the AMD Geode NX1500, the Analog Devices ADSP-BF533, the Freescale MPC7447A, and the IBM 750GX.

EEMBC says the DENbench suite has 65+ benchmark tests that allow developers of set-top boxes, PDAs, mobile phones, and in-car entertainment systems to evaluate the performance of embedded processors in their systems. Specific algorithms in the suite test the speed at which processors compress and decompress audio, video, and still images. Other benchmarks in the suite focus on encryption and decryption algorithms commonly used in eCommerce applications.

** Applied Wave Research, Inc. (AWR) and Auriga Measurement Systems, LLC announced an OEM agreement that the companies say will provide "designers and modeling engineers with a powerful new modeling and extraction solution. Under the terms of the agreement, Auriga will embed AWR’s Microwave Office design software into the company’s soon-to-be-released measurement and model extraction test system."

Yusuke Tajima, Director of Modeling and Design at Auriga, is quoted in the Press Release: "Demands on modeling are becoming tougher as system requirements increase in sophistication every year. Designers are dealing with more complex signal environments and new types of devices all the time. The device modeling capability in the industry is falling behind these demands, and Auriga is going to provide a solution. Customers will benefit from this solution in terms of both faster model development and more accurate model implementation."

** Blue Pearl Software, Inc. announced its first product, the Indigo RTL Analysis tool designed for "rapid functional closure." The company says it will be releasing its timing closure product later in 2005.

Per the Press Release: "Indigo accelerates designs through the synthesis flow by identifying functional issues in RTL designs prior to synthesis. It reduces the number of design iterations required by resolving issues such as synchronization of data crossing clock domains and logic races. Indigo's powerful new high-level functional analysis technology runs at the full chip level, without synthesizing to gates, allowing rapid analysis of multi-million gate designs. Indigo analyzes multiple clock domain designs to ensure that data crossing domain boundaries is synchronized. Indigo recognizes double register, memory and custom synchronization schemes and highlights data that re-converges from independent synchronizers. Indigo quickly identifies race conditions, such as write-write, read-write, and combinational loop races, and automatically pinpoints the lines of source code that cause them. "

Steve Presant, Vice President of Hardware Engineering for C2 Microsystems, was quoted: "We were able to download Indigo and use it on designs in less than an hour," said "Indigo has allowed us to create a low-risk and predictable development cycle that helps generate accurate RTL code, reducing time-consuming iterations."

** Cadence Design Systems, Inc. announced that Sanyo Electric Co., Ltd. has achieved an "important production tapeout" using Cadence's Encounter digital IC design platform. The companies say that the Encounter RTL Compiler portion of the platform helped to "decrease power consumption of an important block of Sanyo's chip by 10 percent, while maintaining critical performance requirements. RTL Compiler shrunk the chip's area significantly over the size achieved by competitive solutions. Hideki Yamauchi, Materials and Devices Development Center BU at Sanyo, is quoted in the Press Release: "We chose Encounter RTL Compiler to tape out this important new chip because it provided us with better area and power that couldn't be attained using our previous synthesis solution. Besides the improvements we realized in speed, area and power, we appreciated the ease with which we were able to integrate Encounter RTL Compiler into our existing production environment."

** Cadence also announced that the company has helped Fujitsu to achieve "first-pass silicon" on 66 consecutive designs. The companies say these designs were done using a standardized reference design flow based on Cadence's Encounter IC implementation technology. The companies also says this reference flow has been utilized at Fujitsu's design centers worldwide, and by their COT partners. The designs were at 90 and 130 nanometers.

Kazuyuki Kawauchi, Executive Vice President of Fujitsu Microelectronics America Inc., is quoted in the Press Release: "We are extremely pleased that our global collaboration with Cadence has produced such tremendous success so quickly. We are working with Cadence in other areas, and I'm confident that we will see many further tangible achievements coming up over the next few years."

** Cadence also announced new capabilities that the company says will enable wireless chip designers and manufacturers to have better insight into the mixed-signal and RF challenges that surround wireless design.

The Press Release says the product offering combines: "new Cadence RF extraction technology, two new design flows tailored for wireless chip design, Engineering Services, silicon-proven IP, and integration with technology from industry-leading Cadence partners Agilent, CoWare, Helic, and Mathworks. The RF IC flow [features] Assura RF, the new Cadence technology that delivers complete extraction for RF design. The two new design flows that are included [are] based on 802.11b wireless LAN design IP. These flows enable simultaneous verification of the RF, analog and digital domains together and verification of the wireless IC design in the context of the system. The flows integrate technology from Cadence partners to help streamline wireless design."

I had a chance to speak by phone with Kelly Perey, Vice President of Marketing at Cadence, about the announcement, and the various companies mentioned in the release.

She told me: "Traditionally, the orientation in EDA has been around – 'I've got this great software product that does these specific things' – and less around – 'Here are the customers' problems and how to solve them.' [Today], we want to go after a market-oriented approach more than a customer-oriented approach. So, in this announcement we've taken the wireless LAN and used it as a reference flow."

"[We have observed] that one reason that Agilent, for instance, has ESOF is because the company absolutely understands that there's an overall problem that their customers are trying to solve – the problem of how to link EDA and test. ESOF [is a result] of Agilent looking at their customers' problems. [As for Mathworks], if we're going to look at a widely used flow, of course it's MatLab. As such, they've got an incredible solution there, and we felt we had to have MatLab as an option that we're tied into. [Of course], we already have a relationship with CoWare, who along with Agilent, provide application-specific libraries. And Hellic is a strong design house with a spiral inductor model that fits within our flow."

"All together, this [set of companies in conjunction with Cadence] offers a set of complete customer solutions. This partnership is about deliverables. We've really oriented [our efforts] towards what design people do, and what we need to do to [assist them in that]. This is about our two new design flows for wireless design, and the other key pieces of technology that for the first time are all packaged together. It's a best leap forward in solutions from an EDA company that has both the analog and the RF perspective in mind."

"[And importantly], there will now be a Virtuoso website where you'll be able to find design solutions, not design products. We're calling is a user resource center, and we believe it will be a better way to get at the tools and technologies that the designers need today."

** In related news, CoWare Inc. announced its SPW DSP application design tool has been integrated with the newly announced Cadence Virtuoso custom design platform capabilities (see below) for RF designers.

Kelly Perey is quoted in the Press Release: "Teamed with CoWare to leverage their SPW tool and SystemC expertise, we can overcome a large hurdle in wireless design," said "The gap between system specification and IC implementation often leads to design failure. Our partnership provides advanced capabilities to bridge this gap for wireless product teams."

** Celoxica announced that through the Synopsys in-Sync program, the company has formalized the interoperability between Celoxica’s Agility Compiler and DK Design Suite with the Design Compiler synthesis solution from Synopsys.

** CriticalBlue says it has completed a benchmark project "validating" its Cascade tool with respect to Synopsys RTL implementation flow. The Press Release goes on to say: "Working with a leading semiconductor company who defined the embedded software benchmark example and its target gate count and performance constraints, Cascade determined the available solution space and to generate synthesizable RTL for suitable co-processor architecture. No modifications were made to the original embedded software. Synopsys’ Design Compiler synthesis solution and the VCS complete RTL verification solution, provided to CriticalBlue through a Synopsys marketing program, were used to synthesize and validate the output from Cascade for delivery of the predicted gate count and performance figures for 0.13-micron technology."

** IBM and Chartered Semiconductor Manufacturing announced they are expanding their joint development efforts to 45-nanometer bulk CMOS process technology. The companies says that upon completion of the development, they will have created "a common process platform spanning three major generations of advanced process technology. The 45-nanometer alliance builds on the multi-year agreement that the two companies signed in November 2002 to jointly develop and align on 90-nanometer and 65-nanometer logic processes for process-exact foundry chip production on 300mm silicon wafers. It extends the development relationship through June 2008. Financial details of the agreement were not disclosed."

** IMEC announced that Samsung Electronics Co. LTD. has become the first long-term strategic partner within IMEC's M4 (Multi-Mode Multi-Media) research program, which IMEC says focuses on the mobile terminal for the future ubiquitous network era.

Under this agreement, Samsung and IMEC say they will "develop key technologies for its future portable communication products. Future generation mobile terminals will start to incorporate ubiquitous network functionality, by efficiently dealing with a multitude of communication modes and various multimedia applications. Further down the road, these terminals will also need adaptive behavior to intelligently manage the computational resources that will be distributed and shared across the environing systems. IMEC's M4 integrated research platform aims to resolve the fundamental technological issues for future mobile terminals, allowing the true ubiquitous network environment to become a reality. Complexity, cost, power consumption, high throughput at low latency, and flexibility are the five primary hurdles in developing a mobile terminal. To overcome these hurdles, IMEC and Samsung have outlined a number of domains of innovation, which are targeted by the M4 technology programs."

The Press Release adds: "In addition to Samsung's strategic partnership with IMEC, IMEC also has a running relationship with several technology partners including Freescale, Infineon and Xilinx, collaborating within one of the M4 technology programs."

** MatrixOne announced the MatrixOne Materials Compliance Central business process application, which the company says is designed to "enable companies to adhere to and keep pace with new environmental compliance regulations throughout the product development process."

The Press Release goes on to address the troubling impact of high-tech gadgetry on the environment: "Companies, particularly those in the automotive and electronics markets, are faced with an onslaught of new regulatory pressures, most notably those presented by Waste Electrical and Electronic Equipment (WEEE), Restriction of Hazardous Substances (RoHS) and End-of-Life Vehicle (ELV) regulations."

"These regulations – which will be in effect starting with the WEEE directive in Europe in August of 2005 and RoHS starting in July 2006 – are aimed at reducing the amount of hazardous materials in new products and ensuring that the materials are recyclable at the end of their product lifecycle. Under these new regulations, manufacturers must implement processes to collect, organize, analyze and report detailed materials and substance data related to all new products. To simplify and improve these processes, MatrixOne Materials Compliance Central allows users to analyze Bill of Material (BOM), or product content information from any source and cross-reference the data against multiple substance lists and regulation requirements easily and accurately during product development. In this way, product teams can quickly determine whether a product's components meet compliance standards and certain design thresholds from the start of the project."

** Mentor Graphics Corp. announced that "its suite of advanced synthesis products supports Altera Corp.'s newly introduced HardCopy II structured ASIC family. Users of the Precision RTL Synthesis and LeonardoSpectrum tools from Mentor Graphics can now enjoy quick and direct access to the unique cost, power and performance benefits of the HardCopy II structured ASIC device family."

Alain Bismuth, Vice President of the HardCopy Product Group at Altera, is quoted: "We have worked very closely with Mentor Graphics over the past year to establish a seamless flow for our HardCopy devices, so it was a clear-cut extension for us to develop a robust and automatic HardCopy II flow. We feel that the combination of Altera's structured ASIC devices and Mentor Graphics synthesis products will enable our mutual customers to consistently and predictably maximize their competitive advantage with minimal effort on their part."

Simon Bloch, General Manager of the Design Creation and Synthesis Division at Mentor Graphics, is also quoted: "The introduction of HardCopy II structured ASICs further empowers those customers designing high-volume Stratix II devices using our Precision Synthesis and LeonardoSpectrum products to cost competitively meet development goals, with none of the usual risks associated with migrating to a structured ASIC. This is a powerful combination, which truly delivers on the promise of structured ASICs."

** Mentor Graphics also announced that "its suite of advanced synthesis products has added support for Actel Corp. newly introduced ProASIC3 and ProASIC3E FPGAs. Users of the Precision RTL Synthesis tool from Mentor Graphics can now immediately request software updates to design the full range of new devices … Actel and Mentor Graphics are working together to ensure robust support for all of Actel's FPGAs. Initial support for ProASIC3/E in the Precision Synthesis tool suite has been available for selected customers since October 2004. "

Dennis Kish, Vice President of Marketing at Actel, is quoted: "Advanced synthesis support from Mentor Graphics for our new ProASIC3/E families is important to us. Our new devices deliver advanced features such as 64-bit, 66-MHz PCI performance and on-chip user flash memory. We have closely collaborated in testing efforts for both Precision Synthesis and Leonardo Spectrum, and believe that Mentor Graphics solutions will help enable customers to realize the benefits of ProASIC3/E."

** QuickLogic Corp. announced a partnership with Renesas Technology Corp. to develop an 802.11b/g IP phone reference platform, which the companies say will target the Wi-Fi market. The reference platform is designed around Renesas’ SH7720 32-bit RISC processor and QuickLogic’s low-power programmable PCI bridge solution.

Per the Press Release: "The reference platforms integrate all the essential elements for a VoWLAN phone, from the keypad and display to the voice codecs and Wi-Fi module. Designed for fast development and software integration, the reference platform provides all the hardware required to build and deploy a Wi-Fi enabled phone. Platform features include low power consumption, system-level integration and exceptional performance to rapidly enable differentiated next-generation VoWLAN phones. The platform runs on a Linux operating system and can operate using 802.11b or 802.11b/g chip sets."

** ReShape, Inc. announced it has shipped its enhanced PD Builder, which the company says supports SoC Encounter Global Physical Synthesis (GPS) from Cadence Design Systems. ReShape says that it worked in collaboration with various Cadence software users to "utilize the PD Builder Open Flow feature to embody expert tool user practices in its programmable reference design flow."

Per the Press Release: "PD Builder is essentially a flow compiler that in conjunction with commercial physical design tools can build the most complex SoCs in less than 24 hours. PD Builder enables 10X+ runtime reduction on physical design compilation times. Now design teams can explore more design options, quickly verify them to layout quality, and produce SoCs with much greater design margin over conventional methods. Designers use PD Builder in conjunction with their existing physical design tools from Cadence, Mentor Graphics, and Synopsys to perform placement, routing, and sign-off verification functions for their challenging SoC designs.

** Synplicity Inc. announced "major enhancements" to its FPGA synthesis software, designed to provide users with "significant productivity gains through close integration with formal verification, place & route, and debugging products while also improving upon the company’s unmatched quality of results (QoR) for FPGAs in terms of area and timing performance."

Enhancements include: integrated formal verification flow support for Cadence’s Conformal and Prover Technology’s eCheck equivalence checker software; tighter integration with P&R tools from Actel, Altera and Xilinx, and Synplicity’s Identify source code debugging product for FPGAs is now integrated into the Synplify Pro product. Also, this version of Synplify Pro software includes support for Actel’s newly announced ProASIC3 FPGAs, as well as Altera’s HardCopy II family of structured ASICs.

Jeff Garrison, Director of Marketing for FPGA products at Synplicity, is quoted: "Synplicity has set the standard in FPGA synthesis for many years and with today’s introduction of our newest Synplify Pro software we have taken big steps in improving the productivity of our users, which directly impacts their ability to get their designs to market quickly. In addition to the many time saving features, we’re seeing significant improvements in timing performance and area reduction, which often enables designers to move to a less expensive device."

** Synplicity also announced, in conjunction with Prover Technology Inc., an integrated verification flow for Synplicity’s Synplify Pro FPGA synthesis product. The companies say this integrated flow combines the Prover eCheck equivalence checker and the Synplify Pro 8.0 software, so that users of the Synplify Pro can use Prover’s formal verification product in their verification flow. The companies also say that the flow was developed "to meet the growing demand for efficient formal verification for mission-critical FPGA applications and ASIC prototyping. The combined flow automates equivalence checking of Altera and Xilinx FPGA designs, dramatically reducing the need for manual configuration. As a result, FPGA designers can now leverage a thorough equivalence checking methodology previously only available to ASIC designers."

** Synopsys, Inc. announced that Toshiba Corp. got a 40-percent power reduction on its latest 90-nanometer Media embedded Processor (MeP) SoC design by using the Synopsys Galaxy Design Platform.

Takashi Yoshimori, Technology Executive SoC Design at Toshiba Corp. Semiconductor Company, is quoted in the Press Release: "Toshiba developed a module-wise dynamic-voltage and frequency scaling architecture for its MeP SoC that targets low power applications. We implemented this architecture using the Galaxy platform's multi-voltage flow on our SoCs for mobile application design and achieved a 40 percent power savings for the module in which the technology is applied. We are now in the process of testing this Galaxy-based flow as a standard part of our low power design methodology."

** Tensilica, Inc. announced the V6 suite of automation tools, which the company says "significantly speed the design of major blocks in SoC design, making it easier and faster to design SoCs with configurable processors than with custom logic. Using the V6 development tools, a design team with an existing algorithm coded in C or C++ could develop a customized Xtensa LX processor in a day, whereas a typical RTL design cycle usually requires six to nine months"

"The new V6 suite includes a fully pipeline-accurate instruction set simulator (ISS), which provides the clock-cycle accuracy of RTL hardware simulation while running two or three orders of magnitude faster. The V6 suite also includes a new version of the Xtensa C/C++ Compiler (XCC), which optimizes programs written in C or C++ for either code density or execution performance on an Xtensa LX processor … The V6 suite also includes the XPRES Compiler, the first and only tool that analyzes standard C/C++ code to automatically create optimized instruction-set architectures (ISAs) for Xtensa configurable processors. By using the XPRES Compiler, SOC designers avoid having to hand-code algorithms in complex languages such as Verilog or VHDL. Designers also avoid the lengthy verification cycles required when hand-coding hardware designs."

** Tharas Systems, Inc. announced its support for Verilog 4-state logic simulation in Hammer 100. The company says that Hammer 100 can now "detect and propagate 4-valued logic – "0", "1", "X" and "Z" similar to a Verilog software simulator. This significantly shrinks the "Time-to-Performance" while enhancing overall verification accuracy."

Per the Press Release: "Traditionally engineers have utilized the 4-state capability of the Verilog simulation language to pessimistically model design elements. This capability helps uncover issues associated with reset logic, random initialization, bus conflicts, un-initialized registers and ATPG-based verification. In the past, since hardware-assisted verification tools only supported 2-state logic ("0" and "1"), engineers had to simplify 4-state dependent models to match software simulation results especially in the test bench. This can be a laborious process and can result in a potential loss of accuracy in certain situations. Hammer 100 now uniquely offers functionality similar to a software simulator. The 4-valued accelerated simulation capability is backward compatible with Hammer 100 hardware."