The Press Releases are running fairly verbatim this week. Read them. There's lots of good stuff in there!

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Calypto Design Systems, Inc. has introduced its SLEC product family, described as "the semiconductor industry’s only sequential logic equivalence checking solution. The SLEC family delivers dramatic improvement in IC functional verification, offering design teams increased productivity, confidence and flexibility in making changes to meet their IC power and performance goals … The SLEC product family is the first commercially available platform that proves functional equivalence between two IC designs that contain differences in levels of abstraction and sequential behavior. SLEC can verify designs with sequential differences such as micro-architectural changes, state machine modifications, timing re-balancing, and interface differences. The SLEC sequential equivalence checking software is based on a patent-pending hybrid verification technology that, unlike traditional combinational equivalence checkers, can support designs with sequential differences. The SLEC product family initially includes two products: SLEC SYSTEM and SLEC RTL. SLEC SYSTEM is used by design teams to check that RTL implementations match a system-level design, while SLEC RTL checks functional equivalence between two versions of an RTL design that have dramatically different architectures and timing."

The Press Release continues: "Moving to high level design is a process of navigating the System-to-RTL continuum. A continuum approach is required for design teams to work at multiple levels of sequential and data abstraction – from fully timed RTL implementation to transaction-level modeling. SLEC allows designers to navigate the System-to-RTL continuum by verifying functional equivalence across levels of sequential and data abstraction. Design teams who adopted system-level design methodologies can use the SLEC products to leverage their investment in system-level validation to verify and refine RTL implementations. SLEC enables designers to quickly verify RTL refinements without having to spend time running a full regression suite. Likewise, RTL designers can leverage previously validated designs to confidently make sequential changes such as pipelining and resource sharing that would have previously taken weeks of simulation time to verify. In both cases, the SLEC platform delivers a comprehensive sequential verification solution that identifies bugs that are difficult to find or missed when using traditional simulation methods. With SLEC, design teams quickly detect side effects that have been introduced during block-level optimization. This gives engineers more freedom in the design options they have, dramatically improving design efficiency."

In support of Calypto's technology, Osamu Tada, Department Manager of System Level Design and Verification Technology Dept., LSI Product Technology Unit at Renesas Technology Corp., is on record as saying: "SLEC’s ability to verify sequential differences is a strong addition to our advanced verification methodology. It offers us an innovative approach for functional verification as we refine our design at various levels of abstraction. We consider SLEC an important tool in our high-level design flow."

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Synfora, Inc. has introduced the ASPEN Architecture, which the company says is "a configurable embedded processor designed to drive application engines that implement key functionality in SoCs.

Application engine synthesis is ideal for the complex algorithms typically found in multimedia (H.264, WMV), imaging (photo-quality printing), wireless (3GPP), and security (AES) applications. PICO-powered AES will leverage the ASPEN processors, integrated with networks of hardware accelerators, to cut the cost and time required for SoC design by fifty percent or more. It will also enable engineers to create much more effective silicon."

"The initial release of the ASPEN architecture will support a wide range of capabilities, allowing it to be used in many different applications with different power, price, and performance points. ASPEN will support single or dual issue, and perform up to 250 MHz in 130-nanometer process technology. This will produce performance of more than 400 MIPS in a processor of 50,000 to 100,000 gates, depending on the instruction set selected."

Synfora CEO Simon Napper is quoted in the Press Release: "The ASPEN architecture represents a major milestone in Synfora’s development of application engine synthesis for SoC and system-level design. We are now focused on delivering an H.264 encoder – based on ASPEN – in a fraction of the time and resources used in manual design. When DAC attendees see ASPEN integrating with the Synfora PICO Express accelerators, it will be an quite an eye opener!"

Also per the Press Release: " ASPEN will be a major component of Synfora’s second application engine synthesis (AES) product, which is planned for release later this year … ASPEN’s features come from general-purpose VLIW/EPIC architectures such as predication, rotating register, modulo-scheduling support, and multi-clustering. ASPEN includes special embedded features such as programmable interrupts, raw register files, streaming data, saturating arithmetic, and multi-precision arithmetic. In addition, the instruction set is customizable to the application in terms of functionality and performance. ASPEN has been designed to integrate tightly with a Synfora PICO Express-generated network of hardware accelerators."

Speaking of PICO, Synfora has also announced the 5.01 release of PICO Express for AES (see above). The company says the new release features "enhanced capabilities for solving implementation challenges inherent in state-of-the-art algorithms found in multimedia (H.264, WMV), imaging (photo-quality printing), wireless (3GPP), and security (AES) applications. PICO Express empowers electronic system-level (ESL) design methodologies by creating flow-controlled networks of hardware accelerators from sequential C algorithms. This addresses the critical issue of complexity levels typical of algorithms such as H.264."

The Press Release continues: " PICO Express 5.01 expands the networks of hardware accelerators that can be synthesized from C algorithms. It also broadens the scope of algorithms that can be efficiently synthesized by blending highly pipelined and sequential stages that are typically found in advanced algorithms such as H.264, WMV, and 3GPP. As a result, designers can now create more sophisticated networks of hardware accelerators."

"PICO Express 5.01 automatically analyzes sequential code blocks to determine if they should run sequentially or in parallel. For performance targets that require further parallelism, multiple buffers will be inserted automatically for shared arrays to allow multiple tasks to run in parallel. In addition, PICO Express 5.01 supports data paths greater than 32-bits by supporting co-scheduling of multiple streams of data."

Synfora CEO Simon Napper, is quoted: "Many companies are working to implement complex algorithms in silicon, for example, H.264 encoders, and they are challenged by unprecedented design complexity. It’s not enough to move to a higher-level language; they need to move to a higher-level capability. The unique ability of PICO Express to take complex C algorithms and automatically create an efficient, flow-controlled, network of hardware accelerators is crucial for managing this implementation complexity. PICO Express 5.01 is the only tool that can produce designs with that complexity."

Thierry Bauchon, Director of R&D for the Home Entertainment Group of STMicroelectronics, is also quoted: "We have used PICO Express on two occasions to produce RTL code used in recent design tape-outs. The first time, Synfora ran the tool and provided RTL to us. The results were competitive and the RTL was delivered much faster than the time forecast for a design by hand. More than one year later, our requirements changed, and we were able to pick up the original C algorithm and make the required changes in less than a day. PICO Express helped us to meet our tapeout deadlines with silicon optimized for our highly competitive markets."

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** Accent and Kilopass Technology Inc. announced that Accent has implemented Kilopass’ embedded non-volatile memory (NVM) (IP in a SoC that the companies say "will provide the key technology element in the electronic infrastructure for an intelligent building application."

This is important, per the Press Release, because: "Kilopass’ XPM memory technology has security characteristics that make it <B><I>effectively impossible to reverse-engineer</B></I>. Because the memory block is embedded, information is internally secured to the SoC’s design. There is no floating charge as with Flash technology, so low-cost passive reverse-engineering methods are not possible. In addition, an XPM memory cell has no visible indicators that would reveal its state, if the chip were to be de-layered."

Massimo Vanzi, Accent’s General Manager, is pleased: "We chose Kilopass’ XPM non-volatile memory technology for the intelligent building SoC project not only because it met our customer’s security requirements but because it could also be embedded easily into an SoC using standard CMOS process technology. It also meant that the technology could be cost-effectively manufactured by many leading CMOS foundries around the world."

Please note: "The companies have also announced that Kilopass has become an IP partner in Accent’s Highway to Silicon program. Highway to Silicon was conceived to offer customers a seamless path for access to and integration of the most advanced silicon technologies into a single chip as well as simplify the management of the semiconductor supply chain, even for low volume production."

** Bluespec Inc. announced it has added co-simulation capabilities to its model simulation technology that the company says "will allow hardware chip designers to utilize Bluespec’s cycle-accurate C models in SystemC or Verilog modeling environments. This provides design engineers with the flexibility to leverage accelerated models in the most appropriate and preferred environment for a given stage in design … The co-simulation capabilities enable a heterogeneous design component environment to be easily simulated. With growing use of IP, it is essential that designers mix high-level design with existing IP blocks, at any level of abstraction. Bluespec will automatically generate all of the shims required for these models to co-simulate … Bluespec’s EDA toolset generates Verilog RTL and cycle-accurate C from a high-level design. The cycle-accurate C models can be integrated into a Verilog SoC design, back-annotated into a SystemC model or testbench or become part of a mixed SystemC/Bluespec model."

** Cadence Design Systems, Inc. announced that the PEX Endpoint Controller IP, which the company says is integrated with the Rambus PCI Express PHY IP, and has passed PCI-SIG compliance testing, and has been added to the PCI-SIG Integrators List.

Interestingly, per the Press Release: "Cadence has taken a vertical approach to meeting the needs of PCI Express customers, combining technologies from industry leaders to enable customers to reduce risk and increase productivity. In addition to design and verification IP, the vertical approach combines emulation, board design and protocol analysis tools targeted at the PCI Express architecture. In preparing for the Compliance Workshop, where devices need to pass compliance and interoperability testing, verification IP from Denali and PCI Express analyzers from Catalyst helped Cadence develop a higher-quality product."

Chuck Trefts of Catalyst, described as "a veteran of many PCI-SIG Compliance Workshops", is waxes poetic in the Press Release: "The performance of the Cadence/Rambus test board against our PCI Express compliance test suite was excellent, among the best PCI Express solutions I have seen."

** Cambridge Consultants announced a new development tools for its 32-bit RISC processor core for ASIC and FPGA applications, XAP3. The company says the tools "include the widely-used GCC (Gnu Compiler Collection) C/C++ compiler, and the uCLinux and Micrium µC/OS-II real-time operating systems, and will provide exceptionally powerful and flexible support for embedded system applications. The new software is in addition to Cambridge Consultants' own ANSI C compiler for XAP3."

** eASIC Corp. announced that STMicroelectronics achieved "24 hours turnaround from RTL to tape-out using eASIC’s structured eASIC technology. ST has licensed eASIC’s 0.13- micron eASICore for the rapid customization of a printer platform, which allows ST to offer fast and easy customization of a printer system controller, as well as image processing personalization, in a standard pre-verified printer-engine architecture. ST’s engineering team was able to ship the final GDS-II files to the silicon fab for eBeam customization in less than a day from the time RTL was received."

Given this news, it's not surprising that Vittorio Peduto, General Manager of Computer Systems Division at STMicroelectronics, was overheard saying: "In an ongoing effort to meet our customer’s escalating needs, STMicroelectronics has developed programmable platforms and ASSPs that provide the required flexibility for new applications and configurability for printer products. Our goal is to obtain state-of-the-art design capabilities that make it easier for us to deliver leading edge IC's, therefore we engaged with eASIC for its breakthrough configurable logic technology. We benefited [from the] 24 -hour design turn around time from RTL to tape out. With eASIC’s technology we can make very efficient use of our Direct-write eBeam equipment and eliminate the high cost of mask for customization."

** Incentia Design Systems, Inc. announced that Faraday Technology Corp. is using Incentia's TimeCraft timing analyzer in its standard Design Kit.

Jim Wang, Director of Design Development at Faraday, is quoted in the Press Release: "Our goal is to achieve first-cut design success, which would ultimately shorten the time-to-market. Incentia's timing software performance and capacity has proven itself capable of meeting our objectives, and worthy to be included in our Design Kits."

** PolarFab has released two new digital standard cell libraries for its modular 8" (200 mm) Polar35 5 V BiCMOS process.

Per the Press Release: "The first library supports synthesis place and route circuit design capability that requires a 'gridded' standard cell library. The 104-cell library includes logic (Verilog) and synthesis views that allow customers to use proven SP&R flows to reduce the design time of logic circuits. The synthesis views are compatible with industry leading EDA tools such as Synopsys and Cadence. The SP&R library features in-place-optimization, so many of the basic logic functions have four drive strengths (d1-d4) with the same footprint."

The Press Release goes on: "The second library is intended for lower gate count mixed-signal designs, where the logic is specified using schematics. The 30-cell, standard cell library gives designers a more area-efficient alternative to the SP&R library that allows them to create lower gate count circuits using proven silicon building blocks, saving time and increasing first pass yield. Both libraries have functional VerilogA cell views that allow designers to perform logic simulations many times faster than SPICE transistor level simulations, making it easier to incorporate more digital circuitry in a mixed-signal design."

** SMSC introduced its USB3500 UTMI+ stand-alone, host or On The Go (OTG) transceiver that passed Hi-Speed USB compliance testing with the USB Implementers Forum (USB-IF).

Per the Press Release: "With this announcement, SMSC offers the industry’s broadest family of Hi-Speed USB stand-alone physical layer transceivers (PHYs) covering the range of SIE/PHY interface standards. The USB3500 provides a flexible, stand-alone, Hi-Speed PHY solution that supports the highest level of UTMI+ support (Level 3). Interoperability has been proven through extensive testing with the industry’s leading Hi-Speed OTG IP providers. Many consumer electronics designers are now turning to FPGA solutions because of the lower risk and quicker path to early production. With its flexible UTMI+ digital interface, the USB3500 is a perfect companion to an FPGA solution. Designers can now choose between the USB3500 with its more traditional UTMI+ interface and the USB3300 with its lower pin count ULPI interface. In addition, the USB3500 was recently selected by the USB-IF to be the reference PHY in the new Hi-Speed OTG compliance test platform, introduced at the USB-IF Compliance Workshop in Tokyo, Japan."

** Synopsys, Inc. and Global UniChip announced that GUC has chosen Synopsys' DesignWare IP for use in GUC's SoC designs. The companies say the multi-year agreement "gives GUC access to the wide portfolio of industry-leading DesignWare connectivity IP for standards such as PCI Express and USB protocols, as well as Synopsys' DesignWare Library building block and verification IP.

Jim Lai, COO and President at Global UniChip, is quoted: " As a leading design foundry, Global UniChip only trusts IP that has been tested and implemented on a wide range of complex SoC designs. Synopsys' reputation and history of deep-submicron design success ensures us that their IP is a sound investment that will fit seamlessly into our design flow."

** Synopsys also announced that CreVinn Teoranta has adopted Synopsys' VCS RTL verification tool for use in its chip verification methodology. CreVinn says it is "taking advantage of the built-in verification features of the VCS solution, including Native Testbench (NTB) technology, to speed the IC verification process."

Vincent Gavin, Co-founder and CTO at CreVinn, is quoted: "VCS NTB's advanced language features enable us to cut testbench development time in half compared with our previous C++ techniques. VCS NTB lets us work at a higher level of abstraction and provides higher performance, allowing more advanced system-level testing than was previously possible. This productivity improvement is a competitive advantage in our contract work as well as in our in-house product development because it allows us to complete more verification cycles within a fixed schedule."

** Synopsys announced as well, that Top Layer Networks used Synopsys' Vera testbench automation tool "to verify the chip at the heart of the Attack Mitigator IPS 5500 family of intrusion prevention solutions (IPS).

Jay Brown, Verification Manager at Top Layer, is quoted: "There was no doubt that Synopsys' Vera testbench automation solution was the right choice for our verification environment. Our customers rely on our products to safeguard their networks from zero-day exploits, denial-of-service (DoS) attacks, worms, spyware, email viruses and other threats. The thorough verification provided by the Vera tool and the RVM allowed us to design an industry-leading product that helps prevent malicious content from slipping through the cracks."

** Tensilica, Inc. announced that sci-worx will be designing several SoC IP blocks, including H.264, WMV-9 and MPEG-2 for High-Definition TV, with multiple Tensilica Xtensa LX configurable processors.

Per the Press Release: "In addition to designing with Tensilica’s Xtensa configurable processors, sci-worx will become Tensilica’s first value added reseller (VAR), distributing Tensilica processors as part of larger sci-worx IP subsystems. sci-worx customers will be able to sign one license agreement with sci-worx that includes the necessary provisions for licensing the Xtensa processors inside sci-worx designed IP blocks."

Young-Hun Kluge, Vice President of Sales and Marketing at sci-worx, is quoted: "The market requirement for multi-standard video codecs for SD and HD resolutions requires more flexible solutions to address the high volume consumer market. We’ll be able to get new IP out substantially faster and provide greater flexibility to our customers by using Xtensa processors instead of traditional RTL design methods."

** United Monolithic Semiconductors announced the release of their new pHemt and HBT Process Design Kits for Agilent's Advanced Design System (ADS) Release 2004A.

Per the Press Release: "These design kits support the design and production of high performance Gallium Arsenide MMICs. Agilent’s Advanced Design System offers simulation and layout capabilities for complete front-to-back MMIC design in an integrated flow. Foundry design kits allow MMIC designers across the globe to utilize ADS seamlessly for creating custom circuits using our large range of processes (pHemt, HBT, Mesfet, Schottky diode). This latest ADS version offers a number of new features, including Linux compatibility, a new Layout Connectivity feature for layout verification, faster harmonic balance and planar EM simulation, real-time tuning, and integrated, equation-based devices."

** Verific Design Automation and Altium Ltd. announced that Altium is using Verific Design Automation’s HDL Component Software in Altium's Nexar product. The companies says, "Verific’s HDL Component Software includes C++ source code-based parsers, analyzers and elaborators for Verilog and VHDL that are tightly integrated with Nexar."

Nick Martin, Altium’s founder and joint CEO, has the final word: "We felt that it was crucial to provide strong support for Verilog within Nexar. Rather than developing our own parsers and analyzers, we found that Verific’s well-engineered and reliable HDL Component Software was the right fit for our needs. We can focus on other aspects of Nexar, and strengthen its position as the universal design system of choice for FPGA-based systems development."