Agilent Technologies Inc. announced that Innovative Wireless Technologies (IWT) has selected Agilent’s Advanced Design System (ADS) software and ultra-wideband (UWB) DesignGuide to help prove UWB design concepts for prototyping. Agilent says the multiyear agreement includes licensing for ADS, its circuit and system simulators, the UWB DesignGuide, and Agilent test equipment.

Agilent Technologies also announced a new budget analysis capability in its ADS 2004A software that the company says "enables engineers to design RF systems more quickly and accurately, [because it] predicts RF system performance by considering specification tradeoffs, such as impedance mismatch versus gain, earlier in the design cycle. In the past, RF design budgeting was achieved mainly through spreadsheet-based analysis, a time-consuming and often cumbersome process."

Aldec, Inc. announced the release of Version 4.3 of its Active-HDL 6.3 co-simulation and debugging environment for ESL design and verification. The company says the release includes a direct kernel connection between Active-HDL’s mixed-language VHDL and Verilog HDL compilers and the C/C++ compiler, so that the co-simulation environment for SystemC is independent of the entry language. For the skeptics, Version 6.3 also includes some sample designs to illustrate the advantages of using SystemC with HDL and the benefits of ESL verification. The company says it has also redesigned the waveform viewer in Active-HDL 6.3 based on a new database and compression technique that enables viewing and managing of large files (1GB and larger) "almost instantaneously."

Altium Ltd. announced the release of a new universal JTAG interface to help engineers use Altium’s LiveDesign tool in the company’s Nexar system-level FPGA development software with "virtually any third-party FPGA development board." The JTAG interface attaches to the parallel port of a developer’s computer and includes a set of flying leads that connect to the target development board.

Per the Press Release: "The interface supports two independent JTAG connections - one to the JTAG programming pins of the target FPGA and the other to four general I/O pins of the FPGA used to establish a secondary ’soft‘ JTAG chain inside the device. The soft JTAG chain is used by Nexar to communicate in real-time with active design elements such as its processor cores and virtual instruments in the circuit implemented inside the FPGA, facilitating interactive development and debug of the system. The interface supports both the Xilinx ISE and Altera ByteBlaster cable standards, making it suitable for virtually any FPGA development board on the market."

ARM announced that it has released the latest PrimeXsys Platform, based on the ARM1176JZF-S 32-bit processor core, to STMicroelectronics. Richard Chesson, Director of Marketing in the Multimedia Platform Unit at ST, is quoted: "As an integral part of ST's Nomadik family of application processors' evolution, the ARM1176JZF-S PrimeXsys Platform with TrustZone technology will help ST to continue to offer the highest level of performance and security. By combining Nomadik's world-leading multimedia performance with the ARM1176JZF-S processor's computing power and security features, we can better deliver the rich multimedia content and experience, as well as application performance that customers of new mobile services and operators will demand."

ARM also announced the launch of the ARM Cortex-M3 processor, "which is specifically designed to meet the requirement for high system performance in extremely cost-sensitive embedded applications, such as microcontrollers, automotive body systems, white goods, and networking devices. This processor is the first member of the new ARM Cortex family of CPU cores."

Cadence Design Systems, Inc. announced a "comprehensive" assertion-based verification (ABV) solution" as a part of its Incisive functional verification platform. The company says the technology creates an environment that helps users define assertions, "enables early detection of bugs close to the source, and monitors for completeness through assertion coverage." Cadence also says that the ABV environment "brings together tools, language, IP, debug and coverage. It includes broad, native assertion support for Property Specification Language (PSL), SystemVerilog Assertions (SVA) and Open Verification Library (OVL). In addition to these Accellera standards, Cadence is also introducing an extended open-source library of assertions."

Cadence Design Systems also announced the Encounter Diagnostics yield diagnostics tool. The new tool aims to help customers identify "critical nanometer IC yield issues and precisely [locate] root cause defects. The result is higher yield in less time. The new tool supports all digital design styles and test vectors produced by all popular ATPG tools." Good stuff.

Chronology, which is now a division of Forte Design Systems, announced TimingDesigner version 7.0, which the company describes as "an interactive timing analysis and diagram product." Version 7.0’s project manager feature aids in the exchange of timing information and helps users manage the specification and analysis of interfaces for digital IC and board designs. Designers have the option to organize multiple diagram components within one project. Components and blocks are arranged and displayed in a single tree, with a summary list of all constraint violations in the project diagrams. Designers can also merge two diagrams from different components, to automatically create an interface to account for component connectivity, as well as to manage signal duplication and propagation delays.

CoWare Inc. and LSI Logic Corp. announced availability of ZSP SystemC-based models for use with the CoWare ConvergenSC design environment. LSI Logic says it developed cycle- and transaction-accurate SystemC-based models for each of the available ZSP cores and, through joint cooperation with CoWare, integrated the ZSP models into CoWare's ConvergenSC Model Library. Per the Press Release: "By running SystemC simulations and performance analysis in ConvergenSC with the new CoWare ZSP models, users can quickly determine the optimum architecture for their specific application and debug the interaction between software and hardware early in the design process. The tools let customers perform detailed analysis of processor throughput and latency, as well as memory subsystem performance and bus analysis."

Rafi Kedem, Senior Director of Marketing of the LSI Logic DSP Products Division, is quoted in the Press Release as well: "Designers can select the appropriate DSP core from the software compatible family of ZSP cores to handle the signal processing and system control tasks. The collaboration with CoWare helps our customers to develop applications in the wireless, voice and multimedia segments while beating their performance and cost goals for these complex SoC designs."

Denali Software, Inc. announced an IP core and design and verification IP software intended for use in the design and verification of chips that use ARM’s AMBA AXI interface. The new verification IP product is called PureSpec-AXI, and "leverages technology from its PureSpec product line to provide a comprehensive solution for pre-silicon verification of functionality, compliance and system-level verification of designs utilizing the AMBA AXI architecture."

Denali’s new IP core is called Databahn-AXI, and "builds upon Denali’s silicon-proven Databahn DDR controller IP, and provides developers with a native AMBA AXI interface for its DDR-based memory controller cores."

HelloSoft, Inc. and Toshiba America Electronic Components, Inc. (TAEC) announced an enhancement to HelloSoft’s voice over Internet Protocol (VoIP) software suite, which the companies say, has been optimized for the Toshiba T6TC1XB-0001 embedded controller.

Craig Mathias, a Principal with the Farpoint Group makes his voice heard in the Press Release: "Voice is becoming increasingly important on wireless LAN connections, and we expect it to become a major driver of the WLAN market over the next few years. Low-cost, high-performance implementations are of course critical to achieving broad market appeal, and we believe the combination of Toshiba’s chips and HelloSoft’s software really points the way here." Listen for him next via VoIP.

IMEC says it has developed a "completely integrated low-cost, low-power, pulse-based ultra-wideband pulser designed in 0.18µm CMOS logic technology. Micro-sized at a mere 0.6 by 0.6mm2, the transmitter operates between 3- and 5GHz yet is flexible in both center frequency and bandwidth." IMEC says this pulser is the key building block for the UWB transmitter, which is currently under development.

Kilopass Technology, Inc. announced that its XPM technology is now available for use in ASICs and SoCs using standard logic CMOS 90-nanometer silicon processes, in addition to its current products that are based on 0.18, 0.15, and 0.13-micron processes.

Jack Peng, CEO at Kilopass Technology, is quoted: "We have shipped our patented XPM technology to over a dozen customers, and are very pleased to announce that we have tested and verified silicon, in 90 nanometers, with 1,000 hours of burn-in, and that our customers expect to move from silicon prototypes to high volume manufacturing in the next few months."

Magma Design Automation Inc. and Cadence Design Systems announced that Magma's IC implementation system now supports the effective current source model (ECSM) from Cadence. The companies say that ECSM is now the timing model of choice for Magma's Blast Fusion because it improves delay calculation accuracy by modeling a cell's output drive as a current source rather than a voltage source. Per the Press Release: "Current sources are more effective at tracking non-linear transistor switching behavior and permit highly accurate modeling of long complex interconnects, common in many of today's largest nanometer low power designs."

Meanwhile, Magma Design Automation and Mentor Graphics Corp. announced an interoperability agreement to integrate the Mentor’s TestKompress embedded deterministic test (EDT) tool into Magma's RTL-to-GDSII design system. The companies say that through this agreement, Mentor and Magma will "provide mutual customers with an integrated IC implementation flow that includes comprehensive DFT capabilities to ensure design closure and testability of nanometer designs."

Robert Hum, Vice President and General Manager of the Design Verification and Test division at Mentor, is quoted in the Press Release: "It's imperative that our test solutions fit easily into any standard design flow, so we're pleased to be able to announce with Magma a comprehensive solution with our TestKompress tool. This collaboration with Magma enables us to provide our joint customers with an integrated flow from RTL to compressed test pattern generation."

[Wow, stuff is definitely happening here. Can you read the writing on the wall?]

Mentor Graphics also announced additional functionality for the Calibre platform in the form of Calibre Transition, Measure and Analyze to address critical design for manufacturing (DFM) requirements. At the same time, Mentor outlined its long-term roadmap for future Calibre DFM tools. Future enhancements will allow users to consider and optimize for manufacturing at various stages in the design flow: design, verification and analysis, tapeout and test.

Sonics Inc. announced its new SonicsMX product for "the design of low-power, cost-effective SoC devices powering multimedia-rich wireless and handheld products ... SonicsMX provides the physical structures, advanced protocols, and extensive power management capabilities necessary to overcome data flow and other design challenges associated with the convergence of multimedia and communications onto a single SoC."

The company says SonicsMX is the result of a "close collaboration" with Texas Instruments to verify that Sonics’ new SMART interconnect is suitable for low-power operation such as TI’s OMAP platforms. According to Grant Pierce, President and CEO of Sonics: "We announced a close working relationship with Texas Instruments last September and SonicsMX demonstrates our commitment to deliver interconnect solutions that give our customers a significant competitive advantage. We are excited to now make SonicsMX available to the general marketplace."

Stone Pillar Technologies Inc. announced that Micrel Inc. has adopted the DesignRuleBuilder component of the company’s Silicon Insight toolkit for "semiconductor technology development."

The Press Release goes on to say, "Technology development for advanced power semiconductor devices requires extremely complex design rules that must be flexible enough to accommodate rule variations based on device geometries, voltages, and applications. The large engineering investment for manually creating such rule sets makes it impractical to support multiple DRC/LVS (design rule checker/layout versus schematic) tools such as DRACULA and IC Editors. By providing a convenient GUI-based interface for rule creation, DesignRuleBuilder enables engineers to speed up runset creation and focus on the creation of high quality rules, rather than learning details of command language specific to individual DRC/LVS tools."

Synopsys, Inc. and Shanghai Hua Hong NEC Electronics Ltd. (HHNEC) announced that HHNEC has adopted Synopsys' Proteus optical proximity correction (OPC) software. In case you didn’t know, "HHNEC is a joint venture between NEC Corporation, Jazz Semiconductor and Shanghai Hua Hong Group, and is one of the leading 8-inch semiconductor foundries in China. HHNEC selected Proteus to increase accuracy, decrease mask synthesis turn-around-time and obtain higher yields through the utilization of Proteus' unique scaleable architecture."

SynTest Technologies announced that its DFT-PRO 100 and 200 Series of ATPG starter packages that will now include the essential DFT tools for comprehensive ASIC testing. The company says "these tools will be able to operate on scan-inserted netlists and will include tools for testing DFT rules' violations, automatic test pattern generation (ATPG), as well as test pattern formatting to directly link to ATE from popular vendors such as Advantest, Agilent, Credence and Teradyne."

SynTest adds: "Experience has shown that to ensure a high quality of complex ASICs with respect to manufacturing faults and to shorten test development time, DFT methodology must be employed into ASIC designs." That pretty much sums it up ...

Tensilica Inc. announced that ATI Technologies Inc. has licensed the Xtensa configurable processor. The companies say this license will allow ATI to add "specialized, customized functions that complement ATI's renowned graphics technology."

Adiran Hartog, CTO at ATI, is quoted in the Press Release: "By adding functions in Xtensa processors, rather than hand coding them in RTL, we can make these functions programmable, giving us plenty of flexibility for changing standards and feature sets."

Teseda Corp. and Yokogawa Electric Corp. announced that they will work together to verify transportability of Standard Test Interface Language (STIL) DFT data between the Teseda OpenDFT WorkBench engineering software and production test platforms. The companies say their efforts will help customers using the Teseda V520 and the Yokogawa TS6000 SOC Test family to validate, debug, and apply IEEE 1450 (STIL)-based production test data generated by EDA tools. The result will be "a test development flow that will cut weeks from time-to-money for many of today’s semiconductor products."

Steve Morris, President and CEO of Teseda, is quoted in the Press Release: "As part of our new OpenDFT initiative, the Teseda V520 engineering test platform running Teseda OpenDFT WorkBench software is a DFT productivity solution that saves weeks when validating and debugging DFT. Yokogawa’s adoption of a STIL-based flow is a perfect fit for Teseda’s OpenDFT production solution. By verifying STIL transportability we will enable our customers to move large volumes of test data from engineering to their Yokogawa testers on the production floor as quickly and efficiently as possible, reducing the cost of test."

Norio Kubo, General Manager of the SoC Department, ATE HQS Semiconductor Test Solution Division of Yokogawa, is also quoted: "Yokogawa is moving to a STIL-based flow to ensure our customers will have a smooth transition from design to test. By verifying STIL transportability with Teseda’s OpenDFT environment, our customers can be confident that their designs will transition quickly from engineering to production, shortening time-to-money."

Teseda Corp. also announced the OpenDFT initiative "to exploit the full power of design-for-test (DFT), uniting design, test, and manufacturing to cut weeks from time-to-money and improve device yield and profitability." Teseda says it has worked with EDA and ATE vendors to develop the OpenDFT WorkBench software to bring DFT-Intelligent interactive validation, debug, and diagnosis to ATE platforms.

Per the Press Release: "Teseda, in cooperation with Agilent Technologies, also announced the development of the Teseda OpenDFT WorkBench software for the Agilent 93000 SOC Series platform."

Toshiba Corp. and Xilinx, Inc. announced a "strategic foundry relationship" whereby Toshiba will manufacture Xilinx FPGA products. The companies say they have already accomplished one milestone in the relationship with the output of functional 90-nanometer first silicon at Toshiba’s 300-mm fab at Oita, in Kyushu, Japan. Subsequently, Toshiba will start volume manufacturing in Q1 2005.

In and around the marketing-speak in the following bit from the Press Release, there are these fascinating financial details: "As part of the manufacturing agreement, Xilinx will make advance payments to Toshiba, which will be offset against future wafer purchases. The amounts involved are not viewed as material to Xilinx. Success in the present agreement is expected to point the way to continued cooperation between Toshiba and Xilinx in next-generation 65-nanometer manufacturing process technology."

Xilinx also announced their EasyPath FPGAs, which the company describes as "the industry’s only customer-specific and flexible solution for volume production priced lower than structured ASICs."

In a phone call with Balaji Thirumalai, Senior Marketing Manager at Xilinx, I jotted down these comments: "This is a very important announcement from Xilinx, because in it we're calling the structured ASIC market irrelevant. In some cases, there might be applications where there's a continuum between structured ASICs and FPGAs. But, in general we're calling the viability of the entire structured ASIC market into question. We’re saying with our EasyPath FPGS, that at the price points that we’re offering [with these products], the structured ASIC market is irrelevant."

"But the real proof will play out in market place with actual customers. We'll get validation we need from our customers. Already they’re telling us, ‘You're giving us to give us a compelling reason [to go with FPGAs].’ It’s true, there are still some EDA vendors banking on structured ASIC, but most are realizing that there are two camps now. Some are [currently] making tools for both FPGAs and structured ASICs, our news will help them [decide if that strategy is necessary in the long run]."

Rounding out Thirumalai’s comments, here are some bits from the Press Materials: "Xilinx EasyPath FPGAs leverage both the inherent redundancy of FPGA devices and a patented testing methodology to deliver lower costs and unprecedented flexibility beyond what Structured ASICs can provide. Other advantages over Structured ASICs include industry’s lowest NREs, the only no-conversion path from a standard FPGA to volume production device, 8-week lead time from design completion to volume production, support for in-system ECOs, and two designs per device."

"Xilinx EasyPath FPGAs come with the most robust design ecosystem in the industry, along with the portfolio of industry-leading soft and hard IP, easy-to-use design tools, services and support. For Spartan-3 EasyPath and Virtex-4 EasyPath FPGAs only, we are announcing the ability to make changes to a LUT and/or the drive strength and slew rate of device IOs in the field. For example, as long as no routing changes are made to the device, a LUT could be changed from a 2-input NAND gate to a 2-input AND gate in an EasyPath FPGA without requiring any re-testing by Xilinx or the customer."