Actel Corp. and Mentor Graphics Corp. announced that the new version of Mentor Graphics' Precision RTL Synthesis tool is producing "significantly higher performance" on designs that use Actel's ProASIC Plus FPGA family, including designs with up to 30,000 logic tiles. The companies are reporting that customers using Precision should expect, on average, an 18-percent improvement in clock frequency over previous versions of the software. The Precision RTL Synthesis tool is integrated into Actel's Libero 6.0 IDE.

Agilent Technologies Inc. has introduced wireless test benches, sources and measurement capabilities for its Advanced Design System (ADS) 2004A EDA software that the company says allows RF circuit designers to verify subsystem performance in wireless communication products.

Per the Press Release: "Traditionally, nonlinear and distortion analysis and measurements rely only on discrete-tone figures of merit. Discrete-tone stimuli and measurements may prove inadequate since real-world sources have different signal characteristics such as power statistics. For accurate verification, designers must validate the performance of their circuit under real-world stimuli and with the system measurements that current standards require."

"The new ADS 2004A capabilities include configurable DSP-based modulated sources with RF and baseband outputs, a set of measurement expressions, and a range of wireless test benches for 3GPP, WLAN and TD-SCDMA technologies. Measurements such as error vector magnitude and bit-error rate can be performed directly on the circuit schematic, providing more accuracy, efficiency and ease-of-use for analysis and design of highly integrated circuits. The new sources and measurements use, when appropriate, the same >algorithms used in Agilent instruments to allow consistent verification from design to test."

Ansoft Corp. announced availability of SIwave v2. The product is a full-wave electromagnetic field simulator, which analyzes signal-integrity and power-integrity effects in PCBs and IC packages. The new release includes: power plane impedance, signal net analysis, resonant mode analysis, Spice export, robust meshing, automated geometry cleanup, unlimited undo and redo, a decoupling capacitor model library, and a frequency-dependent model for dielectric.

Per the Press Release: "SIwave's proprietary full-wave, finite-element technique allows designers to characterize simultaneous switching noise (SSN), inter-symbol interference, power and ground bounce, resonances, reflections and coupling between traces and power/ground planes. Engineers are now able to model entire PCBs and package structures using an analysis engine to generate both frequency- and time-domain results. SIwave is fully integrated to layout tools such as Cadence Allegro and APD and Synopsys Encore."

Apache Design Solutions announced that ATI Technologies Inc. has adopted Apache's full-chip dynamic physical power integrity flow. ATI says it is using Apache's RedHawk-SDL for cell-based dynamic voltage drop analysis and NSPICE-PI for global I/O simultaneous switching output (SSO) verification.

Per the Press Release: "ATI found traditional methods of static-only IR-drop analysis to be inadequate for their high-performance graphics processor designs. They saw that Apache's ability to perform full-chip dynamic power analysis, including the effectiveness of decoupling capacitance, and the verification of global I/O SSO, was important for their current and future designs."

Meanwhile, Cadence Design Systems, Inc. announced that ATI Technologies Inc. selected the Cadence Incisive Palladium acceleration and emulation system to verify some of its highly complex designs.

Cadence Design Systems also announced that NVIDIA used Cadence's Incisive Palladium system to "significantly reduce" its verification time for NVIDIA's new GeForce 6800 graphics processor. Brian Kelleher, Vice President of Hardware Engineering at NVIDIA, is quoted: "Previously, our verification process would take about two to three days per turn - the cycle for bug detection, identification and the repair process. Now, with Palladium, we average two to three turns per day, enabling us to meet time-to-market requirements that are essential to maintaining a strong leadership position in the graphics market."

Finally, Cadence announced that TelASIC Communications, Inc. got a 10x simulation performance increase in the course of developing the "world's fastest analog/digital converter." Cadence said that TelASIC used its Virtuoso UltraSim FastSPICE simulator to verify TelASIC's TC1410 ADC.

Don Devendorf, CTO at TelASIC, is quoted in the Press Release: "Using Virtuoso UltraSim, our designers were able to run multiple simulations on the entire ADC circuit in a few hours, producing accurate results and reducing our verification cycle from weeks to days. This provided us with a significant time-to-market advantage for the TC1410 ADC, which is quickly being designed into applications such as cellular base stations, spectrum analyzers, medical imaging equipment and high-resolution displays."

Carbon Design Systems announced it has integrated its DesignPlayer engine with Virtutech's Simics Instruction Set Simulator (ISS), which the companies say will enable customers with processor-based designs to execute operating systems and application-level software on a fast and accurate model of a chip or system. The companies are also announcing that this integration allowed Sun Microsystems to boot its Solaris operating system on a Simics-DesignPlayer model of their design.

Get down and technical and read this from the Press Release: "Carbon's SPEEDCompiler software creates a high-performance engine - DesignPlayer - from a design's synthesizable Verilog and/or VHDL. The DesignPlayer-Simics integration allows one or more DesignPlayers to be called directly from the Simics ISS. Unlike a traditional simulator, DesignPlayer is a simulation client - it doesn't control system time. The surrounding simulation environment - Simics - controls system time, which greatly minimizes the integration complexity. The Simics-DesignPlayer combination can run millions of instructions per second, since DesignPlayer only executes when it is called by the Simics ISS. This single master-of-time architecture removes the multiple-master performance bottleneck inherent in co-simulation. DesignPlayer can represent one or more chips and multiple engines can represent a system that encompasses hundreds of millions of gates."

"DesignPlayer is a soft model that is accurate to the hardware-cycle and register accurate. Unlike behavioral models or C models generated from an ideal specification, DesignPlayer behaves exactly like the hardware with all its errata. Hardware designers now have the cycles they need to run complete regression suites before chip tapeout. Software designers can finally test and debug their code on a high performance, cycle accurate, linkable model. Customers get an executable specification that contains the silicon errata for system integration and test."

Forte Design Systems announced that Sanyo Electric Co., LTD has adopted Forte's Cynthesizer SystemC behavioral synthesis tool for the implementation of Sanyo's designs for consumer semiconductor devices. Fumiaki Nagao, Senior Staff member at Sanyo Electronic, is quoted: "Forte's Cynthesizer has demonstrated its ability to quickly synthesize high-quality RTL from complex algorithms without sacrificing quality of results. We expect Cynthesizer to help cut months off our design cycle, while providing us with a complete and automated verification flow."

LogicVision, Inc. announced that the company is aligning with UMC to provide the foundry’s customers with access to LogicVision's wafer yield product. Frank Wen, UMC President, is quoted in the Press Release: "We believe this alliance will establish a new standard for rapid diagnosis of process issues associated with the increased design and process complexities of advanced technologies, allowing a faster ramp to full silicon yield."

From the Press Release, as well: "The LogicVision design-for-diagnostic product offering is aimed at developing increasingly higher wafer yields at 90 nanometers and below process geometries. Electronics manufacturers are moving to 90 nanometers and below technologies to take advantage of the significant benefits offered in terms of performance, power consumption and cost. Yet, over time, they want to achieve increasingly better yields. Through deployment and effective use of LogicVision’s software on its testers, UMC has an additional solution to achieve rapid and accurate fault diagnosis and extensive performance characterization. Because UMC is already shipping 90-nanometer silicon with good yields to customers, it was LogicVision’s leading foundry of choice for implementing this new program."

Mentor Graphics Corp. announced that its FastScan ATPG tool has been selected for UMC's 130- and 90-nanometer digital reference flow. Ken Liou, Director of the Design Support Division at UMC, is quoted: "We worked closely with Mentor Graphics to develop the ATPG portion of our reference flow. Using FastScan, we are able to achieve excellent test coverage which ensures we are providing our customers with high-test quality for their designs."

Novas Software, Inc. has announced that the company "continues to drive support for the Accellera SystemVerilog standard with hardware description language analysis (also known as linting) that builds on existing support for the language across the Company's debug solutions. The Novas nLint tool now provides basic rule-checking capabilities for all SystemVerilog 3.0 design constructs to enable the early detection of design problems in IC development methodologies. The availability of SystemVerilog linting aids the adoption of unfamiliar, advanced coding constructs, which is critical as SoC designers get up to speed with the new language."

Dave Kelf, Vice President of Marketing at Novas, is quoted: "Linting will become a key technology that enables designers to become more familiar with the SystemVerilog language and effectively leverage new constructs. nLint brings SystemVerilog source code checking and debug automation together for the first time. Designers can verify design rule conformance and enforce SystemVerilog coding standards and reuse practices, all the while improving their debug productivity with greater understanding of design behavior."

Dave and I also spoke by phone regarding the Novas announcement. He told me, "We're pretty far along at this point with SystemVerilog. We're at a point where we've reached some major milestones including some product work creating effective, powerful things in the linting area. [We're issuing this announcement] partly to dispel the notion that Novas is the laggard in this area."

"Basically, right now I think there are 4 or 5 major companies today who are actively trying to use SystemVerilog for design and are having success. There are 4 or 5 other companies who are watching - large electronics companies - and they're discovering that SystemVerilog is very useful for pipelining and data control. They're trying to leverage [the usefulness of SystemVerilog] and trying to drive the EDA vendors to work on it - they're driving companies like Novas, Synopsys, and other EDA providers to rapidly do SystemVerilog implementations. [Customers now have access to] simulation tools, debugging tools, synthesis of course, and one or two other areas where SystemVerilog implementation is pretty far advanced. Novas is [well along in the process], as is Synopsys, Mentor, Verisity, Cadence and other players."

"I believe that by 2005, we're going to see SystemVerilog being used for design in a whole-hearted fashion. Assertions will be coming on-line at that same time as well. It's an open question right now, however, whether testbenches will be used, although there are companies trying it right now."

"I was talking recently to folks from Co-design, and they all agree that we're on the right path [with respect so SystemVerilog] right now. We're all happy to see the language being used as we thought it would be [when we were all together at Co-design before it was purchased by Synopsys]. We all like to think that we spotted the trend a little earlier than most."

"Of course, I see SystemC as becoming very important as well, but SystemVerilog and SystemC are different languages for different purposes. There's much more usage of both languages and as the users [become more mature with respect to the languages], the usage attitudes become more mature as well."

"[There was a time when the languages were thrown out there and both claimed to be a panacea for the new, complete design flow. But from the beginning, the value of C-based languages had to be related to software design, while SystemVerilog was where people were writing testbenches and trying to improve hardware design. Although [initially] they may have been portrayed differently, now the specific value of each language is [becoming] clear to the customers."

Optimal Corp. and Applied Wave Research, Inc. (AWR) announced what the companies are calling "the first commercially-available three-dimensional (3-D) full-wave electromagnetic (EM) extraction design flow. This AWR-Optimal methodology addresses complex signaling issues in wireless communications integrated circuit (IC) designs operating from one GHz to over 50 GHz. Combining Optimal's O-Wave product with AWR's Microwave Office and Analog Office design suites through the AWR EM Socket interface, this new design flow enables microwave and radio-frequency (RF) designers to quickly and seamlessly perform accurate 3-D full-wave EM simulation and parasitic extraction in order to verify the performance of entire chips before committing the designs to fabrication."

James Spoto, AWR President and CEO, is quoted: "The challenges facing designers of wireless products are quite substantial and require a software solution that is built on an open, standard-based software platform, allowing easy integration of the most capable, best-in-class tools to capture, synthesize, simulate, optimize, layout, extract, and verify designs in all domains. This alliance is an excellent example of how AWR's unique, open, high-frequency design environment can integrate with Optimal's leading edge 3-D full-wave EM simulation tool to provide designers with a first-to-market, complete design flow solution."

Len Perham, Chairman and CEO of Optimal, is also quoted: "RFIC is a rapidly-growing area in the semiconductor industry. Our alliance with AWR provides customers in the microwave, MMIC and RFIC markets with cutting edge 3-D full-wave extraction capability. O-Wave's ability to accurately simulate lossy substrates with 10-times better performance than other tools provides designers with a powerful solution for efficiently analyzing and optimizing their designs. As technology alliance partners, AWR and Optimal demonstrate the ability of two vendors with leading-edge technology to collaborate successfully in order to provide intrinsic value to the customer, in this case, the microwave and RFIC designers who are encountering increasingly challenging circuit problems at the advanced semiconductor technology nodes."

Synopsys, Inc. announced that its DesignWare Endpoint Controller IP core for PCI Express is "the first such IP to successfully pass compliance tests from the PCI-SIG." Testing involved using the DesignWare verification IP for PCI Express architecture to verify the endpoint controller core and an FPGA hardware add-in card for compliance and interoperability testing. The hardware add-in card is configured as a 10/100 Ethernet application for testing in PCI Express architecture-based systems and uses a daughter card to enable interoperability testing of the DesignWare Core for PCI Express with PIPE compliant PHYs.

Tony Pierce, PCI-SIG Chairman, is quoted in the Press Release: "As PCI Express technology is experiencing rapid adoption in the industry, compliance testing is critical to ensure interoperability of products based on the PCI Express architecture. The PCI-SIG has established a set of compliance tests, which products must pass to be included in the PCI-SIG Integrators List - We are pleased to see that Synopsys is included in the first group of member companies whose PCI Express-based product has passed the compliance tests and is on the Integrators List."

Tharas Systems Inc. announced the Tharas Flexible On-demand Rental Collaborative Environment - T-FORCE - which is an on-site subscription verification program.

Per the Press Release: "T-FORCE, with subscription rates starting at $10,000 per month, is the most cost-effective subscription program on the market for accelerated functional verification of complex ASIC and system designs. T-FORCE, developed for customers with flexible verification needs, provides best-in-class accelerated verification at an affordable price. Projects with fluctuating verification capacity needs can increase or decrease hardware-assisted verification as necessary. The entry level of the program gives a customer the ability to verify up to 4-million gates ... Purchasing hardware-assisted verification technology is a huge capital expense that carries the very real possibility of obsolescing that investment every other year. T-FORCE virtually eliminates the fiduciary concern with on-demand access to capacity and performance throughput at an affordable price. The on-site subscription model builds acquisition credits towards future purchases."