Apache Design Solutions announced new capabilities in its RedHawk-SDL product for addressing dynamic power integrity issues for advanced low power designs. The company says the new capabilities speak to the critical need to accurately analyze the impact of dynamic supply noise to chip timing. RedHawk-SDL enhancements will allow design teams to "verify the impact of dynamic power supply noise on chips that employ low power design techniques and timing of high performance SoCs."

Per the Press Release: "Power consumption has become a key limitation for high-speed, high-data-rate electronic systems. To address power limitations, advanced techniques and methodologies are being applied to chip designs that consume less power while maintaining the frequency required for high-performance operations. In addition to the widely used gated-clock approach, low-power design techniques such as the use of multiple Vth transistors, multiple voltage domains, power gating, and dynamic back-biasing are rapidly being adopted. However, the use of these techniques creates a major challenge in physical power integrity analysis and verification. [Therefore], unlike static-only or pseudo-dynamic approach to power grid verification, RedHawk-SDL's full-chip transient simulation (time-point by time-point) identifies critical issues for low power designs. RedHawk-SDL's new release will support design techniques based on multiple Vth and multiple Vdd domains, and header/footer switches."

Barcelona Design Inc. announced that it’s opening up its "silicon-proven" synthesis technology to analog designers through the launch of two new equation-based modeling and optimization products. Barcelona's new tools are StudioTM Circuit Modeler and SculptorTM Circuit Synthesizer, and the technology "enables simultaneous optimization of performance goals, process variation, voltage, and temperature constraints with over 100,000 parameters."

Studio allows users to capture the design intent of any circuit, whether at the system, component, or transistor levels, into synthesizable equations and constraints. Studio includes a variety of modeling techniques that allow analog designers to trade off development effort, operational ranges and accuracy as they develop their circuit models. Designers can use the Sculptor product to synthesize these models into optimally sized circuits that meet performance and manufacturability specifications.

Barcelona says the new products will allow analog designers to design their own circuits so as to hit both performance targets and yield targets within scheduling requirements. The Press Release also says, "With this launch, Barcelona increases its focus and charges ahead to be the leading EDA vendor providing next-generation analog tools and libraries that meet leading edge requirements."

Cadence Design Systems, Inc. and EMA Design Automation announced that the two companies will provide the ActiveParts Online Database free to all existing OrCAD Capture CIS customers. ActiveParts provides access to over 2 million parts, most of which include OrCAD Capture symbols.

Bonneville Minott, Circuit Design/Quality Assurance Manager for the Regional Technology Support Center at Epson Canada Ltd., is quoted in the Press Release: "We typically spend many hours searching manufacturers' Web sites and databooks for new parts for a design. With ActiveParts, not only can we search in one place, but the parts are also immediately ready for placement into our design. Many of the parts even have OrCAD Layout footprints, allowing these parts to go straight to board layout."

Celoxica, Ltd. announced availability of the DK Accelerator for Altera’s SOPC Builder. The companies say that DK Accelerator generates FPGA hardware components directly from Handel-C descriptions for use in the SOPC Builder system development tool. The DK Accelerator, combined with SOPC Builder, provides an automated implementation path for C-language algorithms to system-on-a-programmable chip (SOPC) designs.

Per the Press Release: "SOPC Builder, an automated system integration tool included within the Altera Quartus II design software, lets system designers define and implement an SOPC design by specifying the building blocks or components. The Celoxica DK Accelerator for the SOPC Builder tool enhances this flow by automatically generating SOPC Builder components directly from C-language descriptions of custom algorithms. For each algorithm, the tool automatically converts the software into FPGA logic that the SOPC Builder tool can integrate along with other components to provide critical product differentiation. The created components can be used and re-used in the same manner as other off-the-shelf components."

CriticalBlue announced availability of its Cascade tool. Cascade is described as a "co-processor synthesis solution that delivers an automated migration path from compiled embedded software directly to hardware within existing implementation flows. Working closely with design groups to solve issues dealing with legacy and incremental software within application platforms, Cascade has been architected to facilitate low risk and rapid deployment of platform variants to address new market opportunities."

"Taking the executable code compiled for the main system processor as its input, Cascade works with standard development environments, including embedded software, system-level, and hardware implementation flows. Since it operates within the current software and hardware implementation environments, Cascade is able to support the reuse of existing designs, and/or the integration of new third party software functionality into an existing platform. CriticalBlue's technology makes possible a low risk route for new designs and the rapid creation of faster, cheaper, more flexible, and/or lower power version of existing platforms. The co-processor generated by Cascade is a fully functional programmable machine, and the tool can modify the co-processor's implemented functionality by updating its software, while reusing its hardware."

In related news, CriticalBlue announced the integration of its Cascade technology into standard implementation flows featuring tools from Synplicity and Cadence, among others. The company says the integration work will "ensure that CriticalBlue's technology fits smoothly within industry standard development and verification environments for embedded software and hardware implementation."

Bob Erickson, Vice President of Engineering at Synplicity, is quoted in the Press Release: "We believe that the Cascade technology is compatible with both traditional FPGA users and those who are adopting structured ASICs. In both cases embedded software is the starting point for much of the functionality that ends up in hardware on these classes of designs."

eASIC Corp. announced the tape out of its first Structured ASIC array, which the company says will be fabricated by an IDM partner in Europe at 0.13-micron technology. The taped-out array is called "FA1," and is the smallest member to date of the company’s Structured eASIC product family. The company says initial parts will be used to characterize timing and power for the Structured ASIC fabric and cell libraries. The complete product family is scheduled to be released for production in early Q1 2005. The product is being co-developed with Flextronics Semiconductor who is announcing that they will be offering Structured ASIC products and services.

The technical details are courtesy of the Press Release: "The patented Structured eASIC architecture consists of an array of logic cells (eCells) with SRAM based LUTs (Look Up Table) and flip-flops. eCells are inter-connected by a segmented wiring grid utilizing upper metal layers, which are customized per customer design with a single Via-mask. Logic programming of the eCell is done similarly to an FPGA, by loading a bit-stream to program the LUTs and flip-flops after powering up the device. Thus, a customer design is implemented on the Structured eASIC fabric by using a combination of bit-stream to program the LUTs and single custom Via-mask for customizing the routing. Moreover, single Via-customization is a perfect fit for an alternative lithography approach, namely the Direct-write eBeam. Using Direct-write eBeam completely eliminates the customization tooling cost, shortens time-to-market and adds manufacturing flexibility."

Rich Wawrzyniak, Senior Analyst, ASIC/SoC at Semico Research Corp., is quoted in the same Press Release: "The rising costs and increasing design cycle times for standard cell and SoC products has pushed many would-be users out of the market and forced them to explore other alternatives. The structured ASIC approach provides these would-be users with a welcome alternative. The direct-write eBeam approach employed by eASIC allows for an even lower manufacturing cost which enables even more would-be users to consider an ASIC solution once again and increases the potential market even more."

FishTail Design Automation announced that Toshiba’s System LSI Division has purchased the company’s Focus product, which generates false and multi-cycle paths, for use in Toshiba’s System LSI chip-implementation projects. Masato Nagamatsu, Senior Manager from Toshiba, is quoted: "Prior to Focus, we had to manually sift through timing reports and establish whether timing problems were real. This was a tedious, error-prone and time-consuming task, taking several weeks. By deploying Focus, we expect to be able to significantly reduce the time we spend during timing closure."

Mentor Graphics Corp. announced that its Calibre design-to-silicon platform is now an "approved physical verification tool" for the 90-nanometer semiconductor process platform jointly developed by IBM and Chartered Semiconductor Manufacturing. The companies say that validation efforts were conducted as part of the IBM-Chartered cross-foundry design enablement program aimed at reducing the risks and costs of designing chips manufactured with the IBM-Chartered 90-nanometer process.

Tom Reeves, Vice President, Semiconductor Products and Solutions, IBM Systems & Technology Group, is quoted in the Press Release: "Our design enablement program ensures that chip designers have access to leading-edge technologies that have been validated by our internal 90-nanometer development team."

Magma Design Automation Inc. announced the availability of a preliminary 90-nanometer RTL-to-GDSII design enablement kit in support of the recently announced IBM-Chartered cross-foundry design enablement program. The kit includes a standard cell library, Magma technology and setup files, and a reference design flow for high-performance, power-optimized designs.

Tom Reeves, IBM Systems & Technology Group, is quoted here as well: "We've qualified Magma's design methodology starting with its 0.13-micron 'Ready for IBM Technology' reference design flow. We are committed to continuing to work with Magma to provide support for the newest processes."

Kevin Meyer, Vice President of Worldwide Marketing and Services at Chartered Semiconductor Manufacturing, is also quoted: "The Magma 90-nanometer design enablement kit minimizes the learning curve by offering a truly streamlined RTL-to-GDSII design flow pre-loaded with the 90-nanometer design rules and library, helping designers get started right away."

Prosilog SA announced the integration of ST Microelectronic's TC4SOC multimedia platform within its Magillem environment. Dominique Hénoff, Project Design Manager, Consumer & Microcontroller Groups, is quoted in the Press Release: "STMicroelectronics has been working closely with Prosilog with the common goal to demonstrate that Magillem is the suitable environment to import, integrate IPs and generate a SoC platform compliant to the SPIRIT(*) recommendations. STMicroelectronics is a strong advocate of standardization IP exchange formats. This is why we have jointly initiated the SPIRIT consortium. Our TC4SOC platform is a good driver to demonstrate the capabilities of the EDA tools in that context; we are already very satisfied with the results the Magillem environment from Prosilog is showing."

Cyril Spasevski, Magillem Project Manager for Prosilog, is also quoted: "Our Magillem environment has been built natively around the XML language which is being standardized through the SPIRIT consortium. With STMicroelectronics collaboration, we have integrated
all the IP blocks from the TC4SOC platform; we are able to generate not only the RTL
code of the platform but the documentation and register shielding as well."

Sigrity, Inc. has introduced the XcitePI tool for performing dynamic simulation of full-chip power grid structure with package effects to determine the severity of power integrity issues. The company says the new tool can help customers in the semiconductor, computer, graphics, communications, and networking industries eliminate costly re-spins for complex ICs.

The technical details are here in the Press Release: "Sigrity's XcitePI tool analyzes the power grid with distributed electromagnetic field propagation effects of the package, and capacitive and inductive coupling between all conductors of the IC power grid. Once noise is generated at certain locations of a chip, it often propagates more easily to other locations of the chip through the package power and ground structures, rather than directly through the power grid itself. Lumped RLC off-chip models cannot adequately model such effects; leaving corresponding software tools unable to determine the true transient noise distribution and behavior in the power delivery system."

"[However], XcitePI performs transient analysis of the IC power grid simultaneously with dynamic simulation of electromagnetic fields in the package planes, taking into account both the wave propagation effects in the package and distributed interaction of the IC power grid and package planes. XcitePI uses the fastest known simulation engine, especially designed for power grids, to accomplish transient simulation of the full-chip power grid with package planes. It enables chip and package design engineers to find noise voltage fluctuations; assess the effects of decoupling capacitors, power grid physical parameters and package power and ground planes; and conduct ‘what if’ analysis to optimize their designs."

Jiayuan Fang, President of Sigrity, is also quoted in the Press Release: "Many companies face daunting signal integrity and power integrity design challenges as they try to figure out what the noise effects are and where they are located, and then devise strategies to eliminate them. Success requires the ability to adequately analyze the entire power delivery system – from chip to package to board – to ensure the integrity of power delivery systems and to prevent costly re-spins. That's a unique capability Sigrity brings to the market, due to our established work and success in power-integrity solutions for boards and packages. Now we are extending it to ICs."

In related news, Sigrity, Inc. announced its support of Cadence Design System’s new Allegro system interconnect design platform. The company says that the "key" Sigrity product that supports Allegro is the SPEED2000 transient time-domain simulation software tool.

Silicon Design Systems, Inc. announced K-Route, which the company says is "the first truly concurrent routing technology to solve IC design closure issues magnified by submicron and nanometer technology."

I had a chance to speak with Naeem Zafar, President and CEO of Silicon Design Systems, on the phone recently regarding the company’s announcement. What he told me dovetails well with his quote in the Press Release:

"Silicon Design Systems had used commercial backend tools for the last seven years; we knew first-hand the frustration of closure predictability problems as we searched in vain for commercially available EDA tools to address them. Deciding to tackle the issue ourselves, we developed K-Route as a novel ‘think-then-route’ approach, rather than the traditional ‘route-then-think’ technique. Unlike methodologies that merely minimize violations, K-Route actually solves them, letting companies achieve detailed closure, instead of statistical closure, and create far more efficient design than with traditional cell-based ASIC flows."

The Press Release also details the strategy behind the new release: "[K-Route’s] revolutionary adaptive, fine-grained routing architecture simultaneously uses routing, extraction, analysis and optimization engines to complete tightly constrained designs faster and more predictably. The convergent router automatically recognizes and fixes all potential geometrical, timing and signal integrity violations, allowing for smaller design area and significantly improved performance, power consumption and time to tape-out. Silicon Design System architecture allows several engines to work together, solving each problem simultaneously from various domains – geometrical, timing, noise and signal integrity. Adaptive algorithms enable designers to make intelligent choices, given constraints, to achieve convergence." A clever twist on the classic whack-a-mole strategy that may indeed show the way to design closure.

Synopsys, Inc. announced the latest release of the VCS RTL verification tool. The new release includes support for the same "next-generation" constraint-solver engines used in the Vera testbench automation tool, support for object-oriented testbench architecture, and advanced data types. The company says that with the addition of these new capabilities, "engineers can use VCS to create and run powerful constrained-random testbenches using a single unified tool for maximum productivity and improved overall verification run time by up to five times, including simulation of design, testbenches and assertions, compared with standalone testbench tools working with VCS."

Shrenik Mehta, Director of Frontend Technologies, Scalable Systems Group at Sun Microsystems, is quoted in the Press Release: "We are continuously improving our verification methodologies. By using the testbench and assertion capabilities built into VCS, our engineers are able to write powerful testbenches that run faster compared to other standalone solutions from Synopsys, allowing us to run more verification cycles in the given time."

Synopsys also announced that National Semiconductor Corp. has standardized on Synopsys’ VCS RTL verification too (part of the Discovery Verification Platform), Leda programmable design checker, and Formality functional equivalence checker.

Finally, Synopsys announced that Renesas Technology Corp., a joint venture between Hitachi, Ltd. and Mitsubishi Electric Corp., has adopted Synopsys' JupiterXT design planning flow to "improve turnaround time on chips for leading consumer electronics devices."

Tenison EDA announced VTOC Export, for secure IP distribution. VTOC Export is based on the company’s VTOC tool and allows for the creation of cycle-accurate executable models in C++ of existing IP written in RTL. These models are "secure" in that the original design cannot be interpreted from them, and are controllable in their distribution based on the embedded licensing scheme. The resulting models are distributable to third parties while still remaining under authorized control, and also yield a high-speed prototype for the customer to use in evaluating the IP for use or purchase. The models created with VTOC Export do not require the customer to own VTOC in order to execute, but do require an authorization code from the distributor. Use of VTOC Export requires a VTOC license.

Tensilica, Inc. announced the Xtensa LX configurable processor, which the company describes as "the highest performance processor core on the market, featuring both higher computational throughput and dramatically higher I/O bandwidth. This record-breaking performance, combined with Tensilica’s patented automated design and development environment, makes Xtensa LX the only processor fast and flexible enough to replace RTL design methodologies in SOC designs."

Tensilica says it expects that most of its customers will use multiple Xtensa LX cores in each of their SoC designs, each core being tailored to speed a different part of the customer’s application.

Chris Rowen, President and CEO of Tensilica, is quoted in the Press Release: "With the Xtensa LX processor, designers can configure optimized processors specifically tuned to their application in a fraction of the time that it takes to design and verify RTL, with comparable computational and I/O performance. The inherent programmability of the processor gives designers the flexibility to fix bugs and add features purely in software at any point – late in the design cycle or long after first shipment. This is impossible with hard-coded RTL."

In clearly related news, Tensilica announced that its new Xtensa LX configurable processor core has received "the highest certified out-of-the-box score ever recorded for any 32-bit or 64-bit processor core tested against the Consumer benchmark suite of the Embedded Microprocessor Benchmark Consortium (EEMBC). The Xtensa LX processor’s score of 0.51997 per MHz, which translates to 171.6 Consumermarks in a 330-MHz simulation, was nearly nine times faster than the next best 32-bit device and over five times as fast as the fastest 64-bit RISC CPU tested by EEMBC."

Markus Levy, EEMBC President, is quoted in the Press Release: "The out-of-the-box scores are a good test of compiler performance. The more C-friendly the processor, the better the score, as the processor vendor is not allowed to modify the original EEMBC source code. The exceptional results for the Xtensa LX processor show that Tensilica has developed some very advanced compiler technology." Probably an understatement, if ever there was one.

Meanwhile, for those of you who don’t yet know: "The EEMBC Consumer Benchmark Suite is a compilation of five separate benchmark kernels that are representative of consumer digital imaging applications. The high-pass grey-scale filter benchmark demonstrates performance in front-end processing of digital still cameras, showcasing 2-D data array and multiply/accumulate capabilities. The JPEG compression and decompression benchmarks take still images from full source data captured from a sensor, compress to a JPEG file format for data storage, and reconvert back to full image representation, a common set of tasks in consumer products such as digital still cameras and digital video camcorders. The RGB to CYMK conversion benchmark demonstrates a common conversion used in color printing. The RGB to VIQ conversion benchmark demonstrates a conversion used in NTSC encoders for digital video processing."

TransEDA announced availability of the company's VN-Spec specification coverage and impact analysis tool. The company says the VN-Spec product is the results of "synergy" between TransEDA's coverage products and TNI-Valiosys' technologies.

Per the Press Release: "Today, there is a gap in front-end verification methodology as most engineering efforts focus on checking implementation refinements against the first model written at the system or HDL level, rather than against the initial specifications. VN-Spec fills this gap by unambiguously identifying requirements in the specification documents, and then tracking the coverage of these requirements throughout the entire implementation and verification process."

Jean-Luc Bouvresse, CEO of TransEDA, is quoted: "Our customers can now start their coverage-driven verification earlier, at the specification level, to verify that their designs meet the initial specifications. VN-Spec enables designers to focus the verification effort on their customers' requirements and in this way augments their confidence in the quality of their SoC designs."

In related news, TransEDA also announced availability of a coverability analysis option to the company's VN-Cover coverage analysis tool. TransEDA says it has extended the scope of its coverage solutions that help guide designers to full coverage from specification to functional coverage, across design languages and simulation platforms. The company also says the new coverability analysis option to VN-Cover results from yet more "synergy" between TransEDA's coverage products and TNI-Valiosys' formal verification technologies.

Per this Press Release: "In order to fulfill their test plan, most verification engineers have coverage targets to meet. In practice, it is generally not a problem to reach 90-percent structural coverage, but it often turns out to be a real burden to find stimuli that trigger the remaining uncovered areas. Meeting the coverage goals can hence be a painful and time-consuming task. Moreover, setting a coverage target questions how coverage is measured.

A coverage-driven verification methodology strongly relies on the correctness of the coverage measurement. Accuracy is therefore critical to set reachable coverage goals and insure convergence of random or pseudo-random tests."