Dare you to read all of this …
Best of Show is at the bottom, although there's a Best of Show Paragraph in there mid-stream.

AccelChip Inc. announced its 2005.1 release of AccelWare IP toolkits and AccelChip DSP Synthesis product. The company says its new AccelWare cores "extend the company’s leadership position in cores that directly implement matrix operations for wireless communications, signal processing, and other forward-error correction applications. Additionally, the 2005.1 version of the AccelChip DSP Synthesis tool integrates the algorithmic synthesis environment based on MATLAB with Xilinx System Generator."

Getting technical, the Press Release says: "AccelWare DSP IP cores produce the industry’s only fixed-point, hardware implementations of matrix inversion and matrix factorization. Building upon its recent release of QR factorization and inversion cores, AccelChip has added Cholesky matrix factorization and matrix inversion to its IP products. Matrix factorization and inversion are used with algorithms utilizing linear algebra techniques, for example, adaptive filters which are used in a wide range of applications from radar to global positioning systems. The 2005.1 release also features new and enhanced cores that are fundamental to the development of Software Defined Radio (SDR), Digital Video Broadcasting, and other wireless communication applications."

Michael Bohm, CTO and Vice President of Engineering at AccelChip, is quoted: "IP is an absolute requirement for algorithm development and implementation in DSP. Virtually every DSP design we see can take advantage of cores to accelerate their development. Our AccelWare toolkits include more than 50 AccelWare IP cores with over 110 unique micro-architectures that are parameterized, reusable, and retargetable. Using the combination of application-specific cores with AccelChip algorithmic synthesis, our customers find they require minimal modification to their MATLAB and obtain optimized hardware more quickly than with alternative methods."

Accelerated Technology, a Mentor Graphics Division, announced its Nucleus Inter-processor Communications (IPC) software, which the company says is "an application-level tool that enables high-speed communications between two or more processors running on the same chip, computer or over a network. With the Nucleus IPC software, embedded developers can efficiently and better control their multi-core processor implementation and common RTOS API across all their processors."

Per the Press Release: "The number of different multi-core processors introduced into the embedded market continues to rise. To facilitate communication between these processors, the Nucleus IPC software works in either heterogeneous or homogeneous environments. The software also offers embedded developers an easy-to-use, nine-function API, simultaneous multi-port, and multi-task Inter-processor communication."

Accelerated Technology also announced that a Running System Debug (RSD) enhancement supporting the ARM RealView Developer Suite has been added to the Nucleus PLUS real-time kernel. The company says this enhancement will allow the Nucleus software application developers using the RealView RVD Debugger to halt individual Nucleus software tasks without needing to halt the CPU.

Agilent Technologies Inc. announced "breakthroughs" in its EDA frequency-domain simulation technologies for RFIC, MMIC, and RF SiP design. The company says, "Simulation speed improvements of up to 50 times have been achieved for large and complex circuits used in wireless communications products and aerospace and defense applications … Customers have observed excellent results with test circuits containing thousands of transistors, such as transceiver ICs for wireless local area network (LAN) applications. "

Larry Lerner, R&D Manager of Agilent’s EEsof EDA Division, is quoted: "Our customers’ designs are continually becoming larger and more complex, so we have been investing heavily in our core RF simulation technology. Based on early reactions from customers, these investments are paying off substantially."

Altium Ltd. has announced a "product roadmap" for P-CAD. The company says the roadmap is "an insight into Altium’s ongoing support and development of P-CAD, and demonstrates Altium’s commitment to meeting the current and future design needs of its customers."

Nick Martin, Founder and Joint CEO at Altium, is quoted: "Altium is committed to the ongoing development of the P-CAD design system. We are presenting our customers with a systematic, approachable and incremental way to realize value from their investments with Altium."

Ansoft Corp. says it has released a new version of AnsoftLinks that includes support for Mentor Graphics PADS Layout (formerly PowerPCB). The company says that AnsoftLinks allows for direct import of third-party PCB/CAD databases into Ansoft's electromagnetics software. Additional enhancements in AnsoftLinks include: Simplification of the vias option for solid-model export; Via fill option to define thickness in model units; Ability to define a number of facets for pads and antipads; Exportation of defeatured Ansoft files with plane extents; Integration enhancements for other third-party tools from Cadence, Mentor Graphics, Synopsys and Zuken

Apache Design Solutions announced that STMicroelectronics has adopted Apache’s SoC power closure sign-off flow for its on ST’s Nomadik TM low-power application processor designs.

Alain Artieri R&D director for Nomadik Multimedia Platforms at STMicroelectronics, is quoted in the Press Release: "As we use new design techniques to address the challenges of leakage current and rigid power requirements, we needed an accurate method for verifying the chips’ power, timing and functionality. Apache’s silicon proven dynamic power integrity solution offers the most accurate verification for our advanced low power design techniques, including power-gating."

Arithmatica, Inc. announced that Xilinx, Inc. used Arithmatica's CellMathT IP in its Virtex-4 SX55 FPGA. The companies say the SX55 device delivers 256 billion multiply-and-accumulate per second (MAC/s) processing performance, and with 512 XtremeDSPT Slices, is the highest-performance member of the SX family.

Brent Przybus, Senior Manager of Product Marketing for the Advanced Products Group at Xilinx, is quoted: "The power and versatility of CellMath IP made it an ideal choice for Virtex-4 signal processing solutions. Many of our customers are trying to solve very complex signal processing challenges such as those associated with base stations and software defined radio (SDR) and these require the highest performance at the lowest per function power consumption."

Arteris SA announced its first product offering, which the company describes as "a complete solution for creating Networks-on-Chip (NoC). Arteris NoC Solution is used to connect and manage the communication between the variety of design elements and IP blocks required in today's complex SoCs. The company's proprietary IP library utilizes a packet-based switch fabric in conjunction with Arteris NoC specific design tools to generate unique NoC instances. The result is the first commercial NoC solution that overcomes the limitations of traditional bus-based methods, while maintaining compatibility with existing interface standards and design tool flows."

The Press Release adds: "While NoC has been an emerging area of academic and research interest, Arteris is the first to offer a commercial solution for chip designers. Like the networking of computers, NoC provides an efficient means to manage communications among any collection of distributed systems, which in the case of a complex SoC can be individual IP blocks and/or clusters of functionality that all must communicate with each other. The proliferation of tens, even hundreds, of IP blocks on a single chip, as well as the advent of ultra-thin line widths in deep-submicron processes, have made traditional on-chip communications methods such as buses an increasingly substantial obstacle in the way of realizing the full potential of SoC implementations."

Atmel Corp. and Celoxica Ltd. announced a cooperation that "extends ESL design to a family of dynamically reconfigurable processors currently under development at Atmel." The companies say these backend tools are being developed for processors based on Atmel’s FPSLIC technology that is planned for introduction later this year.

Per the Press Release: "Tools from Celoxica’s ESL portfolio, the DK Design Suite and Agility Compiler will synthesize hardware accelerators from highly complex algorithms described in C or SystemC. Celoxica will also provide its HW/SW co-design technology and board-level integration technology to offer Atmel customers a seamless implementation flow. The tools are new to the industry because they allow for dynamic reconfiguration. More than 4 years of research undertaken at the Academy of Sciences of the Czech Republic has led to this cooperative development. Researchers from the Academy’s Institute of Information Theory and Automation (UTIA) collaborated with both Atmel and Celoxica to define and prove the flow from algorithm to implementation. "

Cadence Design Systems, Inc. announced that it has contributed its custom-design schematic symbol set to the OpenKit Initiative, which is part of Accellera.

Per the Press Release: "The Cadence contribution will form the basis of an open standard for the electronic representation of device symbols. Design kits provide the design rules, device models, schematic symbols and associated formats required by EDA tools during the design entry, simulation, implementation and verification steps of IC design. With the emergence of the design chain, design kits have become essential for linking semiconductor manufacturers and design teams developing IC-based products. With no current standards, nomenclature, use models, interfaces, quality thresholds, and delivery structures can vary widely, depending on the selection of tools, library or IP and targeted foundry requirements. The OpenKit Initiative has been working to address these problems since January 2004, and the Cadence donation represents a critical first step in creating standards for the design-capture phase of custom IC design."

Dennis Brophy, Chairman of Accellera, is quoted: "This is a great example of how Accellera works with leading EDA companies to accelerate the development of standards important to the growth of our industry. Cadence's contribution is the first step in establishing an IEEE standard for a schematic symbol set."

Jan Willis, Senior Vice President of Industry Alliances at Cadence, is also quoted: "Working with groups such as Accellera and Si2, we are actively involved in defining the standards that are necessary to ensure that software, IP, and libraries interoperate seamlessly in our customers' design and manufacturing environments. This contribution continues to demonstrate our commitment to collaboration, based on open standards, to facilitate the growth of the industry, as well as our customers' success."

Cadence Design Systems also announced that Wipro Technologies has renewed an agreement under which Cadence will provide Wipro access to Cadence's technologies. The organizations say that this agreement marks the third renewal of the Cadence-Wipro business relationship over the past eight years Cadence also announced that Wipro taped out its largest design to date using Cadence tools.

Cadence Design Systems also introduced its OrCAD Signal Explorer product. The company says that the new product includes PCB-level topology exploration and signal integrity (SI) analysis technology. Per the Press Release: "Besides enabling improved productivity, this latest addition to the high-performance, affordable OrCAD product line continues to enable easy scalability to the full range of Cadence Allegro PCB offerings. Bringing SI analysis and validation to the design process early allows designers to use circuit and PCB topology exploration to facilitate increased circuit reliability and drive known good requirements into the back end."

Then Cadence Design Systems announced new design-partitioning technology for its Allegro PCB Editor, which the company says includes design-partitioning technology to meet customer demand for "faster time to market and shorter design-cycle times by enabling concurrent collaboration for true team-based PCB design."

Read on to learn that: "The pressure to shorten design-cycle times is heightened by the growing deployment of globally dispersed design teams. With Cadence design-partitioning technology, multiple PCB designers working concurrently on a layout share access to a single database, regardless of team proximity. Designers then can partition designs into multiple sections for layout and editing by design-team members. Designers are able to view the partitioned sections and update the design view for monitoring the status and progress of other sections. This can dramatically reduce overall design cycles and accelerate the design process to help meet project schedules." So much drama, so little time.

Cadence Design Systems also announced Cadence Encounter Test Architect, which the company describes as "the industry's first full-chip test architecture development product. It includes the industry's first unified compiler-based methodology for full-chip test. The result is faster development of a higher-quality test infrastructure than is currently possible with point test tools. Based on a unique test infrastructure compiler, Encounter Test Architect supports a unified methodology for specifying, compiling, and verifying full-chip test. This includes scan, compression, memory BIST, on-product clock generation, boundary scan, and I/O test." Nice. Very nice.

Finally, Cadence Design Systems announced "customer ratification" of its low-power enhancements to Cadence Encounter CeltIC NDC (Nanometer Delay Calculator).

Noam Benayahu, Director of VLSI of Metalink, is one of the ratifiers: "At nanometer geometries, IR drop effects are getting increasingly severe. CeltIC NDC utilizing ECSM enabled us to pinpoint design regions that had potential IR drop-induced timing problems. CeltIC NDC is now an essential step in our signoff analysis since it can help avoid costly silicon failures."

Jamshed Qamar, Vice President of Engineering at Oki Semiconductor, also wants to ratify: "CeltIC NDC plugged directly into our timing signoff flow and delivered very good accuracy with respect to SPICE when accounting for both IR drop and crosstalk effects. We found its ability to perform on-the-fly path simulation a very easy and productive way to further validate our critical paths."

CAST, Inc. announced a new IP core that the company says "implements a dual-role host/device controller in conformance with the On-The-Go (OTG) supplement to the USB 2.0 specification."

Per the Press Release: "USB OTG builds on the popularity of USB (Universal Serial Bus) by making it even easier to connect digital products. Whereas USB needs a computer host to manage the connection to one or more devices (a master-slave protocol), OTG gives every device enough host capabilities so they can be directly interconnected. Users can, for example, connect their OTG-equipped camera directly to a printer for photos or to a cell phone for Internet sharing, without the use of a computer. In host mode, the new CAST USBHS-OTG-MPD core supports hi-speed hubs, and multiple low- full-, and hi-speed peripheral devices. In device mode, the core supports full-speed and hi-speed data transfers." Meanwhile, please note that "the core’s competitive hardware implementation requires just 45,000 gates and runs at 200 MHz in an 0.18-micron ASIC process."

Concept Engineering GmbH announced NlviewWX, which the company describes as "the sixth engine in a steady stream of visualization software components that already support Tcl/Tk, Java, the Microsoft Foundation Class (MFC) Library, Qt, and Perl. EDA tool developers using the wxWidget environment to build their EDA tools can now use Concept's NlviewWX engine to create high-quality, high-performance debugging graphical user interfaces (GUIs) for their EDA tools in a very short time." Good news.

Gerhard Angst, President and CEO of Concept Engineering, is quoted: "The complexity of circuits and the demand for advanced interactive debugging features can only be solved using a very advanced, high-performance visualization engine. To do this in-house might take many man-years and might still result in a solution that cannot compete with our industry-proven engine. We give EDA tool developers a visual debugging cockpit that saves them time and money, so they can concentrate on their applications."

First Silicon Solutions (FS2) and Tensilica, Inc. announced that the FS2 System Navigator is available now for debug and system integration of SoC designs with Tensilica Xtensa V and Xtensa LX configurable and extensible processors. The companies say the FS2 System Navigator architecture includes optional interfaces for FS2 Bus Navigator tools, which provide tracing and bus level analysis of OCP, AMBA, or custom bus interfaces.

Rick Leatherman, President of FS2, is quoted: "The highly configurable Xtensa processor is an ideal match for the FS2 debug tools and custom On-Chip Instrumentation (OCI). Designers can choose the FS2 off-the-shelf solution that supports all of the embedded Xtensa debug features or work with FS2 for a custom implementation. Custom solutions include additional features like heterogeneous multi-processor support and integrated bus analysis."

IMEC and CoWare have signed a "letter of intent to collaborate" on the development of an integrated design flow for efficiently mapping advanced multimedia and wireless applications on a flexible and programmable platform.

Per the Press Release: "The design flow is an integral part of IMEC's multi-mode multimedia (M4) program and will be used to develop software-defined radio and multi-format multimedia codecs. The two organizations intend to close the gap between IMEC's proprietary research tools and CoWare's electronic system-level (ESL) design tools. One of the major targets within the design technology part of the M4 program is to develop an integrated digital design flow for multi-processor based platforms which is applicable for industrial applications. IMEC has an extensive tool suite in support of this design flow and performs research on tools for the design flow that are currently not available on the market. The intended collaboration with CoWare is a first industrial partnership to complete the flow. The design flow is driven by research on future applications, such as software-defined radio and multi-format multimedia codecs. "

IMEC and CoWare say they will make the interfaces of their appropriate tools compatible with the requirements of IMEC's design flow. "Starting from a behavioral specification of the application, the application mapping flow includes three major phases: High-level platform-independent optimization starting from a single-thread system specification; Transformation of the sequential description into a concurrent multi-task model; and Platform-dependent optimization resulting in a set of concurrent tasks including communication information. The organizations feel that the result of the application mapping is a "completely configured flexible platform architecture [and that] the architecture will be further implemented by state-of-the-art hardware/software co-design tools, compilers and synthesizers."

iRoC Technologies Corp. has introduced its TFIT software, which the company describes as its "Soft Error Design Solution Platform." The software is designed to help analyze the impact of soft error strikes on custom designs in order help meet reliability targets. Soft errors are defined as "transient faults caused by external radiation – mainly cosmic rays – that affect the logic states of ICs and memories."

Per the Press Release: "Currently, TCAD/3D modeling techniques are used for SPICE level soft error analysis … to accurately model a single strike/single angle is at least an overnight run, and soft error analysis of a memory or IP block could take weeks. IN contrast, by leveraging iRoC's soft error models, TFIT can do the same simulations in seconds, and full soft error analysis of an IP block in several days … After TFIT extracts the IP block or part of the design to be analyzed, the designer selects the location where he'd like to simulate a strike, and RFIT performs analysis using the designer's test bench and iRoC's proprietary soft error models. TFIT provides the results in a table form or as a current curve displayed on the designer's SPICE simulator."

Michael Buehler-Garcia, iRoC Vice President of Worldwide Marketing and Business Development, is quoted in the Press Release: "Soft error concerns have traditionally been the purview of the military and aerospace industries because of the mission critical nature of those applications. Today, the data in commercial applications such as storage systems and network routers carry data that is also considered mission critical to end customers. This now makes soft errors a concern for memory designers, network processors designs, and IDM library development teams targeting these markets.

Macraigor Systems LLC announced the availability of its J-Scan Version 1.0 boundary-scan debug and programming tool. The company says the new technology "allows circuit designers to facilitate early test development, thereby shortening the development cycle and prototyping process."

Per the Press Release: "Unlike logic analyzers and oscilloscope probes, J-Scan permits designers to see what all the pins under a ball grid array (BGA) device are doing in real time on their PCs or laptops. The J-Scan debug and programming tool also allows designers to manually force the pins to any logic state with a simple point and click of the mouse. For the first time, users can finally see what every pin under a BGA is doing. J-Scan instantly answers questions such as: Is the oscillator connected to pin H17 under the BGA? Is the address bus active? Is the data bus being driven? Are any lines shorted? With J-Scan Version 1.0, the IC designer now has control of every pin. If the CPU is not yet available and the designer needs to program flash memory, programming is as easy as setting up the signals (address, data, enables), selecting a data file and pressing the PROGRAM button. The provided USB 2.0 download cable permits programming times of minutes, not hours. Utilities to program field-programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs) are also available." Nice.

Craig Haller, Chief Engineer at Macraigor Systems LLC, is quoted: "The best news is we have intentionally priced J-Scan at one-fifth of the competitive solution with all the same features so that every designer and technician who debugs circuit boards can have access to this powerful technology."

Mentor Graphics Corp. announced that the Fraunhofer Institute for Integrated Circuits (IIS) has selected the Mentor Graphics Catapult C Synthesis tool for use in next-generation digital broadcast applications.

Frank Mayer, Design Manager at Fraunhofer IIS, is quoted: "During our evaluation, we found Catapult C's quality of results and ease of use to be very convincing. Using the tool, we expect a 5 - 10x improvement in productivity for algorithmic blocks, compared to HDL synthesis. The Catapult C tool's ability to use pure C code as input fits very well in our design flow, allowing us to automatically generate hardware directly from our untimed C/C++ system models regardless of the target technology. Based on the success of our evaluation, we immediately deployed Catapult C in production design projects."

Mentor Graphics also announced "further integration capabilities" between CHS (Capital Harness Systems), the company's electrical design-to-build flow, and Dassault Systemes' CATIA V5 MCAD suite. The companies say that a new data bridge linking CATIA V5 with Mentor's Capital Engineer product is now available. Per the Press Release: "This new data bridge complements the recently released bridges linking CATIA V5 with Mentor's Capital Logic and Capital Integrator wiring design products. Taken together, these bridges dramatically reduce electrical system design time and errors via the integration of electrical, mechanical and harness data within a single flow."

Mentor Graphics also announced the release of the PADS2005 PCB design solutions.

Per the Press Release: "The PADS2005 update features significant enhancements that improve the designer's productivity and ability to optimize designs for performance and manufacturing. This release also extends the capabilities of PADS Logic to enable faster schematic capture, viewing and analysis by design team members and increased ease-of-use features for the full PADS flow. New features include floating connections that organize the design according to the preference of the designer, as well as automatic connection of parts-to-parts and parts-to-nets that accelerate the incorporation of new parts into the design. True Type Font support for both PADS Logic and PADS Layout, increased readability of the design screen and printed schematic. In addition, international fonts, such as Chinese characters, are supported." Pretty interesting.

Mentor Graphics also announced that Renesas Technology Corp. has completed a joint development effort that integrates the Mentor Graphics 0-In Assertion Synthesis technology and assertion-based verification flows with Renesas’ LogicBench rapid prototyping system. The companies say the cooperation results in "a solution that gives Renesas the ability to specify assertions in any format and have them used throughout the verification process, from C-based system design through FPGA prototyping. Assertions provide the ability to detect and diagnose bugs earlier and faster than traditional methods enabling design teams to reach verification closure more effectively and efficiently."

Osamu Tada, department manager of System Level Design and Verification Technology, Design Technology Division, LSI Product Technology Unit of Renesas Technology Corp., is a happy guy: "We needed an assertion-based verification method that includes simulation and formal verification to strengthen our verification solution based on LogicBench. We selected Mentor’s 0-In Assertion Synthesis technology because it provides the best solution for our target."

The Silicon Design Chain Initiative announced new design techniques that are said to achieve "total power savings of over 40 percent on a 90-nanometer test design. The low-power design employed an ARM1136JF-S test chip, ARM Artisan standard cell libraries and memories, Cadence Encounter design platform and TSMC's Reference Flow 5.0. Applied Materials, Inc., ARM, Cadence Design Systems, and TSMC form the Silicon Design Chain Initiative.

Our old friend Edward Wan, Senior Director of Design Service Marketing at TSMC, is excited: "This is the first time industry leaders have banded together to correlate real power savings into real silicon, which should dramatically increase the adoption rate for 90-nanometer technology. This project exemplifies the power of strategic collaboration to significantly differentiate our respective technology offerings."

Christopher Chun, Advanced Power Management System Architect, Freescale Semiconductor, is also excited: "Many power reduction techniques are being investigated, but most significantly increase IC costs through increased design times. For robust and practical power reduction techniques, it is critical that process developers, IC designers, and IP and tool providers collaborate to automate the methodologies."

STMicroelectronics and Siliconix Inc. (described in the Press Release as 80.4%-owned subsidiary of Vishay Intertechnology, Inc.) announced that the two companies have concluded an agreement "whereby ST will license from Siliconix a new power MOSFET packaging technology that provides superior thermal performance via top and bottom heat dissipation paths in systems using forced air cooling. Offered by Siliconix under the PolarPAK name, the new package's leadframe and plastic encapsulation are similar to those used for most standard power MOSFET packages, ensuring good die protection and easy handling in manufacturing. Yet compared with the standard SO-8, the PolarPAK package dissipates heat so efficiently that it can handle twice the current within the same footprint dimensions."

Synopsys, Inc. announced DFT Compiler MAX, which the company describes as its "next generation DFT synthesis solution, offering 1-pass test data volume compression capabilities to address design and test challenges occurring in 130-nm and smaller process technologies. DFT Compiler MAX is an extension of Synopsys' unique 1-pass test synthesis solution that delivers push-button test data volume compression of 10-50x, enabling deep submicron (DSM) testing for high fault coverage without significant impact on test costs. The solution is transparently integrated within Synopsys' Design Compiler and the entire Galaxy Design Platform to achieve best timing closure and to help eliminate costly iterations between design and test implementations by designers with minimal test expertise."

Synopsys also announced that Synopsys' coreAssembler IP integration tool supports the SPIRIT 1.0 IP packaging standard. The company says that coreAssembler is "the only tool that supports a path to implementation in silicon for SPIRIT-compliant IP in addition to system-level integration and verification. Tight integration with the Synopsys Galaxy Design Platform and Discovery Verification Platform helps to achieve superior quality-of-results and speed the time to verification. By providing production support for SPIRIT 1.0, coreAssembler now enables designers to more rapidly integrate the broad portfolio of DesignWare IP, as well as third-party IP compliant with the SPIRIT standard."

Please note that: "Synopsys is a founding member of the SPIRIT consortium, an independent organization focused on defining standards for IP packaging and reuse. The SPIRIT 1.0 specification, released in December of 2004, defines a common, XML-based format to describe IP that is targeted for automated integration techniques and enables SoC integrators to use IP from multiple sources with SPIRIT-compliant tools."

Synopsys also announced its Galaxy IC Compiler, which the company describes as "the next-generation physical design solution, endorsed by leading-edge early users including Agere Systems, ARM and STMicroelectronics. IC Compiler transcends current-generation solutions by unifying previously separate operations. It is the first-ever physical design solution which provides concurrent physical synthesis, clock tree synthesis, routing, yield optimization and sign-off correlation, delivering unmatched design performance and productivity. IC Compiler is the centerpiece of the Synopsys Galaxy Design Platform, which provides a coherent solution from RTL to silicon."

Aart de Geus, Chairman and CEO of Synopsys, is quoted: "This new architecture solves multiple design problems concurrently, bringing substantial productivity improvements in our customers’ quality of results, time to results and cost of results. Early customers are already successfully applying this new technology to their toughest problems today."

Best of Show Paragraph – "The unrelenting march of technology coupled with the dynamics of a consumer-dominated market has created a situation where results and the cost of results are both important and interdependent. This dynamic requires a systemic solution, providing consistent optimization of timing, area, power, testability and yield across the flow from RTL down to silicon. Today, the Galaxy Design Platform is the designers’ solution of choice. As technology challenges continue to multiply, leading-edge customers have collaborated with Synopsys to evolve the Galaxy Design Platform and develop IC Compiler as the key to performance and productivity in physical design."

TurboTools announced its CablEquity product, first in the company's SystemEquity tool family. TurboTools says it is the first company in the industry that introducing the next generation of engineering automation solutions that "go beyond the capabilities of traditional EDA applications. The SystemEquity is defining the new market segment for EDA tools called System CAD or SCAD. TurboTools views SCAD as an entirely new method of managing system design and manufacturing processes."

Per the Press Release: "Design of modern electro-mechanical equipment has become a complex task where competitive pressures demand rapid introduction of innovative products. To be a market leader a company has to operate quickly and efficiently reducing costs and streamlining the take to market process. The challenges are therefore to improve the speed and effectiveness of the product development process, radically reduce the time taken to create new innovative designs, and provide significant savings across every part of the design to manufacturing cycle. Early adopters of CablEquity reported numerous competitive advantages and business benefits."

X-FAB Semiconductor Foundries AG has announced a collaborative agreement with Cadence Design Systems, Inc. X-FAB says it will "work closely with Cadence to build and deliver comprehensive design kits for analog and mixed-signal ICs targeting mainstream and advanced process technologies."

Jan Willis, Senior Vice President for Industry Alliances at Cadence, is quoted: "The proliferation of consumer electronics, including wireless technology, has driven an increase in mixed-signal content within complex SoCs. To address this increased complexity, design chain collaboration is critical to produce silicon-validated reference flows and process design kits (PDKs) that ease the challenges designers are facing. The combination of jointly developed PDKs with X-FAB and our proven analog and mixed-signal solutions enables mixed-signal chip designers to integrate more functionality onto a single chip."

Hans-Juergen Straub, CEO of X-FAB Group, is also quoted: "This alliance enables engineers using the Cadence Virtuoso custom design platform to have a smooth and efficient path from design through physical implementation. Our customers will benefit with faster time to market with lower risk and shorter design cycle times."

Xilinx, Inc. announced that its Virtex-4 FX family is "rapidly gaining traction with new applications for FPGA-based embedded systems and the availability of the new ML403 development platform. Fueled by the innovative Auxiliary Processor Unit (APU) controller for the integrated dual-PowerPC processor, the Virtex-4 FX platform empowers designers to achieve up to an astounding 20X boost in overall system performance relative to traditional software only execution. This application-specific hardware acceleration approach enables designers to implement faster, more flexible programmable embedded platforms for a broader range of product applications." Nice.

Xilinx also announced version 7.1i of the Platform Studio tool suite for Platform FPGA embedded processing design. This new is aimed at the company's Virtex-4 FX family. Per the Press Release: "The 7.1i release incorporates a variety of usability enhancements and new features never before available for Platform FPGA design that further simplify, abstract and accelerate embedded system development … [including] system profiling and analysis tools to help optimize performance and target design functions for acceleration in FPGA hardware."

Meanwhile, Xilinx and AccelChip Inc. announced the immediate availability of a new interface between AccelChip DSP Synthesis and Xilinx System Generator for DSP tools which "enables rapid development of high performance DSP and communications systems. Jointly developed by Xilinx and AccelChip, this new interface enables designs captured in The MathWorks’ MATLAB language to be rapidly incorporated into System Generator designs for implementation and verification. System Generator for DSP is the framework for developing and debugging high performance DSP systems for Xilinx’s advanced FPGAs. System Generator, together with The MathWorks’ Simulink tool, provides the graphical design environment commonly used by system architects and hardware designers."

Ken Karnofsky, Marketing Director for Signal Processing and Communications at The MathWorks, is quoted: "Many of The MathWorks’ customers use a combination of MATLAB for algorithm development and Simulink for system-level design and integration. MATLAB is an intuitive language and technical computing environment with advanced data analysis and visualization for algorithm development. Simulink with System Generator for DSP is an outstanding simulation and prototyping environment. Through the efforts of AccelChip and Xilinx, DSP design teams can now leverage the strengths of each environment."

Virtio Corp. says it has released a software development model for the Texas Instruments’ (TI) TMS320DA295 portable audio playback processor. The VPDA295 Virtual Platform, which features fast, full-function emulation of TI's recently introduced device, provides developers with the ability to develop and test their software without waiting for hardware availability. In addition, the VPDA295 platform gives developers insight into and control of software execution that are impossible on the hardware platform. TI engineers, who used the platform in developing the evaluation board support software for the device, have validated the accuracy of the VPDA295 platform.

TI’s Portable Audio and Infotainment business manager Chris Schairbaum, addressed the conundrum of hardware/software co-design: "We had to begin testing software before the device even entered tape-out. The Virtual Platform was invaluable in helping us get the software ready in time for the hardware release."

Virtio Corp. also announced support of the Texas Instruments (TI) OMAP family, the VPOM-V1030 Virtual Platform.

Filip Thoen, CTO for Virtio, was overheard: "With the release of the VPOM-V1030, we are expanding our focus to support modem development along with OS and application software. Modem development is like a black art and requires lots of low-level tweaking. The Virtual Platform provides developers with full access to processor and hardware registers to simplify debugging."

ZAiQ Technologies, Inc. and ProDesign Electronics Corp. announced that ZAiQ's SYSTEMware verification software and IP and ProDesign’s CHIPit Systems will be integrated to produce a transaction-based verification platform.

Heiko Mauersberger, ProDesign's CTO is quoted: "By combining the transaction based verification capabilities of Zaiq’s SYSTEMware with the leading performance and visibility features from ProDesign, customers will have a compact solution for high performance verification. ZAiQ's SYSTEMware and synthesizable standards-based verification IP and ProDesign’s CHIPit family provides the flexibility and speed of reconfigurable or targeted hardware along with a common easy to use verification environment."

Rich McAndrew, Executive Vice President and GM of ZAiQ's SYSTEMware Products Group, is also quoted: "True electronic system level (ESL) verification requires a transaction based approach which is Retargetable from simulation to emulation. By tightly integrating the transactors and retargetability features in SYSTEMware with the performance of the CHIPit family through the SCE-MI 1.0 interface, customers will have an easy to use, high performance, verification system which can be used for simulation acceleration, emulation or silicon virtual prototyping."

Zuken announced that TopSPICE is now available as a simulation engine for the CADSTAR suite of schematic and printed circuit board (PCB) design tools.

Per the Press Release: "TopSPICE, from Penzar Development, enables design engineers to simulate their schematic exactly as it will be passed into PCB layout. The integration between CADSTAR and TopSPICE, which has been developed in partnership with LatimerCAD, means that CADSTAR users no longer have to copy data from schematic to simulation, but instead work within a single design environment, utilizing a seamless design flow based around a single set of data. All design and simulation functions are available from either the schematic or netlist editor front-ends, reducing design time and significantly boosts productivity. The TopSPICE simulation engine includes a native mixed-mode, mixed-signal simulator for circuits with any combination of analog and digital functions; and works with most PSpice net lists and vendor SPICE model libraries."

"Smart devices and fast networks are changing the landscape of industry and our world. The fine hand-eye coordination of an industrial robot, the clockwork precision of a national railway, the mission-critical control system of a battleship, air traffic control over a major city, each of these applications depends on the connectivity and cooperation of many independent devices. In all of these applications Real-Time Innovations’ data-critical networking software provides seamless communication between independent devices, tying them into a logical and manageable whole. Such real-time networked devices are solving problems and delivering services single computers cannot handle. To build these complex systems, developers need increasingly sophisticated and powerful tools to help them visualize, analyze and debug intricate platforms. "

"Today, RTI announced the first comprehensive suite of tools that enable developers to configure, monitor and control the network. RTI’s open-architecture platform, NDDS, the basis of the Object Management Group's (OMG) Data Distribution Service (DDS) standard, offers a rich set of publish-subscribe middleware that is a compelling solution with its fully integrated tools for system visualization, analysis and real-time debugging. Now network developers have tools for DDS-based applications that will greatly simplify the design, ease development and improve the quality of applications in simulation, telecommunications, industrial automation, medical equipment, factory automation and avionics. The industry’s first fully integrated system-visualization tools for distributed systems will allow OEMs to focus on what they do best-innovative design that maximizes their return on investment. The NDDS developer tools provide informative views into the system to better understand and manage distributed application complexity. System tools enable developers to visualize network connections and understand, configure and optimize network parameters. The network tools analyze protocols and help developers understand and tune bandwidth parameters. Application tools show how the application is using the network. "