The Design-for-Debug Consortium (DFD) met at DAC to initiate what member companies hope will be an industry-wide discussion of silicon debug challenges and a collaborative approach for defining DFD solutions. There was a lot of enthusiasm at the opening meeting on Monday, June 13th, and my impression would be that something substantive will emerge from the commitment and effort of the members to make the consortium a functioning, contributing player in the industry.

Here are some details per the Press Release: "The DFD Consortium is initially focused on mobilizing a representative cross-section of the industry to raise awareness and create a forum in which tool interoperability and methodology issues can be identified and investigated. The DFD Consortium will also identify data and file format standards required to simplify and accelerate the functional debug of chips mounted in silicon prototypes or systems (referred to as "in situ"). These efforts are all targeted at providing both DFD users and solution providers with a better understanding of product requirements and practical roadmap for adopting design guidelines.

Charter members include: Corelis, Inc.; DAFCA, Inc.; First Silicon Solutions (FS2); Intellitech Corp.; JTAG Technologies; Fidel Muradali (consultant) and Novas Software, Inc.

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The Open SystemC Initiative (OSCI) announced that it has officially transferred the Language Reference Manual (LRM) for SystemC 2.1 to the IEEE for further standardization.

Per the Press Release: "The LRM is the definitive description of SystemC 2.1. The purpose of the standard is to provide a precise and complete specification of the SystemC library so that implementations can be developed with reference to the SystemC standard alone … The SystemC 2.1 LRM defines the public interface to the SystemC class library and defines constraints on how those classes may be used. It provides an unambiguous definition of what is required to accurately implement SystemC tools. "

OSCI Chairman Alain Clouard is quoted: "The beginning of the IEEE standardization of SystemC with the release to the IEEE of the LRM, which was recently approved as OSCI-level standard by the OSCI Board, is a great milestone for OSCI. The development of a document that adequately defines the syntax and semantics of any language is notoriously difficult. We would like to recognize the dedication of our members to this effort and Doulos Ltd. for their significant contribution writing this document."

Victor Berman, Chairman of the P1666 WG at IEEE says his technical team has worked closely with OSCI during the development of the LRM and that its contents have been incorporated into the draft standard proposal already. "Balloting of the standard is scheduled to begin shortly following the final approval of the document by the working group at a meeting to be held on June 15 in Anaheim during the Design Automation Conference. The proposed standard is following the fast track procedures of the IEEE, which could allow for standardization in a matter of months. The final draft of the SystemC 2.1 LRM has been under review for several months, and I don't anticipate that major changes will be required."

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* Applied Wave Research, Inc. (AWR) announced the release of a code division multiple-access 2000 (cdma2000) testbench for the company’s Visual System Simulator (VSS) design suite. The company says the new testbench is designed for RF system engineers who need to evaluate the impact of RF link impairments on frame error rate (FER), bit error rate (BER), symbol error rate (SER), and other metrics.

Joel Kirshman, AWR Market Segment Manager for System Simulation, is quoted: "The VSS cdma2000 test bench is the latest software innovation in AWR’s continuing commitment to provide engineers with effective, easy-to-use, integrated tools for the generation of the complex modulated signals needed to design next-generation communications products."

* Denali announced that Atheros Communications, Inc. selected Denali’s PureSpec verification IP products.

David Lin, Denali’s vice president of Product Marketing, is pleased: "We are seeing this same level of customer acceptance in our PureSpec products for Ethernet and USB. Atheros has implemented a leading-edge design and verification environment that enables them to bring to market high-quality products quickly. We are pleased to have them as a customer, and we are committed to their continued success."

* Atrenta Inc. introduced its 1Team:Embedded C and C++ analysis environment for embedded software. The company says 1Team:Embedded "helps ensure that embedded software is designed correctly from the start: free of coding hazards, compliant with industry-standard and company-specific best practices and coded for optimal portability and reuse … 1Team:Embedded uses sophisticated module- and system-level analysis to quickly identify and avoid potential problems, maintain code integrity, enforce best practices and apply company-specific coding standards. In addition to semantic and syntactic checks, it examines the overall software architecture, the coding practices and functional implications, including impacts on performance, platform-independence, maintenance and reuse. In so doing, 1Team:Embedded complements and extends conventional debugging tools."

Hopefully Atrenta will take a look at the new DFD Consortium nonetheless.

Bernard Murphy, CTO at Atrenta, is quoted: "Embedded software is an enormous and increasing challenge in electronic system development. Its complexity is outpacing that of the hardware itself, and its impact on schedules and budgets is growing. Yet until now there were no tools to thoroughly analyze and validate embedded C and C++ code. 1Team:Embedded fills that gap. It dramatically reduces the need for late-stage reworking and results in better embedded software: more robust, better-performing, more reliable, portable and reusable."

* Atrenta Inc. also introduced 1Team:System and 1Team:Embedded, assist system hardware and embedded software development, respectively. 1Team:System provides an analysis environment for validating and optimizing SystemC hardware designs; 1Team:Embedded does the same for C and C++ embedded software designs.

Ajoy Bose, CEO of Atrenta, is quoted in the Press Release: "ESL offers a way to master the growing complexity of systems, by creating designs at a higher level of abstraction. But ESL has its own complexity challenges, and new tools are needed to assist designers and accelerate ESL-based development. This includes not only system hardware, but also embedded software development, which is often overlooked in our EDA-centric industry. They’re both critical pieces. 1Team:System and 1Team:Embedded are the first in a new generation of solutions that will do for ESL what EDA has done for IC development."

* Bluespec Inc. announced it has added low-power ESL synthesis with integrated clock and power management and formal clock verification capabilities to its ESL synthesis EDA toolset. The company says it has added "integrated clock management and formal clock connectivity verification to enhance its multiple clock domain (MCD) support. By incorporating clocking into its semantic model, Bluespec’s toolset simplifies complex clock topology implementations and ensures that mis-connections are caught at the time of synthesis."

Technical reasoning per the Press Release: "As SoCs continue to become larger and faster, gated clocks and multiple clock domains are increasingly used to manage power, to support multiple, varied communication interfaces, and to re-use older IP, that can demand different clock requirements. Interconnection among these different clock domains has become difficult to manage and prone to error, as most commercially available verification tools do not guarantee correct implementation to handle metastability. As a result, synchronization issues are sometimes not discovered until the chip is manufactured into silicon – adding significant delays and costs to the design of the chip. In addition, implementing and managing control logic around clock gating for power management is burdensome and contributes to design errors."

Sathyam Pattanam, Vice President of Engineering at Bluespec, is quoted: "We are one of the few companies addressing the increasing challenges presented by MCDs – and have taken the lead in the high-level synthesis space by delivering the first tool with integrated clock management and verification to minimize their costs. Bluespec is tightly integrated with existing tools and methodologies, and, more importantly, with the complex design needs of engineers, who cannot afford to compromise in results as well as capabilities."

* Cadence Design Systems, Inc. announced that Nethra Imaging taped out its first product, the NI-2050 image processor designed for mobile handset applications, using Cadence's Encounter RTL Compiler synthesis.

Ravi Bhatnagar, Senior Vice President of Engineering at Nethra, is quoted: "Our engineers have found the tool to be fast and powerful. The synthesis results were up to our expectation, and it helped us save power and area. RTL Compiler, along with other tools in the flow, helped us achieve first-time working silicon."

* Cadence Design Systems also announced that Essence Technology taped out a design with Cadence's Encounter RTL Compiler.

Jeremy Lee, Vice President of Essence, is quoted: "Encounter RTL Compiler's global optimization was key in our ability to save 30 percent of the design's synthesizable area, which lead to an overall die-size reduction. This, combined with the capacity and performance advantages, helped us achieve the excellent design results in less time."

* Cadence Design Systems also announced it has ported the Encounter digital IC design platform onto the 64-bit Intel Xeon processor-based systems with Linux. The company says that Encounter RTL Compiler synthesis and SoC Encounter Global Physical Synthesis (GPS) RTL-to-GDSII both now include support for this port, and have other additional features as well.

Guru Bhatia, IT Engineering Computing Director at Intel, says they're excited: "We are excited to see the support of the Cadence Encounter platform for 64-bit Intel Xeon processor-based systems delivering world-class computing performance."

* Cadence Design Systems also announced that Agere Systems chose the Palladium II accelerator/emulator system to "verify and launch its TrueAdvantage converged access solutions." The companies said that Agere was able to begin the verification of the hardware and software up to three months earlier in the design process, and that the verification environment for the TrueAdvantage was up and running within 2 weeks from the outset – including third-party IP, the operating system and external debuggers, and connections to external networking-test sets such as Bit-gate and Adtech.

* Cadence's new Verification Division outlined its strategy for its enterprise Verification Process Automation (VPA) "strategy," which results from Cadence's acquisition of Verisity. The company says the VPA strategy "will manage and link design and verification specialists and offer users an optimal blend of e, SystemVerilog and SystemC languages. The strategy mirrors market-tested approaches established by leading enterprise software companies such as SAP and Oracle."

Cadence says it will develop a "layered set of verification capabilities optimized for various market segments. Each layer will include unique process-automation capabilities that link and manage the activities of multiple design and verification specialists from plan to closure across block, chip and system levels."

Ari Cohen, Vice President of Hardware Engineering and Operations at Silverback Systems, endorses the move: "With the recent acquisition of Verisity, Cadence will now offer enterprise-level verification solutions based on a comprehensive methodology. Ever-increasing complexities combined with shrinking schedules and spec changes are forcing us to automate the entire process. Cadence delivers the foundation we need today while setting the stage for tomorrow."

Moshe Gavrielov, Executive Vice President of the new Cadence Verification Division, is also quoted: "Cadence understands that market pressures brought on by complexity require new ways of thinking. Typically in EDA, we get caught up at the technology level and tend to lose sight of how to apply it and fundamentally improve the way we do things. The growth of the enterprise business-software market proves that broadening your view beyond databases and software for functional silos can create tremendous value for the customer and accelerate growth within an industry."

* Cadence also announced that a new design production flow from Japan's Semiconductor Technology Academic Research Center (STARC) developed using Cadence technology delivered "50 percent reduction in power consumption on designs. The STARCAD-21 Cadence Flow Version 2.0 is the first production flow based on Cadence Encounter 4.2 digital technology."

* Then Cadence announced in conjunction with Virage Logic Corp. announced that the Encounter low-power digital IC design flow "now supports power saving features of Virage Logic's IPrima Mobile Semiconductor IP Platform's Ultra-Low-Power (ULP) standard cell library."

Brani Buric, Senior Director of Business Development and Platform Product Marketing at Virage Logic, is quoted: "Encounter is the first routing technology to demonstrate the Virage Logic IPrima Mobile Platform ULP cell library low-power offset biasing options. Although offset biasing is not new to the industry in terms of providing leakage power savings, this proven methodology is unique in addressing biasing capabilities at the SoC design level."

* CoWare Inc. introduced its CORXpert technology, which the company says is a new part of its LISATek product family, that automates the path for software developers "to develop custom instructions to improve processor performance, creating differentiated products. With CORXpert Personality Kits for a particular processor software developers can develop and explore instructions to improve processor performance for a target application without impacting their time-to-market goals."

"High-quality RTL synthesis together with ready to run synthesis scripts allows a direct implementation path, without waiting to hand the design over to the hardware development team.

This means there is no risk of misinterpretation of a paper specification. Generation of the instruction documentation that is consistent with the ISS models and RTL provides an easy way

to communicate the new instructions to other software developers. And with these consistent

models, verification time is reduced drastically compared to manual methods."

AK Kalekos, Vice President of Marketing and Business Development for CoWare, is quoted: "Increasingly, designers are looking at software-driven differentiation. But, by putting all the differentiation in software, they may be compromising product performance. By offering a fast and easy way to extend the processor's instruction set with user defined instructions that optimize specific application-software performance, we enable custom-hardware performance and the programmability benefits of software. It's the best of both worlds."

* Gideon Intrater, Vice President of Solutions Architecture at MIPS, is quoted: "CoWare's electronic system-level technology will enable our customers to more easily take advantage of the powerful and flexible CorExtend capability without manual implementation. In today's cost and time-sensitive markets, product differentiation is essential. We are pleased with this new technology that allows customers to leverage their application expertise by developing custom instructions for our MIPS processors, making their product more competitive in the market."

* CoWare also announced, in conjunction with MIPS Technologies, Inc., that CoWare has created its first CoWare CORXpert Personality Kit for the MIPS32 24K Pro Series cores. With this product, CoWare provides customers with a tool to optimize user-defined instructions for MIPS processors.

Meanwhile, CoWare Inc. announced "its commitment" to support the newly released SystemC 2.1 language reference manual (LRM) as it becomes standardized by IEEE P1666. CoWare says it will deliver initial support in two steps. The latest releases of CoWare's ConvergenSC Model Library and CoWare's SystemC IP creation tools, including LISATek and SPW, provide SystemC models that are compliant with the proposed LRM today. These models, and any models or designs created to early SystemC 2.1 specifications from the Open SystemC Initiative (OSCI), can be used immediately in the latest release of CoWare's ConvergenSC SystemC toolset.

Secondly, ConvergenSC tools will be updated to take advantage of minor C++ implementation changes recommended by the proposed LRM. CoWare will support these changes in the next release of the ConvergenSC tools, which are otherwise compliant with the LRM now. CoWare will track the formal IEEE standardization process to ensure each new tool and IP model library release complies with the IEEE standard.

* CoWare Inc. also announced a collaboration with PMC-Sierra, Inc. to provide an ESL design solution for customers designing products based on PMC Sierra's RM7900 family of MIPS-Powered processors.

Per the Press Release: "The solution consists of a processor support package for CoWare's ConvergenSC(r) design environment based on an RM7900 SystemC transaction-level model for the processor. The inclusion of the RM7900 model in the ConvergenSC Model Library—the industry's largest model library for SystemC—extends the freedom of choice for processor IP demanded by today's systems architects. The SystemC-based solution provides a significant reduction in overall design time by enabling designers to validate a design's hardware architecture concurrently with embedded software--much earlier than with previous design methods."

* Forte Design Systems announced that Seiko Epson Corp. (Epson) has chosen Forte's Cynthesizer behavioral synthesis product to design its next generation image processing applications.

Akinari Todoroki, General Manager of the Information and Communications Technology Communications Device R&D Development Division at Seiko Epson Corporation Research and Development Center (does that actually fit on a business card?), is quoted: "Conventional design methods can not utilize design results of algorithm verification at the C language level forcing RTL designers to hand-coded their hardware. We have now confirmed that we obtain consistent quality of results at the C language level and the hardware (RTL) design by incorporating Forte's Cynthesizer into our system-level development process. We have chosen Cynthesizer for the design projects in our division and are aiming for significant reduction in SoCs development time by designing IP reusable in other projects and deriving projects."

* Gradient Design Automation, Inc. has introduced its FireBolt core thermal analysis engine that the company says "enables temperature awareness in industry-standard physical design tools that analyze leakage power, voltage (IR) drop, electromigration, and timing of chips for portable devices, high-end graphics processors, automotive electronics, and memories such as DRAM and Flash."

FireBolt provides a 3-D full-chip temperature map to account for the electrical effects of thermal gradients within a semiconductor. It can capture 3-D full-chip temperature variations, locate maximum temperature differences on the die due to device self-heating, provide leakage power analysis using computed temperatures of the devices, calculate metal temperatures due to wire self-heating (useful for accurate electromigration rule checking), provide a list of devices and their locations based on temperature, provide a list of metal and interconnect temperatures, and provide "contour maps" for temperatures to help in hotspot removal.

Rajit Chandra, Gradient Founder, President and CEO, is quoted: "Thermal challenges arise from dynamic variability of chip parameters during the operation of a chip, and need to be made predictable and manageable like other DFM issues. However, the temperature of a chip is deterministic for a given power density distribution; it does not make sense to take statistical approaches, as they can lead to over worst-casing and can mask real problems."

* Gradient Design Automation also announced the creation of a design flow to integrate Gradient’s FireBolt thermal analysis engine into Cadence Design System's Encounter design platform. The companies say the integration brings "temperature awareness" into the Encounter digital implementation tools.

Per the Press Release: " Customers using the integrated solution will be able to use Gradient’s thermal analysis and repair engine at various levels of abstraction during the physical design of a semiconductor. For example, floorplanning tools will use temperature results to place the blocks for least, or optimal thermal gradients; the power rail and clock signal will be analyzed for IR drop, electromigration, and delays, respectively. The thermal analysis function within the place and route tool will query cell moves that minimize the temperature gradients within the chip. At the final routing stages, temperature data will be used for final analysis and sign off. Appropriate repair techniques will be used at each level for optimizing the thermal gradients. After the final routing and temperature-aware timing analysis is completed, if there are any more hot spots, FireBolt will use thermal structures to further minimize temperature gradients, and the flow will then be completed with the optimal temperature distribution for the given design and package parameters."

Eric Filseth, Vice president of Marketing at Cadence, is quoted: "Temperature behavior has become a significant concern for designers at 65 nanometers. The need to analyze and repair critical problems caused by the effects of temperature within a chip plays an important role in achieving timing and power closure in next-generation design flows. Timing margins in particular can be minimized when temperature effects are accurately taken into account."

* IBM, Intel Corp. and Synopsys Inc. announced a "mobile-aware" technology initiative that the companies say will "bring mobile design tools to the EDA market segment, [which are] aimed at increasing the productivity and flexibility of design engineers." As part of the initiative, Synopsys will execute a technology and market assessment of "mobile-aware" design applications with selected customers and with support from Intel and IBM. Following the assessment phase, Synopsys will introduce "mobile-aware" EDA applications for Intel Centrino mobile technology-based platforms.

Raul Camposano, CTO at Synopsys, is quoted: "By developing applications that utilize the strengths of Intel Centrino mobile technology and IBM's ThinkPad notebooks, Synopsys is embracing the latest technological advances in order to enhance the productivity of our customers."

Guru Bhatia, IT engineering computing director at Intel, in quoted: "Intel developers are currently using Intel Centrino mobile technology-based platforms for engineering and product development. An Intel pilot study shows more than a 10 percent productivity increase for design engineers on Intel Centrino mobile technology-based workstations in connected mode alone, and estimates higher productivity with connected and unconnected modes when all EDA applications are made mobile aware."

Dale Hoffman, Director of Business Development and CTO at IBM's Engineering Technology and Services division, is also quoted: "As engineers face intense time-to-market pressure, battle to hold development costs within budget, and still optimize their products' functionality, they need a radical change in the way they manage the design chain, especially in the realm of nanometer design. IBM will address these critical requirements through the deployment of solutions like the Mobile Engineering Workstation and our Integrated Electronic Design Environment (IEDE). We will demo our IBM IEDE Methodology Guide, which allows users to navigate the tools and best practices needed to design a chip, on a Synopsys Design Compiler flow at the Intel booth."

* Ignios Ltd. announced an ESL model that demonstrates "the seamless integration of multiple ARC family 600 cores, using Ignios’ SystemWeaver multicore-enabling technology. The multicore SoC demonstration is based on 32 processors from the ARC 600 core family integrated with the SystemWeaver multicore-management IP core, which enables a high-level approach to software development for multicore SoC implementations. The demonstration shows that code which uses the SystemWeaver multi-threaded API can be easily developed for a single ARC processor and then simply re-targeted to a multicore implementation, with no need to recompile the source code. The SystemWeaver IP core provides the flexible run-time management resources to coordinate the multiple processors to ensure that the system achieves efficient performance and power results. SystemWeaver also provides non-intrusive access to trace information to enhance system-level debug for multicore configurations."

Karl Auker, Director of Strategic Alliances at ARC, is quoted: "An increasing number of ARC customers are implementing multiple cores on SoCs targeted at compute-intensive applications. By working with partners such as Ignios, ARC’s licensees will have access to technologies that can ease the process of multicore software development and debug. We are pleased with the work that Ignios has done in building this demonstration."

* Innovative Semiconductors announced availability of working samples of its third-generation USB 2.0 On-The-Go PHY IP, iPhy. Per the company, "iPhy is designed for cost effective, reliable, low-power USB connections with personal computers and portable electronics devices including digital still cameras, digital video cameras, MP3 and personal media players, mass storage devices, thumb drives and more. "

"Our cores are found in tens of millions of chips today, and we continue to improve our technology to enable consumer electronics manufacturers to go to market with superior performing products quickly and easily," sayeth Nabil Takla, President and CEO for Innovative Semiconductor. "With iPhy, we’ve taken our USB 2.0 PHY technology and made it smaller, higher performing and lower power for smaller form factor portable devices."

* MatrixOne, Inc. announced a series of prepackaged PLM tools, the MatrixOne Semiconductor Accelerators for Enterprise Project Management and Design-to-Manufacturing. The company says these products are "tailored to meet the specific needs of IC product development to speed time to market for new designs."

Also per the Press Release: "As the industry moves to 65-nanometer semiconductor process technology and beyond, designers face numerous simultaneous challenges, as they are pressured to introduce an ever-increasing number of new products with an abundance of advances in functionality, while lowering costs and reducing staffing levels. At the same time, increased global competition to bring winning designs to market has dramatically shortened the timeframe for new chips and products to be completed and released. These new offerings, combined with MatrixOne’s semiconductor industry-leading solutions for Design Data Management and IP Reuse and Distribution provide the semiconductor industry, for the first time, with an integrated environment to deliver new product to market from concept to silicon."

John Fleming, Senior Vice President and General Manager of the Electronics Business Unit at MatrixOne, is quoted: "With these new industry solutions, our customers can manage, in a single environment, all of their product development activities from concept to launch, while improving communication and collaboration between system design, test, and manufacturing engineers. As a result, semiconductor companies may realize reduced design iterations and cycle times, increasing the likelihood that products may be delivered on schedule and on budget to meet market share and margin targets."

* MoSys, Inc. announced availability of its 1T-SRAM "Classic Memory Macros", which the company describes as "a family of pre-configured, high density, high speed, low power memory macros using silicon-proven 0.13-micron cores. By offering this set of macros in addition to its custom-designed embedded memory products, MoSys' customers now have the advantage of off-the-shelf, silicon-proven 1T-SRAM memory for rapid integration of high-density embedded memory into their SoC designs."

* MoSys also announced availability of its 1T-SRAM memory compiler for standard 0.13-micron CMOS logic processes. The company says the compiler targets processes from TSMC, Chartered, SMIC and UMC. The MoSys memory compiler is a web-accessible tool that generates a variety of design scenarios for MoSys' 1T-SRAM memory.

* Panasonic and Ansoft Corp. announced the release of a new device library for Nexxim and Ansoft Designer, which the companies say is based on Panasonic's high-density miniaturized surface-mount technology (SMT) components.

Per the Press Release: "Engineers designing electronic equipment, such as cellular handsets, car navigation systems, and Wireless Local Area Networks (WLANs), can now design large-scale PCBs with accurate electrical models for these high-performance parts … Panasonic SMT components are offered in both equivalent circuit and S-parameter form and can be used in Nexxim and Ansoft Designer "

* Photron Technologies Ltd. and AccelChip Inc. announced an FPGA implementation of a patented digital filter for wireless data transmission rates of 100bps/Hz. The companies say the devices will be the core of a new technology called Ultra Spectral Modulation (USM), which was developed by Photron. The USM technology provides wireless data transmission rates of 5Mbs through a narrow 50Kz channel. Current technologies require channel bandwidths that are 25x larger.

The key to achieving the FPGA hardware implementation solution in a short period of time required software and hardware expertise. The design flow was comprised of MATLAB simulation software and AccelChip DSP Synthesis and AccelWare DSP IP Core Generators. These software combinations, coupled with FPGA development hardware and software, allowed the respective engineering teams to reduce the hardware development time to one-third the time of a traditional approach.

Per the Press Release: "Completion of the FPGA implementation of the hardware confirmed the efficiency of the MATLAB simulation and now brings the reality of USM and T3 data rates on a wireless basis one-step closer to market. The final phase of design work will retarget the FPGA into an ASIC.

Dale Kluesing, CTO at Photron Technologies, is quoted: "AccelChip was an important contributing factor to the success of this FPGA implementation. Our initial design was a very traditional textbook approach; however, with the AccelChip tools, we were able to explore many options and still complete the design in only a few short months."

Vin Ratford, President and CEO at AccelChip, is quoted as well: "With the growing importance in getting products to market faster, anything a company can do to decrease its design time will have an impact on the bottom line. Our products can improve design productivity up to 20x by shortening the time between algorithm development and silicon implementation. We’re proud to have contributed to the success of this significant step forward in wireless communications."

* Poseidon Design Systems announced the adaptation of its Triton Tool suite for compatibility with the Xilinx ISE tool flow to enable Virtex-4 FX FPGA designers using the Auxiliary Processor Unit (APU) controller to automatically generate hardware accelerator modules.

Per the Press Release: "By making the Triton tools complimentary to the ISE tool flow, Poseidon has streamlined the identification of system performance bottlenecks and the mechanics of partitioning and implementing hardware acceleration co-processors that utilize the APU controller. The APU controller provides a flexible high-bandwidth interface between the reconfigurable logic in the FPGA fabric and the instruction pipeline of the integrated IBM PowerPC 405 CPU. Fabric co-processor modules (FCMs) implemented in the FPGA fabric connects to the embedded PowerPC processor through the APU controller interface to act as user-defined hardware accelerators. These hardware accelerators operate as extensions to the PowerPC 405, thereby enabling the offloading of the CPU from demanding computational tasks."

* Pulsic announced that Hynix Semiconductor Inc. has increased the use of the Lyric P&R platform.

S.K.Hong, CIO and Vice President of Hynix, is quoted: "We have been looking for the solution to reduce turnaround time for our memory design. Initially, using a select number of production designs we investigated the usefulness of Pulsic software. We have been very pleased with the results, and we now plan to extend the deployment to a larger part of our design community; in our quest for faster time to market."

* Synopsys, Inc. announced the integration of the Synopsys Galaxy Design Platform into the latest Semiconductor Technology Academic Research Center (STARC) STARCAD-21 Synopsys-based production flow Version 2.0, offering a complete RTL-to-GDSII solution for low power design. The STARC production flow includes Synopsys technologies for ultra low power design. Used in a flow through a 90-nanometer test SoC, STARC demonstrated a 50 percent power savings utilizing advanced low power design techniques enabled by the Galaxy-based production flow.

Nobuyuki Nishiguchi, Senior Manager in the Design Methodology Group at STARC, is quoted: "Our customers demand a world-class low power design environment, which is why we have continued to partner with Synopsys in the development of our STARCAD-21 Synopsys-based production flow Version 2.0. The Synopsys Galaxy Design Platform offers a highly advanced, low-power portfolio in a fully automated flow delivering the best combination of lowest power and highest performance for our design. We are impressed by the fast convergence and consistent quality of results that Galaxy provides for the most demanding low-power designs."

* Synopsys, Inc. announced that ARM, TMSC, Virage Logic, and Library Technologies support of Synopsys open source Liberty Composite Current Source (CCS) models in their IP for semiconductor design.

Neal Carney, Vice President of Marketing for Physical IP at ARM, is quoted: "ARM provides Liberty models for its products supporting a large number of semiconductor foundries and processes, and has enhanced its characterization infrastructure to generate Liberty CCS models. These models enable higher accuracy and more efficient voltage scaling capabilities in support of advanced process demands and new design styles, like the ARM Intelligent Energy Manager (IEM) technology. CCS models for the ARM Artisan SAGE-X standard cell library on TSMC's 90-nanometer GT process are immediately available for download to beta customers."

Edward Wan, Senior Director of Design Service Marketing at TSMC, is also quoted: "Our evaluation of CCS does show this technique is more accurate in dealing with Miller capacitance and interconnect effects. Our library team is working closely with Synopsys to improve and take advantage of this technology, to enhance design quality and accelerate implementation and sign-off."

Brani Buric, Senior Director of Business Development and Platform Product Marketing at Virage Logic, is also quoted: "We are pleased to collaborate with Synopsys to provide integrated solutions to our mutual customers to address the complex features of nanometer designs and will have CCS-enabled 90-nm libraries available starting in the third quarter of this year."

Finally, Mehmet Cirit, who is CEO at Library Technologies, speaks: "We are very pleased to partner with Synopsys to support the Liberty open source CCS model because it enables highly accurate models to within two percent of HSPICE without increasing characterization runtime. Our library characterization solution LibChar has already been updated to support full set of CCS features."

* Synplicity Inc. and Xilinx, Inc. announced optimizations to Synplicity's Synplify Pro software that are designed to help designers efficiently implement DSP functions into Xilinx Virtex-4 FPGA devices. For example, per the Press Release: "FIR filters can be inferred and implemented to operate at 500MHz using Synplify Pro. Through its knowledge of the Virtex-4 device architecture, the Synplify Pro software allows users to take advantage of the many different operating modes of the device family's DSP48 blocks by automatically implementing the XtremeDSP structures as selected by the designer and exclusive capability to cascade multiple DSP blocks."

Jerry Banks, Director of Business Development and Strategic DSP alliances at Xilinx, is quoted: "Designers can achieve optimal DSP implementations using Synplify Pro 8.1 software, latest optimizations are the result of our strong ongoing partnership with Synplicity. Through our relationship, Synplicity has been provided with unique knowledge of our devices in order to deliver synthesis tools that allow our mutual customers to realize the best results possible."

* Zuken announces its new high-speed design solution, CR-5000 Lightning, that the company says will help with increased electronics design complexity resulting from the growth in density, miniaturization and multi-functionality of products. The product results from R&D in Japan, the UK, and Germany, and combines PCB designs and simulation. The IDE includes CR-5000 Board Designer and CR-5000 System Designer and allows users to share information through a unified database directly within the high-speed design environment. The tool is designed to help with trading off signal integrity parameters such as crosstalk, timing or EMI requirements, against mechanical and thermal constraints. Included are: unified constraints; process-orientated unification; a unified analysis engine; frontloaded verification; and the ability to develop multiboards.

Per the Press Release: "Using design methods that rely on conventional know-how and partial optimization are no longer feasible for the latest high-speed designs. The growth in the adoption of this advanced technology mandates deeper integration and a single design environment that has the ability to predict the behavior of PCBs in terms of signal integrity and EMC."