There will be a Pop Quiz on all of this next week ...

** Agilent Technologies Inc. announced what the company describes as two major advances in the integration of the CST Microwave Studio (CST MWS) simulation tool with Agilent’s Advanced Design System (ADS) EDA software. The companies say the integration "helps RF and microwave designers improve passive circuit performance and increase confidence that manufactured products will perform optimally. [In addition], these advances are implemented in the latest version of CST MWS as a direct result of the alliance and technical collaboration between Agilent and CST announced in June 2004."

** Cadence Design Systems, Inc. announced the release of the Incisive Formal Verifier, which the company says extends "the power of formal analysis to designers’ desktops. Combined with Cadence simulation, acceleration and emulation technologies, the Incisive Formal Verifier enables designers to improve the productivity and quality of functional verification earlier in the design and verification process. Customers can reduce production schedules significantly because design engineers can begin verification as they are designing the chip."

Incisive Formal Verifier employs the same set of assertions supported across the entire Incisive platform. Incisive Formal Verifier supports Verilog, SystemVerilog, VHDL and mixed-language environments, with assertions written in PSL and SVA, or using OVL and the Incisive Assertion Library. A various formal engines are provided, along with automatic assertion extraction, formal coverage metrics, and assorted debug features.

This Press Release offers a thumbnail sketch of formal verification: "An integral part of the Incisive verification platform’s assertion-based verification (ABV) offering, formal analysis does not require a set of test vectors, which means functional bugs can be detected months before testbench development and simulation. Incorporating Formal Verifier into verification flows can help minimize silicon re-spins and improve the quality of design. Formal analysis methods can statically expose corner-case functional bugs that are difficult – sometimes impossible – to detect with dynamic verification techniques like simulation, acceleration or emulation."

Bernd Zombek, Project Manager at Siemens, is quoted: "We conducted an extensive evaluation of leading static property checkers and chose the Incisive Formal Verifier for production flow adoption. It enables us to begin verification months before the testbench is ready, which improves productivity for our design and verification teams. Incisive Formal Verifier is easy to adopt and almost anyone can use it after some basic assertion training."

Mitch Weaver, Vice President and General Manager of Systems and Functional Verification, Cadence agrees: "The introduction of the Incisive Formal Verifier product represents an evolutionary change in how designers will design and verify large, complex chips. Functional verification has been a significant challenge in the chip-design process and having the ability to formally verify assertions substantially increases our customers’ productivity, while improving the quality of the design."

** Eagleware-Elanix Corp. announced its Founder's Forum, which the company describes as an open and searchable database with questions and answers from experts about RF and microwave design problems, now has over 1000 threads posted. Per the Press Release: "In over 6 years of operation, the open and free Founder's Forum has achieved over 1000 unique topics or threads posted with helpful information for microwave and RF designers. Most threads average 5 or 6 postings from expert engineers. Today's most popular topics include modeling, oscillators and narrow band filters. "

Randy Rhea, Founder and Chairman of Eagleware-Elanix, is pleased: "Our unique Founder's Forum does much more than support designers with product information. It helps the RF and microwave design community with answers to their critical design-related questions."

Charlie Miller, Eagleware-Elanix, Vice President of Marketing and Business development, is also quoted in the Press Release: "The Founder's Forum has information that is valuable for all microwave and RF designers, and is not just for our customers."

** MatrixOne, Inc. announced a new release that the company says includes "enhanced product portfolio management and synchronous product engineering capabilities," which happily enable customers "across the globe to make more strategic decisions about the development of new products," thereby helping companies "reduce development costs and speed introductions," [and] "enabling companies to increase the potential return on their new product innovations."

Sam Zawaideh, Senior Vice President of Products and Solutions at MatrixOne, is proud: "With the new product development process becoming increasingly complex, companies need advanced solutions that deliver to everyone touching the new product process - from the drawing board to the boardroom – the most accurate, updated information needed to make informed decisions. Our product portfolio management and synchronous engineering solutions help organizations eliminate barriers and enable true real-time collaboration and decision making."

This Press Release is very informative as well: "Due to mass customizations and personalizations, the number of new products rolled out to consumers worldwide continues to blossom at a record-pace - and companies are forced to spread their limited product development budgets among an increasing variety of new products. In order to accurately capture customer needs, efficiently execute new product development projects and analyze the performance of various product development business processes in real-time, a PLM-based product portfolio management solution is needed. When implemented correctly within a PLM platform, portfolio management capabilities serve as the foundation to analyze competing product opportunities – providing management with the information needed to make the funding, development and launch decisions that are increasingly important to a company's future. In addition to having the proper tools to successfully manage its product portfolio, a company needs to eliminate the significant barriers that exist between different design disciplines and work to enable effective real-time collaboration among them all – something known as "synchronous engineering." In order for products to be developed on-time and on-budget and with no costly errors, these various disciplines – often comprised of electrical, semiconductor, mechanical and software design elements – must work together on an enterprise product data view that is automatically updated with the latest information, no matter where system, design, and manufacturing engineers are based in the world. In addition, the solution must enable companies to adhere to and keep pace with new environmental compliance regulations throughout the product development process. Synchronous engineering helps compress development cycles, improve information reuse and reduce the possibility of product rework, ultimately enabling companies to produce better and more products at a lower cost."

** Mentor Graphics Corp. has announced extensions to its Catapult C Synthesis algorithmic synthesis tool, which the company describes as "a leading ESL design tool." with extensions that allow the tool to automatically create SystemC transaction-level models and wrappers and thereby help designers explore architectural tradeoffs. The Press Release says these extensions are helping designers "simulate their designs 20X to 100X faster than traditional RTL using verification environments that support SystemC, like Mentor’s ModelSim."

Venkat Rangan, Senior Staff Engineer at Qualcomm, is quoted in the Press Release: "The new enhancements to Catapult C promise to automate the time-consuming process of SystemC model creation. Automatic SystemC model generation has great potential to accelerate block- and system-level verification, which would enable designers to produce better hardware much faster than before."

Simon Bloch, General Manager of the Mentor Graphics Design Creation and Synthesis Division, is also quoted: "The combination of algorithmic synthesis from pure ANSI C++ with an integrated SystemC verification environment provides a powerful solution for ESL design. For the first time, designers now have a methodology for easily implementing a ‘golden source’ from the algorithmic level of abstraction down to technology-specific RTL. With the ability to generate SystemC models, designers can now rapidly explore architectural tradeoffs and verify their design, while re-using existing C++ and SystemC testbenches throughout the flow."

Additional tutorial notes from the Press Release include: "The Catapult C Synthesis tool enables designers to use algorithmic C++ models as a "golden source." The tool employs interface synthesis and sequential-to-structural transformations to automatically generate SystemC or RTL hardware descriptions without changing the original sequential C++ source. Traditionally, designers had to manually re-write their C algorithms into SystemC, a slow and painstaking process of incremental refinement, adding the structure, parallelism, and interfaces necessary for SystemC. Instead of this manual progressive refinement, the Catapult C Synthesis tool now automatically adds these hardware details to the algorithmic C++ model to generate a cycle- and bit-accurate behavioral SystemC model. Hardware designers can then employ Mentor’s scalable verification platform to rapidly verify generated models. The interface of the SystemC model has the same behavior as the RTL generated by Catapult C Synthesis, but is optimized to simulate 20-100X faster. Designers can, therefore, more rapidly explore and verify architectural tradeoffs and achieve faster verification of their optimized designs."

** The Optical Internetworking Forum (OIF) announced that it has completed two Implementation Agreement (IAs) relating to Common Electrical I/O technology. The new agreements are based on CEI IA, published early in 2005, that addressed 6 Gbps short and long reach and 11 Gbps short reach applications. This now completes a 2-year effort "to increase system capacity and bandwidth by doubling and quadrupling the rate of electrical signaling between chips and over backplanes."

"The first, CEI 11G-LR, addresses 11 to 13 Gbps applications over backplanes. This IA responds to the industry’s move toward higher speed electrical signaling, driven by system vendors’ desire to quadruple the bandwidth of existing systems without increasing the number of backplane traces."

"The second IA, CEI Protocol (CEI-P) is a new protocol designed for use with the fast electrical interfaces developed by the CEI project team. A key feature of this new protocol is the Forward Error Correction (FEC) capability, which is tolerant of burst errors and substantially improves the error rate performance of a link. The FEC has the capability to improve the channel’s bit error ratio by as much as 12 orders of magnitude."

And just in case you didn't know:

"Launched in April of 1998, the OIF is a non-profit organization with a unique and diverse member base, including many of the world's leading carriers, component manufacturers and system vendors. As the only industry group uniting representatives from data and optical networks, the OIF helps advance the standards and methods of optical networks. The purpose of the OIF is to accelerate the deployment of interoperable, cost-effective and robust optical networks and their associated technologies. Optical internetworks are data networks composed of routers and data switches interconnected by optical networking elements."