How can we possibly absorb all this news in the days before DAC?

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Vying for favorite story of the week ...

** Sigrity, Inc. has announced CoDesign Studio, that the company describes as "a complete chip and package co-design solution for analyzing the performance of the combined power delivery system. CoDesign Studio is the first EDA solution to simultaneously co-simulate the complete chip and entire package in an integrated design environment. It leapfrogs existing power integrity tools by including all package effects that impact the correct operation of the chip. Sigrity's unique co-design methodology ensures that ICs are operational when they are placed into actual packages, preventing costly respins, and potentially saving millions of dollars for companies in the semiconductor, computer, graphics, communications and networking industries. Unlike other EDA tools, the CoDesign Studio solution analyzes power integrity of the entire chip and package power delivery system. This comprehensive approach combines Sigrity's proven flagship SPEED2000 solution for de facto-standard electrical analysis of packages, with the company's XcitePI solution for complete IC power grid analysis."

Jiayuan Fang, President of Sigrity, is excited: "Power integrity issues continue to be a critical concern for high-speed designs. Most current EDA tools inadequately represent chip/package interactions, often leading to incorrect or misleading power analysis results. Sigrity helps companies overcome these deficiencies by co-simulating the complete chip and entire package to ensure correct operation and reduce design iterations."

** Mentor Graphics has announced its new line of Questa verification products. The company says "the Questa verification products offer built-in support for testbench automation, coverage-driven verification (CDV), assertion-based verification (ABV), and transaction-level modeling (TLM). This initial release includes two new products: Questa SystemVerilog and Questa Advanced Functional Verification (AFV). Both products utilize a new verification technology, QuestaSim, the first standards-based, single-kernel verification engine that integrates an HDL simulator, a constraint solver, an assertion engine, functional coverage, and a common user interface."

Robert Hum, Vice President and General Manager of Mentor Graphics Design Verification and Test Division, is quoted: "Every survey indicates that verification remains a huge bottleneck in design cycles, and it's clear that the industry must transition to new verification methodologies to eliminate the bottleneck," "With Questa, designers can use the latest language standards and methodologies to find more bugs faster and increase verification productivity."

** Silicon Design Systems, Inc. has announced its first product, K-Route, which the company calls a "next-generation IC router with a push-button flow, and fully automatic geometrical and electrical convergence. It leapfrogs traditional closure methodologies in efficiency and predictability to improve the bottom line of each physical design project. Unlike other solutions, K-Route's Interconnect Synthesis implementation is placement-independent because it uses its own powerful incremental placement engine, and easily can be plugged into any physical design flow. The company expects K-Route to revolutionize routing similar to the way Physical Synthesis impacted placement."

Nir Sever, Senior Director for VLSI Design and Technology at Zoran Microelectronics, is quoted: "Our company develops devices for consumer electronics applications with an aggressive die size target. The idea of concurrently optimizing our designs during the routing process, rather than afterwards appeals to us as it can potentially allow us to achieve higher utilizations. K-Route holds great promise for us, and we are actively investigating its benefits. We have used SDS technology in the past to achieve substantial value in terms of die size and predictability."

Naveed Sherwani, President and CEO at Open Silicon, is also quoted: "Closure predictability and time to market are key elements for success in our competitive environment. We feel that K-Route's unique approach of progressively optimizing the design can bring great benefit to our time to market."

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In other news …

** AXIOM Design Automation, formerly @HDL Inc., announced the release of what the company calls "a complete SystemVerilog verification environment, augmenting its existing leading edge formal verification and debugging products with the introduction of the MPSim simulator. MPSim offers native design, testbench, and assertions while delivering up to 6x performance improvement using commercially available multi-CPU hardware … MPSim also provides a unique graphical environment that allows integrated debugging of design, testbench and assertions to help locate and fix the most complex design bugs. The overall performance of the verification environment is enhanced by native integration of testbench and assertions. MPSim is currently in production use at customers with leading edge designs including Raza Microelectronics, SiNett and Bay Microsystems."

Please note that: "The emerging computer hardware and CPU technology is focused on delivering multi-core and multi-CPU systems rather than the previous emphasis on faster clock speeds."

That's why Badru Agarwala, President and CEO of AXIOM, says: "MPSim is a fourth generation simulator architected from the ground up take advantage of these emerging hardware platforms. MPSim can achieve up to 6x performance across all aspects of verification with currently available commercially hardware without requiring any changes to the design or verification environment." MPSim is architected such that its performance will scale further as hardware with more than 8 CPU’s become available.

** Azuro, Inc. announced PowerCentric, which the company is excited to describe as "a revolutionary new low power clock implementation solution that significantly reduces the power consumption of digital chips … Azuro’s PowerCentric solution differs from existing industry design flows where clock gating and clock tree synthesis are performed at two different points in the flow. By unifying these operations at the placed gates level in the design flow, PowerCentric’s patent-pending iCTS technology is able to explore a larger global solution space of clock gating topologies and make power-timing trade-offs that are superior to current industry solutions. When compared to the industry’s existing low power design flows, PowerCentric delivers significant reductions in the dynamic power consumption of logic blocks without any impact on design performance."

Steve Barlow, Senior Director of Engineering for Broadcom's Mobile Multimedia Products, confirms the excitement: "Power dissipation has become increasingly important to the semiconductor industry as consumers demand ever more talk time, play time, and functionality in their next-generation mobile phones and portable devices. Meeting power requirements is one of the biggest challenges facing chip design teams today. Without effective clock gating, most of the active power in a typical digital logic block is consumed by the clock and registers. Azuro provided Broadcom with design automation tools that assisted in reducing the active power consumption of our BCM2702 mobile multimedia processor."

Meanwhile, Steev Wilcox, Co-founder and Chief Architect at Azuro, wisely points out: "You cannot optimize what you cannot accurately measure. Our SASim vectorless power estimation technology enables PowerCentric to implement the best trade-offs and save the most power during optimization."

** CAST, Inc. announced that Tezzaron Semiconductor has implemented a wafer stacking technology core from CAST to produce the first 3D IC processor.

Per the Press Release: "Tezzaron’s 3D IC processor uses the vertical connections and precise stacking of their FaStack process to place 128 Kbytes of SRAM memory above the 8051-type processor and bind the two layers into a single device. Using a 160-nanometer technology, the resulting 3D IC runs up to ten times faster and requires only about 1/10 the power of a typical 8051. The core, CAST’s R80515, uses a reduced instruction set and other features that make it an effective and efficient embedded processor or controller."

Robert Patti, Tezzaron’s CTO, is quoted: "We wanted to demonstrate our technology with a workhorse processor that’s still used in thousands of products and devices around the world. CAST proved to be a great partner – easy to work with and providing excellent support—and implementing their core was painless and straightforward."

** Celoxica Ltd. has announced availability of the RC10 Pilot board, which the company says is a "low-cost, high-density, FPGA-based embedded system teaching and evaluation platform. Expressly built for designers, teachers and students who want to pilot C-based design and synthesis, the RC10 represents a breakthrough in FPGA board price and performance. The RC10 Pilot board is fitted with a 1.5 million-gate Spartan 3 FPGA and is packaged with a set of comprehensive support libraries intended for use with Celoxica's suite of ESL design tools including the DK Design Suite and PixelStreams image and video processing library. The feature set of the RC10 makes it suitable for prototyping and development of diverse applications such as robotics, encryption, automotive diagnostics, audio, video and image processing."

"The RC10 Pilot board is also ideally suited to accelerate users through the learning curve associated with C-based embedded system design and synthesis. The board package includes design examples and tutorials showing applications integrating MicroBlaze soft-core processors and PicoBlaze embedded microcontrollers. System level APIs supplied with the RC10 enable HW/SW co-design and architectural exploration of system partitions by abstracting the specific board level detail away from the application code."

Graham McKenzie, Senior Product Marketing Manager at Celoxica, is quoted: "C-based design and synthesis is growing in established markets, attracting users that are new to hardware and FPGA design. The RC10 encourages that growth with ease of use, very low cost and an advanced set of features extending beyond raw hardware and supporting a much broader range of applications."

** Denali has announced that its Databahn and PureSpec IP products now support the Serial ATA (SATA) open industry standard. Per the Press Release: "The Databahn IP for SATA is a complete, synthesizable IP core that supports SATA 1.5Gb/s and SATA 3Gb/s including Native Command Queuing (NCQ) functionality. PureSpec for SATA is a comprehensive verification IP solution that also supports optional features in the specification."

Joni Clark, SATA-IO Marketing Chairwoman and Seagate Technology Serial ATA Marketing Manager, is quoted: "As the industry prepares to introduce powerful 3Gb/s Serial ATA systems, PC and server builders need powerful tools to help them comply with the Serial ATA specification, as well as meet their own quality and time-to-market requirements. We welcome Denali’s participation in SATA-IO and in-depth knowledge of the current SATA specification; it will prove important for Denali customers who want to enable the highest-performance Serial ATA 3Gb/s systems."

** Denali also announced that its PureSpec verification IP product is now available for the verification of USB designs. Denali says PureSpec now provides both design and verification engineers with a high-quality solution for modeling, simulating, and verifying designs that utilize the latest USB 2.0 and USB OTG (On-The-Go) interfaces.

A. K. Ganesan, President of Arasan Chip Systems, is quoted: "Denali has earned the reputation for providing the highest quality verification IP in the industry. We have developed a very sophisticated verification environment for our products, and PureSpec plays a critical role in the functional verification of our USB designs."

** Denali also, also has announced that its PureSpec verification IP product now supports the verification of Ethernet designs. Denali says its PureSpec product provides design and verification engineers with a comprehensive solution for modeling, simulating, and verifying Ethernet interfaces.

Vic Juneja, Product Marketing Manager for Denali, is quoted: "PureSpec is the most trusted verification IP solution in the industry. Denali has an excellent track record for providing high-quality verification IP for other interfaces such as PCI Express and DDR memory and we are leveraging the same proven architecture to now support Ethernet interfaces. Our customers rely on us to provide a very high-quality solution that works with all the latest testbench tools and languages for out-of-the box productivity and reuse."

** Eagleware-Elanix Corp. announced GENESYS 2005, which the company describes as "a major new release of its popular RF and microwave design suite. The new version includes

WhatIF – a frequency planning tool, uses a new simulation technique that analyzes spurious performance of Intermediate Frequencies (IFs). Spur-free regions are identified including multiple frequency band conversions to a common IF frequency. Users see performance tradeoffs between the IFs and can identify all spurious offenders giving them complete control over mixer requirements and specifications. This approach is a complete turnaround from traditional methods.

CAYENNE – a SPICE-like time domain simulator. In addition to the normal analysis capabilities available in other time domain simulators, CAYENNE incorporates the following: Direct use of S-parameter data, faster hybrid frequency/time mode creates models that are exactly correct at a specific high frequency and are approximate at other frequencies, User trade-off of accuracy versus simulation time, Co-simulation with electromagnetic simulator, including lumped elements, and Compatibility with all GENESYS linear, nonlinear, Verilog-A, and system elements.

MIXER – a new mixer synthesis module, which allows the user to design and analyze mixer configurations using a variety of topologies as starting points. The 11 topologies of the initial release range from simple passive configurations such as the "diode rat race mixer" to complex active models such as the "bipolar double balanced Gilbert mixer." For each configuration, supporting information provides insights into the theory of operation, applicable frequency range, and performance tradeoffs.

AMPLIFIER – a new amplifier synthesis module, facilitates the design of linear low-noise RF amplifiers. Requirements can be automatically transferred from system-level behavioral models, and simulation results can be exported to system-level simulation to check results. Transistor and FET implementations are supported in both single and multiple stage configurations.

** Emulation and Verification Engineering (EVE) announced new capabilities to its ZeBu verification platform that include a transaction-level interface to Native Testbench (NTB) in Synopsys, Inc.’s VCS RTL verification tool, and support for SystemVerilog assertions and automated design clustering software.

Per the Press Release: "The ZeBu platform now offers a high-performance, transaction-level interface to Synopsys’ VCS solution. The interface enables advanced testbenches running in VCS NTB to drive and monitor designs running on ZeBu at MHz speed. The interface can utilize a Synopsys Reference Verification Methodology (RVM) transaction-level channel class interface, enabling the upper layers of an RVM-based testbench to run in VCS, while lower layers of the testbench and the design under test (DUT) can be simulated in either the VCS solution or the ZeBu platform. This approach enables customers of the VCS solution to apply native technologies, such as constrained-random stimulus generation and comprehensive functional coverage, to designs running on ZeBu. In addition, concurrent and temporal synthesizable SystemVerilog assertions are fully supported by ZeBu to provide coverage feedback or to control the emulation execution."

Lauro Rizzatti, Worldwide Marketing Vice President and EVE-USA General Manager, is quoted: "Our ZeBu platform is the only verification solution on the market to address hardware/software integration and embedded software validation at more than five MHz on designs exceeding 10 million ASIC gates. ZeBu does not require specialized prototyping technology experts to map a complex design."

** Golden Gate Technology Inc. has announced two new software products – Power Optimize Gold and Power Plan Gold – that work with existing place & route flows from Cadence Design Systems, Synopsys and Magma. Golden Gate says its new products "can reduce total power consumption by up to 25%. Power Optimize Gold reduces leakage and switching power while simultaneously meeting constraints for timing, signal integrity and electromigration. Power Plan Gold creates architectural multi-voltage-island designs by automatically creating complex power grids. This enables sophisticated on-chip power management schemes."

Kelvin Chun, Director of Design Center Application Engineering at Oki Semiconductor, is pleased: "We have over 50 successful tapeouts with Power Plan Gold."

Dave Holt, CEO, Lightspeed Semiconductor, is also pleased: "From our benchmarks, we determined that, out of all the tools we evaluated, Power Optimize Gold consistently produced exceptional results."

Okay, now it's time to get technical: "Wires account for 5x more power consumption than transistors at the 90 nanometer node, and 30x more power consumption than transistors at 35 nanometers. Since wires burn most of the power on nanometer chips, Golden Gate's power reduction software gives wires the first priority with a patent-pending optimization technology called, WiresFirst. WiresFirst minimizes total capacitance on critical clock and signal nets through route optimization and isolation techniques that reduce power without negatively impacting chip timing, signal integrity, or electromigration."

"Power Optimize Gold reduces power at many stages in the physical design flow. Power Optimize Gold works with placement and clock tree synthesis to reduce power consumption in the critical clock network. WiresFirst algorithms incrementally rebalance capacitances and restructure logic to recover excess power consumption with minimal perturbation to a design's timing and physical layout characteristics. When used throughout the design process, the various power reduction techniques implemented by Power Optimize Gold are cumulative."

"Power Plan Gold works with silicon-virtual-prototyping tools to automatically create sophisticated multi-voltage-island architectures that supply the optimal amount of current to every device on a chip. With WiresFirst technology, Power Plan Gold gives designers the most accurate power-consumption information, earlier in the design flow than was previously possible. With this data, chip engineers can now build their power supply systems correctly the first time without incurring either costly downstream iterations caused by undersized power grids, or wasted power and silicon resources caused by over-designed power architectures."

** IC Manage announced the IC Manage Caching Accelerator network appliance, which the company says significantly improves performance in large multi-site and multi-user Perforce installations. The Caching Accelerator requires very little setup so that IT professionals can gain significant performance benefits with very little effort."

Wait, there's more: "The Caching Accelerator seamlessly integrates into existing environments, including Storage Area Network and Network Attached Storage models, delivering a higher performance hardware solution. The best way to combine both performance and reliability is to use the server as a caching accelerator and perform write-back operations to the network storage within the corporate enterprise storage system to deliver both performance and reliability without compromise. The accelerator consists of a hardware server with a disk cache and software to manage real time replication and cache management. The server utilizes commodity x86 components running Linux to deliver low cost with maximum performance."

** MatrixOne, Inc. announced that the Bosch Group has selected The MatrixOne PLM platform to implement "across its global operations to drive collaboration and speed product development. Over time, thousands of Bosch employees worldwide will be linked to the MatrixOne PLM platform and Bosch’s existing product data management (PDM) systems will be integrated into the MatrixOne system. In highly competitive global markets, innovations based on new approaches in product development and production are pivotal for a company’s success." Wow.

But there's more: "Bosch has an additional goal for their implementation of the MatrixOne PLM platform – to integrate the three worlds of mechanics, electronics and software. In order for products to be developed on-time and on-budget, these various disciplines must work together on an enterprise product data view that is automatically updated with the latest information—no matter where these designers and system engineers are based in the world!"

** Impulse Accelerated Technologies, Inc. and PICO Computing, Inc. have announced the joint release of the Platform Support Package, which allows the Impulse C tools to compile C algorithms to PICO’s E-12 line of CompactFlash FPGA accelerator cards. The companies say, "The resulting software-programmable hardware accelerator offers the potential for startling speedups of desktop and embedded software applications (with 10X to 400X increases in processing speed common), in a form factor the size of a standard CompactFlash memory card … The Impulse tools optimize the C code to exploit the FPGA’s parallel processing capability, resulting in potentially large factors of acceleration. The Impulse tools also generate the required software-to-hardware interfaces, allowing data to be moved efficiently between the FPGA and the optional on-board PowerPC processor, and between the E-12 card and a host PC. Applications where this type of approach shows the most promise include image processing, video processing, data encryption, bioinformatics, geophysics and other types of embedded and scientific computing … The PICO E-12 is based on the latest-generation Xilinx Virtex-4 FPGA. There are two versions of the PICO E-12: Logic Optimized (LO) and Embedded Processor (EP). The Logic Optimized versions offer the most user-configurable logic, while the Embedded Processor version provides a reduced amount of FPGA logic but adds an embedded PowerPC processor."

Robert Trout, Founder and President of PICO, adds comment: "We are excited by the growth of FPGAs as general-purpose computing platforms. To that end we are providing a design environment designed more for software programmers. The Impulse tools provide such an environment."

David Pellerin, Co-founder and President of Impulse, agrees: "We are great believers in FPGAs for general-purpose computing. The PICO E-12 lets software engineers accelerate algorithmic hot spots in a fraction of the time it would take to do it in VHDL."

** Microsoft says it has selected ASSET’s ScanWorks boundary-scan (IEEE 1149.1/JTAG) test system for its Xbox 360 video game and entertainment system marks the first major announcement of boundary scan in a high-volume consumer electronics product. Through the end of the year, over 50 ScanWorks systems will be deployed to test the Xbox 360 console throughout its product life cycle.

We so rarely hear from our friends in the Pacific Northwest, it's good to have this quote from Don Kadyk, Manufacturing Test Engineering Manager of Microsoft: "We continually look for ways to improve the quality of the Xbox experience. That means looking for ways to test the quality of our product at every phase in its life cycle. We saw that ASSET’s ScanWorks had the versatility and portability to support our life-cycle testing goals and keep a lid on test development costs. In the very price-sensitive consumer electronics marketplace, it’s incumbent upon us to reduce costs whenever we can and ScanWorks is helping us do that."

Gabe Valentin, Manufacturing Test Engineer at Microsoft, also wants to chine in: "As we began to develop our test strategies for the Xbox 360 console, we thoroughly analyzed whether incorporating boundary scan into ICT and functional test would be effective. In the end, we realized that any risk would be eliminated because we could migrate the ScanWorks’ tests that were developed for prototype debug into ICT and functional test. Our investment of time and effort in developing boundary-scan tests for ICT and functional test would be minimal."

** Nallatech has announced the Virtex-4 XtremeDSP Development Kit, which includes a range of IP – memory controllers, BIST and examples designs, allowing rapid configuration of high-speed memory subsystems and design implementation – and Nallatech’s FUSE system software to control and configure the board. The systems communication design tool DIMEtalk, is also available to help migrate designs developed on the Virtex-4 SX35 XtremeDSP Development Kit to multiple FPGAs.

The Press Release says the Development kit will: "immediately leverage Xilinx new DSP-rich Virtex-4 SX FPGAs in new advanced FPGA designs. The Virtex-4 XtremeDSP Development Kit is equipped with a SX35 Virtex-4 FPGA, which has 192 XtremeDSP slices, where each slice is capable of operating at 400MHz providing performance up to 77 GigaMACs/second (using 18x18 multipliers). The Virtex-4 SX FPGA also features additional embedded memory capacity, featuring 3,456Kbits internal RAM and 15,360 logic slices as well as supporting low power performance ideally suiting the board for high performance DSP designs for 3G wireless, video encoding and decoding, including H.264 or MPEG-4, radar and beam forming applications."

Please Note: "Xilinx and Nallatech have a history of bringing to market comprehensive development kits for digital communications and signal processing applications. The Virtex-4 SX35 platform builds on the success of the popular Virtex-II and Virtex-II Pro XtremeDSP development kits, which Xilinx has been shipping since 2002."

** Open Core Protocol International Partnership (OCP-IP) announced that the OCP interface is the "latest addition" to the Mentor Graphics CheckerWare library of verification IP.

Per the Press Release: "The CheckerWare solution is comprised of a library exceeding 100 assertion checkers and protocol monitors, making possible the quick adoption of cutting edge assertion-based and formal verification methodologies without the cost and risk often associated with the adoption of new tools. The monitor currently supports OCP v2.1, the organization's newest standard, announced in March. OCP 2.1 includes profiles for the most commonly coupled OCP features and an advanced tagging scheme for enhancements in out-of-order processing.

Ian Mackintosh, President of OCP-IP, is quoted: "OCP has a robust, thriving infrastructure supported by many independent companies such as Mentor that provide excellent services and products. This is a testament to the tremendous adoption we have seen throughout the industry."

Steve White, General Manager of Mentor Graphics' 0-In Functional Verification Business Unit, is also quoted: "Mentor Graphics is proud of being a contributor to the OCP-IP organization, with OCP as a leading interconnect to our customers designing complex SoCs. The addition of the CheckerWare OCP monitor enables these customers to quickly adopt the advanced methodologies needed to reach verification closure."

** Optimal Corp. announced what the company is calling "the EDA industry’s first full-wave adjacent structure coupling capability in Optimal’s Full-Wave Signal Integrity/Power Integrity (SI/PI) Simulation Flow. Designers of IC packages and PCBs can use Optimal’s PowerGrid and O-Wave products to completely model signal and power nets together on designs with over one million edges."

Hold on to your hat – we're getting technical again: "Current full-wave simulation tools can model either signal nets or power nets, but not both. To create an adjacent structure-coupling model, users must break their model down into multiple sections and simulate each section separately. Even then, initially complex device geometry must be simplified from millions of edges down to 200,000-300,000 edges in order for other tools to be able to run the simulation to completion. The final step is to manually compile the results into one final model. This level of up-front data manipulation and results compilation is time-consuming, error-prone and substantially impacts the accuracy of the results."

"Optimal developed its full-wave adjacent structure coupling capability by adding a Full-Wave Coupling module to its O-Wave product. Armed with this new Full-Wave SI/PI Flow, the user runs a simulation on selected signal nets and part of the Power/Ground nets in O-Wave. Simultaneously, PowerGrid runs a simulation on the complete Power/Ground structure which is then combined with the O-Wave results, resulting in one complete model."

"Adjacent structure coupling is the electromagnetic (EM) interaction between adjacent structures on a given device. The structures may be physically located side by side on the same plane, or adjacently on a horizontal plane to a vertical connector. Resulting from the close proximity of adjacent structures, one structure may cause changes in the EM characteristics of itself, or of the adjacent structures nearby. Predicting and controlling these potential changes in EM characterization is imperative as devices continue to increase in complexity. Optimal’s Full-Wave SI/PI Flow now enables designers to accurately simulate these EM effects in the design iteration process."

** Pentek, Inc. has release its Model 6826 VME A/D Converter board. Per the Press Release: "The Model 6826 features single- or dual-channel data acquisition at a blazing 2 GHz samples/second with 10-bit resolution using the new Atmel AT84AS008 A/D device. The board’s ability to accept either single-ended or differential inputs preserves signal integrity across a variety of analog signal sources."

Rodger Hosking, Vice President at Pentek, is quoted: "For our customers, this product opens up a whole new range of previously unavailable frequencies and applications. It allows them to directly digitize signal bandwidths up to nearly 900 MHz, so they can capture wideband radar and communication signals as a single channel instead of digitizing several smaller bandwidth slices. The inclusion of the Virtex-II Pro FPGA is essential for processing these large bandwidth signals to extract information and reduce the data rates to a manageable level within the system."

** PolarFab announced what the company describes as "a one-time programmable (OTP) antifuse for PBC4, PolarFab's 0.5 micron BCD (bipolar-CMOS-DMOS) process. The new antifuse is a non-volatile memory element that requires no additional mask layers, allowing for a cost-effective post-package or wafer-level trim capability. The antifuse hard macro is organized in an 8-bit (1-byte) block, where each individual bit may be selected for programming. In addition, multiple antifuse blocks can be implemented in a single design yielding a greater number of trim bits per die and enabling trim coverage over a wider range or to a greater resolution."

** Sequence Design has announced that Toshiba America Electronics Components, Inc. (TAEC) has introduced a design kit for its custom SoC and ASIC customers using Sequence's PowerTheater. The companies say the kit supports designs for using the TAEC TC280 (130-nanometer) and TC300 (90-nanometer) process technologies, there will be support coming along for future processes as well.

Also per the Press Release: "PowerTheater was benchmarked on a 10-million gate ASIC to establish 15 percent accuracy between RTL and gates. Operating on a 64-bit platform, PowerTheater analyzed power on the entire design both at RTL and gates in less than overnight runs."

** Synopsys, Inc. announced that its DesignWare Universal Serial Bus On-The-Go (USB OTG) digital core plus three physical interfaces (PHYs) IP is "the first and only complete OTG IP solution to be certified by the USB Implementers Forum (USB-IF). The certification helps ensure DesignWare users of interoperability with Hi-Speed USB PCs and Hi-Speed USB OTG products."

Jeff Ravencraft, Chairman and President of the USB Implementers Forum (USB-IF), is quoted: "USB is the most successful PC connectivity standard of all time and it has successfully migrated into CE and Mobile devices. We welcome Synopsys' work to further the standard's acceptance in the marketplace. As an active member of the USB-IF Synopsys continues to help ensure high-quality USB specifications."

Then Mario Manninger, Director of Engineering in the Communications Business Unit of austriamicrosystems, is quoted: "We looked to Synopsys for the complete, high-quality, Hi-Speed USB OTG solution that we needed to quickly and reliably integrate into our portable audio platform," said "Synopsys' rigorous approach to quality and risk reduction has enabled us to make Hi-Speed USB connectivity a differentiating feature of our products."

Finally, Eric Huang, Product Marketing Manager for DesignWare USB IP at Synopsys, has his say: "Designers can now select from more semiconductor processes to align with targeted silicon costs. They can use our certified digital core with one of our three certified PHYs – two in 130 nanometer and one in 9 90-nanometer processes. Synopsys continues to lead the way in risk reduction by participating at the first Hi-Speed USB OTG plugfest held by the USB Implementers Forum, and passing all the tests with not just one, but three PHYs."

Please note: Eric Huang also serves as chair of the USB On-The-Go Working Group.

** Tenison EDA says it will be providing additional support for the ESL design flow through its VTOC technology. The company says it's now bridging the ‘Model Gap’ by synthesizing models from RTL to higher levels of abstraction.

To quote specifically, "Targeted at unifying HW design and SW development, VTOC’s integrated methodology bridges the language and performance barrier by moving existing RTL IP into high performance C++ and SystemC models. These are needed by Software and Architectural engineers to begin early program validation, thereby reducing the overall time for product design. Future releases will provide models that operate with transaction level designs at even higher speeds."

Martin Harding, CEO at Tenison, is quoted: "The ability to create C++ and SystemC models from RTL on the fly and verify their equivalency is the first step in our strategy for supporting our customers in ESL design. As complexity continues to increase and designers move to higher levels of abstractions to cope, there will be a growing need to be able to move up and down between these levels to gain the maximum benefits of the speed and accuracy tradeoffs."

Subject update: "As consumer and communications demands increase, design complexity and the dominance of embedded software content has grown dramatically, coupled with product introductions increasingly being delayed by late software design starts or overruns. This is primarily due to the lack of hardware prototype platforms that have traditionally been necessary for software development. Subsequently, designers are moving to an ESL design methodology, where they are able to generate higher-level models of their designs in various languages such as SystemC and C++ depending on their needs, knowledge, or development process."

"Currently, the models written for this system level exploration or process investigation have no direct connection to the RTL used for implementation, thus there is no guarantee of equivalency; as if one model was directly derived from the other. The different models are most often written by hand and updated if required to maintain consistency across multiple code and language development paths. Tenison’s VTOC tools automate - through advanced algorithms - the movement from one level to another, verifying the accuracy and continuity of the models as you go."

** Tensilica, Inc. has announced that Agilent Technologies, Inc.’s Imaging Systems Division has signed a technology-access agreement to license Tensilica’s Xtensa V and Xtensa LX configurable processor technologies for next-generation products.

Steve Roddy, Tensilica’s Vice President of Marketing, puts pen to paper: "In their first design, Agilent’s engineers realized the tremendous benefits of using a configurable processor to speed their image processing application. Now, with much broader access to our technology, including the Xtensa LX processor, we look forward to further successful deployments of Xtensa processors in key imaging applications."

** Zuken announced what the company is calling a "major upgrade to its CR-5000 enterprise-wide PCB design suite of tools that includes 44 productivity enhancements in schematic capture, PCB layout and simulation. CR-5000 Version 8.01 is a constraints-driven tool suite aimed at designers of high complexity boards that utilize extreme miniaturization technologies such as embedded passives, flex circuits, high-density interconnects and FPGAs. CR-5000 capabilities include RF design, design re-use and design partitioning with core design strengths that meet the requirements of consumer and high-tech electronics applications. Version 8.01 has been built upon the same design structure and methodology of version 7, which, due to a strict quality management philosophy experienced only two critical bugs in 21 months. The improved version of CR-5000 has been developed in accordance with even higher quality standards, but also meets the growing demand for functionality to deal with variations, personalization and increased complexity – while being a fully integrated system."

There are a lot more enhancements where these come from – you should be checking it out ASAP.