Things - tools & technology July 18, 2005 ********************************** Midnight at the Oasis ... First read this: "The OASIS (Open Artwork System Interchange Standard) specification handles the ever increasing GDSII file sizes of complex deep-submicron designs. The specification's compact representation of geometric shapes can reduce file size enabling better tool performance. It also reduces storage requirements and speeds data file transmission. Adoption of OASIS will answer the need for common, open data formats for transferability between mask data prep (MDP) tools. Mask data file sizes have become so large at the 65-nanometer node that they are unmanageable in a cost-sensitive mask manufacturing environment, captive or merchant. When fully implemented, OASIS data file sizes decrease by 10-50X and the expression of those files can improve the performance of many of the tools and databases. Effective management of mask data at 65-nanometer and beyond is not only about file size reduction. Tool-to-tool data file interoperability and portability are relevant contributing factors affecting the rising costs of design and mask manufacturing." Then read this: Synopsys, Inc. announced that its Galaxy Design Platform and DFM tool suite support the entire OASIS file transfer format with all current production releases. The company says that "all relevant Synopsys software now support the OASIS format for design and production, including; Astro, IC Compiler, CATS, Hercules, Proteus, SiVL and Star-RCXT software products. These products provide the full benefit of OASIS' file compression capability and support the entire specification including the ability to process CBLOCK records which embed compressed data for additional compactness … Synopsys was an early participant in the Semiconductor Equipment and Materials International Data Path Task Force Working Group (SEMI DPTF-WG) that defined the new format. Finish with this: Tom Grebinski, President and CEO of OASIS Tooling. is quoted: "The industry is at a key transition point where geometric design and mask layout data can no longer be represented and expressed efficiently enough by GDSII. Synopsys invested significantly in the development of newer features and infrastructure supporting optimal interoperability that scale with the business and technological needs of its customers. High performance, OASIS compliant and interoperable MDP tools, such as those introduced here by Synopsys, become critical and timely for the replacement of GDSII tools." Raul Camposano, Synopsys' senior vice president, chief technical officer and general manager, Silicon Engineering Group. "With our Galaxy Design Platform and DFM product family support of the entire OASIS specification, we will help designers handle the burgeoning size and complexity of today's advanced designs and ease the transition to a new standard file transfer format." ********************************** Okay, now answer these four questions (without cheating) …
********************************** In other news ... * Actel Corp. introduced its Libero version 6.2 Integrated Design Environment (IDE). This release includes Actel's new SmartTime static timing analysis environment, which the company says helps designers analyze and manage timing constraints, perform advanced timing verification, and "ensure predictable timing closure through a tight integration with timing-driven place and route … The SmartTime Constraints Editor view enables users to list, edit and create precise timing constraints. It includes a graphical user interface with visual dialogs that guide users toward capturing their timing requirements and timing exceptions correctly." Actel points out in the Libero V 6.2 Press Release that this release extends an existing partnership with Mentor Graphics that allows Mentor's ModelSim AE simulation tool to be a part of the Libero "Gold" package and available to all Actel customers free of charge. Libero 6.2 also includes synthesis capabilities from Synplicity and physical synthesis features from Magma Design Automation. Also please note – Libero now runs on Linux and Solaris platforms. Saloni Howard-Sarin, Director of Antifuse and Tools Marketing at Actel, is quoted: "This new version of our Libero IDE includes significant new functionality for design analysis and timing closure. Users are able to apply constraints to their designs, manage and analyze the effects of those constraints, and drive their designs efficiently to timing closure, while achieving higher performance."
Neil Martin, Marketing and Services Manager with Agilent’s EEsof EDA division. "It’s good to know that ADS has met this customer’s current technical and budgetary needs, and that we can provide support and design expertise to help them succeed."
Kevin Rinebold, Senior Technical Marketing Manager in Synopsys' Packaging Products Department, is quoted: "As a result of our close collaboration, Ansoft's advanced electromagnetic technology for package extraction and characterization can be accessed directly from our Encore product today. Our work with Ansoft further advances the state of the art in package planning and design by integrating Ansoft's latest capabilities with our IC/Package co-design environment."
Per the Press Release: " As part of its ongoing commitment to providing customers with greater flexibility and choice in their design methodology, AWR has created the EM Socket(TM) open standard interface, which enables users to access a broad variety of EM tools from leading vendors, without leaving the Microwave Office design environment. The EM Socket interface provides unprecedented interoperability and ease-of-use, saving design time and increasing accuracy. " James Rautio, President of Sonnet, is quoted in the Press Release: "Both companies were inspired to explore mutual opportunities to integrate the best features of AWR's Microwave Office circuit design software and Sonnet's EM software and to demonstrate how easily two companies can work together in order to provide our customers with timely and superior solutions. In this spirit of cooperation, we were able to integrate AWR's Xmodels with the industry's most accurate and reliable high-frequency planar EM software in a matter of days; truly a testament to the openness and integration of the Sonnet and AWR environments."
Kanji Aoki, manager of the IC Design Technology Department at Epson. "With its leading-edge technology, Encounter RTL Compiler helped us meet the design schedule. Our designers will continue to follow the top-down synthesis method enabled by Encounter RTL Compiler to maximize our time-to-market advantages."
The Press Release says, " A variety of competing products have allowed abstract systems to be cobbled together, but have either ignored the RTL implementation altogether (idealized models), required long bring-up time (breadboards and emulators), or suffered from poor performance (co-simulation with event-based simulators) — all diametrically opposed to today’s short development schedules. The new [Carbon] product optimizes RTL compiler technology; system building blocks including transactors, memories, and IP cores; and tight integrations with SystemC and popular instruction set simulators. Carbon’s new software approach allows multiple levels of abstraction to be combined early in the design cycle, when only behavioral models, legacy RTL, and instruction set simulators are available. When full-chip RTL is ready later in the design cycle, the complete system can be validated with software executing on the real RTL implementation model. The key to VSP is performance; the ability to execute billions of cycles and boot embedded operating systems, all with desktop software." Steve Butler, President and CEO of Carbon, is quoted: "In the past, segregating the implementation view to hardware assisted solutions was necessary, because the EDA software tool chain just didn’t have the throughput required to validate today’s complex chips. VSP on the other hand, has the performance to incorporate behavioral models, the software programmer’s view, and RTL implementation—all in software."
The system captures and identifies a vehicle in real-time. Using license-plate recognition to calculate driving criteria such as distance and position the system allows the driver to maintain a safe distance from a car in front to reduce "tail-gating," and rear-end collisions. The ultimate use of the technology is the possibility of autopiloting the car with the flick of a switch. Once the majority of the cars in the world are so equipped, many believe traffic will flow smoother, faster, with fewer accidents and lower automotive care and insurance costs.
Mr. Tonou, Department General Manager at Fujitsu Ten, is quoted: "Through extensive testing we have proved that we can integrate C-based design and synthesis with model based design approaches. This better enables us to turn software into silicon and it will have a beneficial impact on our productivity and our customer responsiveness."
Per the Press Release: " Sponsored by the European Space Agency (ESA) the ACES program tests the performance of a new type of atomic clock that exploits and depends upon microgravity conditions. Approved to fly on the International Space Station, the program supports fundamental physics experimentation, new experiments testing general relativity within the solar system and will provide an ultra-high performance global time-scale … Kayser Threde built a qualification model as part of the FCDP verification process using special radiation hardened FPGA devices mounted onto a board. The code generated from the DK Design Suite was directly synthesized to the board and the system proved itself to be first-time correct."
Dave Ranhoff, President and CEO at Credence, is quoted: "Delay defects are a dominant cause of yield loss in designs at 90 nanometers. A Sapphire used in conjunction with Cadence Encounter True-Time Delay Test as well as Cadence Encounter Diagnostics provides semiconductor companies an optimized engineering and production test development path for detecting and diagnosing these most difficult problems. Supporting the design for yield methodologies developed by the major EDA suppliers like Cadence is important to our customers and fits into our broader vision of how Credence participates in design debug all the way to production test."
Per the Press Release: "The facility covers all advanced processes up to silicide level for both IMEC's planar bulk CMOS and multi-gate (MuGFET, FinFET) devices. To realize this, strategic alliances were concluded in 2004 with more than ten of the world's leading equipment suppliers - AIXTRON AG, Applied Materials, Inc., ASM International, ASM-Lithography, Axcelis, Dainippon Screen Mfg. Co., Ltd. (DNS), FEI Company, KLA-Tencor, Lam Research Corporation, Tokyo Electron Limited (TEL) and SEZ. The first pathfinder lots include bulk-Si nFET (targeting 45nm node) and SOI FinFET (targeting 32nm node) lots to demonstrate the readiness for moving the materials-and-device research projects from the 200mm to the new 300mm fab. The lithography of all critical levels is performed on the ASML /1250i immersion scanner. All lots have devices with physical gate length down to 40nm.TaN and TiN metal gates are used in combination with high-k dielectrics such as HfO2 for the gate stacks. Installation of the copper/low-k interconnect technology tools will start in the second half of 2005. The agreements with Applied Materials, ASM International and LAM Research Corporation have been expanded towards interconnect technology which will enable IMEC and its affiliates to investigate the most advanced low-k and copper plating solutions for the sub-45nm technology node."
David Pellerin, Co-founder and CTO of Impulse, is quoted: "The Xilinx Virtex-4 provides a great platform for accelerating embedded applications. By providing software programmers with a path from C code to FPGA hardware, we make it possible for embedded software applications to be accelerated dramatically, using familiar software design methods to target the Virtex-4 platform."
Per the Press Release: "This agreement begins an ongoing relationship in physical synthesis and routing addressing deep-submicron design, including lithography-aware routing, among Magma, IBM and the University of Bonn. Magma intends to leverage the IBM technology to integrate novel algorithms into Magma products. These include analytical formulations for routing – as opposed to the heuristic approaches used by most EDA companies today – resulting in reduced via count and significant yield improvement compared to existing EDA tools." Kevin Carswell, Vice President of Product Technology Development in IBM’s Systems and Technology Group, is quoted: "IBM sees this licensing agreement as an outstanding opportunity to expand the IBM relationship with Magma and more broadly leverage the innovative work of the University of Bonn. We look forward to working with Magma to enable the ongoing development of these advanced tools."
Paul Ouyang, Vice President of Design Services of SMIC, is quoted: "As design complexity and time-to-market pressures increase, we find that an inherently integrated flow that delivers better results is critical. With its unified data model, Magma provides tight integration and enables our engineers to communicate more easily with the customer, allowing us to quickly finish the design."
Sam Zawaideh, Senior Vice President for Products and Solutions at MatrixOne, is quoted: "By providing real-time access to product designs, companies can enhance collaboration across the value chain, speeding time to market and cutting development costs."
Jason Cheng, Vice President of R&D at ASUS, is quoted: "We feel that Mentor Graphics Expedition Series is the solution that will enable us to achieve that goal. In addition, it will allow ASUS to be even more efficient and to create a greater number of advanced designs faster and with better quality."
These plans are wide-ranging – per the Press Release: "Under the arrangement, Nallatech and SGI plan to assess complementary capabilities and integrate, customize and deploy FPGA computing solutions to existing customers and new prospects. Nallatech and SGI will collaborate on new business opportunities for products, tools and associated services in markets that require demanding high-performance computing solutions. The companies will also work together to apply FPGA-based computing solutions for growth markets that could include oil and gas - geophysical; homeland security; bioinformatics; medical imaging; and data distribution and visualization systems. The companies will work together to develop an integrated high-performance computing offering based on FPGA technology which will be used to facilitate high-performance, high-density implementations to support demanding computing needs and processing algorithms." The operative words here are: strategic, collaborative, high-performance, reconfigurable, FPGA, complementary, capabilities integrate, customze, deploy, solutions, prospects, opportunities, associated, growth, offering, facilitate, high-density, implementation, demanding, computing, processing, and algorithms.
Per the Press Release: "Traditionally yield improvement has been left to the people in the fab. However, there are often major opportunities to change the layout so that defects are less likely to cause faults. The EYES tool uses the design layout and fabrication defect data to make very accurate yield predictions that are reliably better than 1%, as reported by customers. The EYES tool uses a patented sampling technique to make it possible to quickly extract the critical areas of state-of-the-art designs. Yield reports are then generated in simple text, HTML with chip maps and graphs, or in a spreadsheet format."
Andre Chartrand, Vice President of Engineering at TranSwitch, is quoted: "TranSwitch was actively looking for technology that would allow our logic designers to predict the impact of their design decisions on the physical implementation process. On one of our recent projects, the Chip2Nite tool enabled us to identify several design issues and to rectify them prior to handing off the design to the physical design team. By handling these issues at the appropriate stage in the development process we avoided bogging down the physical design team unnecessarily and were able to meet our tight schedule. Even before the chip went to physical design our logic designers became aware of potential physical design problems. They were able to analyze several options, make the necessary modifications, and solve the issues well before any hand-off to physical design." **********************************
A new line of software products called SingingCoach now gives users instantaneous professional feedback without having to hire an expensive vocal instructor. SingingCoach software installs easily on a personal computer and makes it fun to sing better. It's a product that combines cutting edge technology with the expertise of a veteran vocal coach -- and it allows anyone to become a better singer using their personal computer. How Does SingingCoach Work? Once loaded on a computer, the user follows the step-by-step instructions given on the screen. The program comes with 20 singing lessons and a high-fidelity headset with a built-in microphone for a hands-free singing experience. The software technology of the SingingCoach tracks and displays the pitch of the singer, comparing it to the correct pitch of the chosen song. The singer is able to see where his/her pitch is off and make adjustments accordingly. At the end of each song performance the software calculates and displays a score from 1 to 100, giving users an immediate report on vocal progress. Once a skill is mastered, the program graduates the user to the next level.
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