** AccelChip Inc. announced AccelChip DSP Synthesis version 2004.6, which includes "significant" new MATLAB language support: New AccelWare Advanced Math Toolkit with Matrix Inversion and Factorization; New intellectual property cores including Reed-Solomon decoding; New native Galois field support in the AccelChip DSP Synthesis tool; Significantly improves the ability of algorithm developers to create forward error correction algorithms in their preferred form (Galois fields) for synthesis and verification; Improved support for two-dimensional array operations; A wider variety of designs using matrix- and array-based operations can be synthesized and verified using AccelChip products; Support for Virtex-4 devices; and Support for Cadence’s Incisive Simulator.

** BYO Solutions, Inc. announced its Partition-Pro partition tool designed for partitioning "big ASIC design in RTL description across multiple FPGA's automatically."

Daniel Day, BYO President, is quoted in the Press Release: "I am confident that our tool, Partition-Pro will shorten the design cycle time. It helps to build a good quality FPGA prototyping. A good quality FPGA prototyping means bug free, no re-spin. It saves time and saves money. It will be very useful when quick time-to-market is critical, even thought it is a relative small EDA tool. A six month free trial is available during the product announcement period."

** Cadence Design Systems, Inc. announced the release of Encounter Conformal Constraint Designer, which the company says automates the generation and validation of design constraints at all stages of the design process from RTL to final netlist.

The Press Release goes on to say, "New product performs comprehensive design constraint quality checks to ensure that designers start with high-quality constraints up front. This helps reduce the number of iterations due to invalid constraints. Design constraints are used to direct synthesis, timing analysis and place and route to meet a chip's timing, area and power requirements. Poorly designed constraints lead to long implementation design cycle time and the risk of silicon failure and re-spins. With design constraints getting larger and more complex, designers are spending significant amounts of time attempting to produce a set of valid constraints. Until now, there has been no automated solution dedicated to resolve this problem. Encounter Conformal Constraint Designer addresses the challenges of the new domain of constraint design by generating and validating design constraints, and helping pinpoint the root cause of constraint problems."

** MatrixOne, Inc. announced that Comau Pico selected MatrixOne as its standard PLM environment, and "will expand on previous efforts to improve the collection and flow of data throughout its organization in bringing new automation products to market. Comau Pico's adoption of MatrixOne PLM comes after several successful implementations of MatrixOne in other business units of the Comau Group."

** Mentor Graphics Corp. announced that TSMC used a comparison of Calibre xRC results, field solver data and silicon measurements as part of the validation for its 90-nanometer process technology. The companies say that TSMC and Mentor Graphics worked collaboratively on the test structures and the measurement technique to accurately quantify and measure 90-nanometer parasitic effects. The test structures that were developed comprised a wide range of line widths and pattern densities to evaluate the effects of process variation across the wafer and across a single die."

Our old friend Edward Wan, Senior Director of Design Service Product Marketing at TSMC, is quoted: "The objective of the TSMC 90-nanometer test chip program was to validate the stability of extraction correlation of the 90nm process using third-party vendor extraction tools such as Mentor Graphics Calibre xRC. As a result, our mutual customers can design to our leading-edge Nexsys technology with confidence in the accuracy of parasitic extraction results."

** MIPS Technologies, Inc. and Virage Logic Corp. announced that they have produced "a fully-routed design that they believe provides the lowest cost, lowest power processor available today at 333 MHz."

The Press Release also says – and you will be tested on this later – "Using a MIPS32 24Kc core plus Virage Logic's Area, Speed and Power (ASAP) Logic High-Density (HD) libraries and ASAP Memory HD memories in a TSMC 0.13G process, the companies have produced a tape-out ready design for a 333 MHz processor in 3.7 mm2, consuming 166.5 mW and delivering 480 Dhrystone MIPS (DMIPS) performance – a 34% smaller core consuming 37% less power and delivering 20% higher performance than an ARM 1136J-S running at 333 MHz. Portable consumer applications – for which this combination is particularly well suited – will increasingly rely on Java-based applications. The fully-routed 24Kc core with Virage Logic libraries and memories delivers 2,664 CaffeineMarks at 333 MHz."

** Open Core Protocol International Partnership (OCP-IP) announced the availability of CoreCreator 4.0. OCP-IP says that CoreCreator "provides a single graphical or command-line-based environment for validating Open Core Protocol (OCP) implementations. Version 4.0 is fully compliant with, and supports OCP 2.0. CoreCreator 4.0 streamlines generation and packaging of core models, interfaces, timing parameters, synthesis scripts, test vectors, and verification suites necessary for efficient IP core reuse and SoC integration."

"It also provides an environment for stimulating a core (or multiple cores) and analyzing performance and functionality in a system environment. The tool features a comprehensive design environment for importing existing IP cores or creating new IP cores OCP protocol and physical constraint compliance verification; and maximum frequency and gate area estimation. Its automated environment provides configuration, simulation, logic synthesis and timing analysis, as well as TCL scripting for auto-generation of configuration files and timing constraints."

** The Optical Internetworking Forum (OIF) announced that six of its member companies will demonstrate interoperability functionality using the OIF’s recently approved Common Electrical I/O (CEI) Implementation Agreement (IA). The demonstration will take place at DesignCon 2005, and will include Altera, Interconnect Technologies (A Northrop Grumman company), Molex, Tyco Electronics, Vitesse and Xilinx. Test equipment from member companies Agilent Technologies Inc. and Tektronix, Inc. will provide test equipment for the demonstration.

** Pulsic Ltd. announced that it has licensed its Lyric Physical Design Framework to ON Semiconductor. ON Semiconductor says it has licensed Lyric components for "detailed floorplanning, standard cell placement, interactive editing and automatic routing of its next generation of mixed-signal designs."

** QualCore Logic announced immediate availability of 15 silicon-validated analog IP cores and special I/Os for graphics and memory interface applications. The company says that each of these cores was successfully validated in 0.13-micron process technology from two "leading" foundries to reduce risk and accelerate product development of SoC design.

Mahendra Jain, QualCore Logic President and CEO, is quoted: "QualCore Logic’s strategy is to build the largest and most diverse portfolio of silicon-validated analog and mixed-signal IP and special I/Os. These 15 new IP cores bring that number to more than 400."

** Synopsys, Inc. and Grace Semiconductor Manufacturing Corp. announced that Synopsys' Professional Services group and Grace have jointly developed a reference design flow for Grace's 180-nanometer processes. The companies say the RTL-to-GDSII flow is based on Synopsys' Galaxy Design and Discovery Verification platform, and that end-users can download the pre-verified reference flow, which is available immediately from Grace.

** Synopsys also announced that CEVA, Inc. has taped out its next-generation high-speed serial interface chips and the CEVA-Teak DSP using Synopsys' Galaxy and Discovery platforms. The CEVA design team says that Synopsys' convergent flow was the reason for their success. The Flow included Physical Compiler and Astro products, PrimeTime SI tool for signal integrity, Power Compiler, and VCS and NanoSim software.

** Tensilica, Inc. announced that it has based its FPGA prototyping design flow on the Design Compiler FPGA (DC FPGA) tool from Synopsys. Drinks are on the house because, "only DC FPGA supports key design elements of the Tensilica processor. When designers of Tensilica's Xtensa configurable processors want to create an FPGA-based prototype of a SoC that incorporates one or more Xtensa processors before committing to final silicon, Tensilica's patented Xtensa Processor Generator uses the DC FPGA tool to generate an optimized FPGA netlist."

** Tensilica also announced that NVIDIA Corp. has licensed the Xtensa LX configurable processor. The companies say this license will allow NVIDIA to add specialized functions to its outstanding graphics capabilities in new SOC designs.

Frequent keynoter Chris Malachowsky, NVIDIA Co-Founder and Vice President of Hardware Engineering, is quoted in the Press Release: "For the application areas we are targeting, the extensibility and performance of Tensilica’s Xtensa LX microprocessor were key factors in our license decision. We were very impressed with Tensilica’s automated approach for both the processor extensions and the generation of the associated software tools. We are anxious to capitalize on the improved productivity and flexibility that Tensilica’s configurable microprocessor and toolset provides us over our more traditional fixed function, hand-coded implementation techniques."

** Finally, Tensilica announced that LG Electronics has used the Xtensa configurable processor core to deliver what the companies describe as "the world’s first mobile phone capable of receiving digital broadcast signals. Compatible with the Terrestrial digital-multimedia-broadcast (T-DMB) system, a broadcast system currently being rolled out in Korea, the new mobile phone is powered by a sophisticated digital media processor which was designed using the Tensilica Xtensa processor core and design environment. The new LG phone allows consumers to watch television programs, while using normal dialing functions simultaneously. Other mobile devices, such as PDAs, have featured broadcast capabilities, however, this is the first small form factor device to feature both broadcast capabilities as well as dialing functions. The new SOC can also be applied to notebook computers, PDAs and car terminals, speeding the adoption of the T-DMB standard."

** TransEDA announced SystemVerilog support in new versions of its VN-Cover and VN-Check tools. The company says that "by delivering these new versions, TransEDA has met the commitment it made at DAC 04 to provide support for the emerging SystemVerilog standard. SystemVerilog support in VN-Cover, the industry's most accurate code coverage solution, means that designers can take advantage of powerful new SystemVerilog constructs such as enumerated types, records, user-defined types, etc., and still accurately measure code coverage on their design in the same way they do with VHDL and Verilog. Coverage measurement for SystemVerilog/VHDL, mixed-language designs is also fully supported. SystemVerilog support in VN-Check, the configurable rule checker, enables designers to check name and style rules for this language very early in the design flow."

"This extended capability is extremely useful to ease migration of design teams to SystemVerilog and to ensure consistent use of this new language on a company-wide basis. The new version of VN-Check also implements numerous assertion-oriented rules, aimed at helping designers to include assertions in order to correctly cover their designs. Another major enhancement in the new version of VN-Check is the implementation of advanced rules, which are verified using an embedded formal engine."

And the SystemVerilog momentum continues to build steam …