** Cadence Design Systems, Inc. announced that it has donated SystemVerilog data type and IP encryption technology to the IEEE P1800 Working Group. The company says the Working Group will incorporate the Cadence technology in the first release of the SystemVerilog standard, due later this year. Per the Press Release: "These donations enhance the data types that are currently available in SystemVerilog and enable existing encryption technology to be used to encrypt SystemVerilog code, resulting in enhanced language efficiency and usability … The Cadence donation provides enhanced data types that raise the level of abstraction in SystemVerilog, enhancing designer productivity and language usability."

The Press Release adds this notation: "As the initial developer of the Verilog language, Cadence now provides design and verification platform support for SystemVerilog, VHDL, Verilog, PSL/OVL, SystemC, Verilog-AMS and VHDL-AMS. Customers can efficiently run SystemC to verify system function, SystemVerilog and Verilog to verify gate implementation and timing, VHDL for compatibility, PSL for complete assertion-based verification, and AMS for mixed-signal designs. All of these languages now run inside a single simulation interface, allowing customers to use any combination for design and verification to improve language interoperability."

Victor Berman, Director of Language Standards at Cadence and DVCon 2005 Conference Chair, is quoted in the Press Release: "In response to our customers' needs, Cadence is driving support for a single Verilog standard that will give users the benefits of open interoperability, exemplified by our recent donations to the IEEE. Our design and verification platforms, especially the Incisive functional verification platform, are built around open standards that offer customers the flexibility and language choice needed to optimize their verification methodology."

Kevin Silver, Vice President of Marketing at Denali Software, is quoted: "Cadence has leveraged its leadership in language design and hardware implementation, and is providing valuable technology to designers. Cadence's support for SystemVerilog ensures that the Verilog language will remain a unified industry standard. This unification is very important to users.

Reno Sanchez, Director at the Microprocessor Center of Excellence for Xilinx, is also quoted: "We've been successfully using this encryption technology with the Incisive functional verification platform using VHDL, and are looking forward to seeing this capability standardized on by all hardware description languages, including SystemVerilog. This encryption technology will make it easier for us to protect our IP as well as help our customers gain access to a broad portfolio of high-value IP, and do so within an industry standards-based protocol."

** Celoxica announced it is shipping Agility Compiler for SystemC. The compiler includes system design capabilities for synthesis of SystemC models to hardware; it produces IEEE-compliant RTL descriptions as input to various, currently available ASIC/SoC synthesis flows, and then generates gate-level EDIF netlists for what the company describes as "high density" PLDs.

Per the Press Release: "With Agility Compiler, designers can produce working silicon from SystemC models much earlier in the design flow, accelerating system verification and SoC prototyping. The direct path from SystemC to hardware closes a critical gap in the ESL design flow for successful SoC design from system-level models. Agility Compiler synthesizes a complete hardware system with no artificial limitations on design hierarchy, structure, timing or interfaces. Agility Compiler advanced synthesis technology supports multi-million gate designs, multiple blocks and multiple clock domains, easily beating the results of entry-level behavioral synthesis tools that restrict designers to small, single block, single clock domain designs. In addition, Agility Compiler synthesis extracts accurate timing and physical design metrics to support fast cycle accurate simulation and test bench generation for system verification. Agility Compiler's synthesis is driven from pure, standard compliant SystemC descriptions. By avoiding the use of proprietary descriptions or linked constraints, the synthesizable SystemC code remains standard compliant and portable for model and IP reuse. Agility Compiler is fully compliant with the OSCI standard SystemC synthesizable subset."

** CoWare Inc. announced a new option for its SPW 5-XP DSP application solution for Windows that the company says "enables early verification of complex embedded DSP designs." Using the option, designers who are developing DSP applications can reuse their SPW 5-XP reference models for verification of embedded software for TI TMS320C6000 and C5000 DSP platforms developed using TI's Code Composer Studio (CCStudio) IDE. The Press Release describes SPW as "the most comprehensive DSP application solution that bridges the gap from DSP algorithm exploration to implementation into hardware and software."

Also per the Press Release: "The complexity of applications running on TI DSPs is steadily increasing, and although designers can alter TI DSP software after production, it is difficult for them to find bugs if the software is not running concurrently with a transparent testbench. Debugging prior to lab integration is becoming an integral part of the design flow to meet time-to-market requirements, and using physical prototypes is a very time consuming process. An SPW reference simulation offers an easier option."

Jennifer Skinner-Gray, WW DSP Partner Network Manager at TI, is quoted: "The integration between SPW 5-XP and CCStudio provides our catalog customers with greater tool choice, and our premier customers with integration into the market leading design flow centered around the SystemC language."

** Synopsys, Inc. announced a service to allow users of Verisity's Specman Elite testbench product to easily migrate to Synopsys' VCS RTL verification tool. The Native Testbench (NTB) migration service converts Specman Elite verification environments to VCS environments and includes tool, language and methodology training. The Press Release says "the migration from the Specman Elite testbench-only product to the VCS solution with NTB technology allows customers to achieve up to 5X faster verification performance."

Janick Bergeron, Industry Luminary and Scientist in the Verification Group at Synopsys, is quoted: "Creating a sophisticated verification environment requires the most capable bug-finding technologies, the fastest verification performance and a proven methodology based on broadly supported standards. With Synopsys' single-compiler NTB technology and the widely used Reference Verification Methodology, VCS software delivers a powerful verification solution in a single tool."

** Cadence Design Systems, Inc. announced that ATI Technologies Inc. is now using Cadence's new Palladium II acceleration/emulation system to "significantly accelerate" the functional verification of ATI's high-performance digital television (DTV) chip designs.

David DiOrio, Vice President of Engineering at ATI Technologies, is quoted in the Press Release: "We needed to accelerate our verification to continue building the world's most advanced DTV chips. We chose the Cadence Palladium II system for our emulation and acceleration methodology because it was the best tool available from any vendor that delivered the required performance and flexibility that was promised. The Palladium II system provided a single state-of-the art emulation and acceleration verification platform scalable from IP core development to full system-on-chip designs."

** Nascentric, Inc. introduced the Nascim fast-SPICE simulation technology, which the company says is 10x faster than the current generation of fast-SPICE simulators and the first in a series of simulation and analysis products being developed by Nascentric. The company's suite of products intends to focus on transient physical and electrical effects that negatively impact timing, power and signal integrity in nanometer designs, effects such as IR drop, leakage currents, electromigration, and cross-coupling. Nascentric says that Nascim’s current-based transistor models reflect the actual current flow and current density in CMOS circuitry, and enhance overall accuracy when simulating and analyzing nanometer effects.

Per the Press Release: " Its unique, patent-pending approach to simulation includes the intelligent use of multiple evaluation engines, accurate current-based measurement, and efficient storage and transformation of data. Nascentric’s innovative approach to simulation includes the use of multiple engines for device-, topology-, and application-specific evaluations. Optimized for each type of design entity within the circuit (transistor-, interconnect-, cell-, and block-level analysis) the engine-based architecture enables the simulation of nanometer effects with a much finer level of granularity. Nascim takes advantage of the topology of each circuit it analyzes to maximize runtime performance, accuracy, and capacity."

Vess Johnson, President and CEO of Nascentric, is quoted: "Simulating and analyzing current-based nanometer effects has become a critical factor in producing successful silicon. The transient and interdependent nature of these effects requires a transistor-level simulator like Nascim that is accurate and fast enough to make dynamic, full-chip simulation of nanometer effects possible."

** Sandwork Design, Inc. announced that its analog and mixed-signal circuit debugging tools have been incorporated into the design flow of ON Semiconductor Inc.'s design centers. Jo Hamid, Vice President R&D and Europe R&D Director at ON Semiconductor, is quoted: "The availability of a Spice-centric productivity solution that complements all of our fast-Spice simulation flows is an attractive step towards tightening our analog mixed-signal design turnaround time. Beyond implementing ways to shorten simulation cycles, we have realized further time savings by providing our designers with the novel waveform analysis capabilities of WaveView Analyzer."

** Synopsys, Inc. announced that Aarohi Communications, Inc. is now using Synopsys' VCS RTL verification tool for the functional verification of Aarohi's "next-generation" FabricStream intelligent storage product.

Kaushik Patel, Vice President of Hardware Engineering at Aarohi, is quoted: "VCS – our longstanding choice for simulation – now gives us a fully integrated RTL verification solution in a single tool. We have successfully migrated our existing verification environment to the VCS solution with NTB and are using it on our next-generation chip project. Synopsys' VCS NTB capability increases our engineering productivity by providing one integrated solution to power our verification environment, as compared to using multiple tools with our earlier projects."

** Synopsys, Inc. also announced that NetSilicon, Inc. has had "first-silicon success" using Synopsys' Vera testbench automation tool and the VCS RTL verification tool as part of NetSilicon's NS9750 NET+ARM processor verification environment.

Brad Hollister, Verification Lead at NetSilicon, is quoted: "After evaluating available testbench solutions on the market, we selected the Synopsys Vera tool because of its superior capabilities for constrained-random stimulus generation, ease of adoption and evolutionary path to VCS Native Testbench technology. Even though this chip was more complex than our previous projects, it was functionally correct on first silicon. Doing this project without the Vera tool would have likely required at least twice the number of people and twice the elapsed time."

** TransEDA announced Expression Coverability Analysis, which the company says provide "automatic in-depth analysis of conditional expressions for designs written in Verilog, VHDL and mixed languages and, [therefore] guides the user on the quickest route to full condition coverage. [Using an embedded formal engine], uncoverable expression terms, and coverable terms that have not been exercised, are quickly identified. After confirmation, uncoverable expression terms are reported and eliminated from the overall coverage calculation. Diagnostic information, including VCD files, is generated for currently uncovered, but testable sub-expressions. Quick isolation of unreachable expression terms allows engineers to achieve faster convergence to full Focused Expression Coverage."

The Press Release says: "Measurements of statement and branch coverage are no longer considered sufficient for the verification of HDL design representations. Because code coverage is very sensitive to RTL writing style, the same functionality written in different ways can give different coverage results depending on the style in which the code is written. As a consequence, achieving even 100% statement and branch coverage does not ensure that a design has been sufficiently exercised. In order to improve confidence in coverage measurement, best practice now demands the use of coverage for expressions in conditional statements, which means performing coverage analysis at a greater level of detail … Using technology that has been proved by aerospace industry experts to be equivalent to Modified Condition/Decision Coverage (MC/DC), TransEDA’s established Focused Expression Coverage (FEC) metric delivers this ultimate level of accuracy in coverage measurement."

** Mentor Graphics Corp. announced that LSI Logic has licensed Mentor’s 10/100/1000 Ethernet Media Access Controller (MAC) IP core.

Per the Press Release: "The core has been proven in silicon and has been pre-verified and tested for easy integration into SoC designs … Mentor Graphics acquired the complete line of Ethernet IP from Alcatel in July 2003. Mentor has enhanced and grown the product line since its acquisition with the addition of new features and product offerings such as the M-SGMII Serial Gigabit Media Independent Interface (M-SGMII) core. Mentor IP is silicon-proven in multiple process technologies, and is currently used in 10/100 Mbit/s ports and Gigabit Ethernet ports shipping worldwide."

Terry Pence, Communications Marketing Manager at LSI Logic, is quoted: "This IP from Mentor Graphics meets our stringent criteria, and we are pleased to offer versions based on this industry-leading core to our mutual customers for both ASIC and RapidChip Platform ASIC implementations."

** Virtual Silicon Technology, Inc. announced what the company describes as "the industry's first fully integrated Digital Frequency Synthesizer (DFS). This Delta-Sigma Fractional-N Phase Locked Loop (PLL) product allows the SoC designer to synthesize the exact output frequencies to suit an individual project. The Virtual Silicon DFS includes the first Delta-Sigma Fractional-N PLL IP for the generic CMOS market. There is no special processing for mixed-signal circuits. The DFS has the widest frequency range available - 1-300MHz input and 88kHz to 3000MHz output - and multiplies a clock input by 0.50000 to 999.99988, providing the ability to use any crystal to get any frequency, reducing crystal inventory and material costs. The Virtual Silicon DFS is also the first product to provide flexible Fractional-N frequency multiplication and Clock Deskew in one PLL, further reducing IP purchasing challenges and inventory."

Barry Hoberman, CEO of Virtual Silicon, is quoted: "The Virtual Silicon programmable DFS provides a designer the ability to use any crystal to generate any frequency using generic CMOS process technology. This high level of reconfigurability and flexibility delivers real benefits of reduced inventory and delivery time and a lower bill of materials cost to the SoC designer."

Edward Wan, Senior Director of Design Service Marketing at TSMC, says things are deep and wide: "Virtual Silicon's DFS PLL product continues the collaboration between Virtual Silicon and TSMC. Their new IP provides robust solutions to our customers, and adds to TSMC's IP portfolio, which is the broadest and deepest in the industry."

** Anadigm announced AnadigmDesigner2 version 2.5, which the company says features for greater flexibility in designing and prototyping FPAAs and allowing the use of lower-end microcontroller companion devices in FPAA implementations. A new Visual C++ Prototyping tool in this version makes it easier to dynamically reconfigurable FPAAs using the AnadigmVortex development system. Also, the new user interface includes improvements to the CAM browser and handler, and to the AnadigmFilter tool, which allows users to create custom filters by manually moving pole and zero positions.

Bill McLean, CEO of Anadigm, is quoted: "We’ve demonstrated a continued commitment to enhancing our AnadigmDesigner2 EDA tool suite, making it increasingly easy to use and flexible enough to handle a wide variety of applications in the audio, RFID, industrial, and medical industries, to name a few. From our customers’ point of view, this new version of AnadigmDesigner2 represents a major advance for both prototyping FPAAs and reducing cost of ownership for production designs."

** Test **

** LogicVision, Inc. announced that Open-Silicon is using LogicVision’s embedded memory-test and repair-analysis technology as part of its standard tool flow in ASIC designs. Additionally, the companies announced that LogicVision intends "to collaborate with Open-Silicon to add automatic memory repair to Open-Silicon’s tool flow."

Jim Healy, President and CEO of LogicVision, is quoted: "Our technology is designed to efficiently and economically fully test Open-Silicon’s ASIC designs at-speed and uncover those illusive un-modeled faults that are often the cause of low yields and customer field returns."

Satya Gupta, Vice President of Engineering for Open-Silicon, is also quoted: "Through our OpenMODEL, we seek to bring the best of all design methodologies to the table. LogicVision’s solutions will ensure that our customers reap benefits in both cost savings and time to market."