** Z Circuit Automation, Inc. announced ZChar, which the company says is a tool for "fast, automatic characterization of digital cell libraries which is essential to the success of an integrated circuit, particularly in the areas of timing closure and power consumption."

After a lively conversation with the folks from Z Circuit last Thursday, I decided to include whole chunks of their Press Release out of respect to their tenacity and good cheer in enduring my cross-examination.

First, Karen Bartleson, Director of Interoperability at Synopsys, is quoted in the Press Release: "Designers are able to develop their chips more quickly and accurately when they access up-to-date, accurate models for their technology in the Liberty format. Z Circuit's active participation in Synopsys' TAP-in program has enabled them to leverage Liberty, one of the most successful interoperability standards in EDA."

Then, Jim Thomas, Vice President of Product Development at Spansion LLC, is quoted: "ZChar provides us with very fast turnaround time. It quickly generated three full corners in a weekend, including 120 flip-flops, for our advanced 90-nanometer Flash memory process. The Z Circuit software and training has been instrumental in upgrading our digital design environment to compliment our existing, state-of-the-art analog and Flash memory design capabilities."

Finally, Edmond Macaluso, President of Z Circuit Automation, is quoted: "Based on our many years of experience with cell library development, we built ZChar to improve library developers’ efficiency through a new generation of technology which makes the library characterization task much simpler, provides fast turnaround time, and monitors output results for correctness. Our fast turnaround time, including advanced parallel-processing capabilities, makes it possible to re-spin a library quickly or build custom corners, critical to accurate timing signoff."

"As feature sizes shrink to 0.13 microns and below, design teams require more corners and more complex timing and power models. Characterization of a large cell library can contain over a million data points and require thousands of simulation hours, leading to a very slow turnaround time for producing library models. A library will need to be characterized for changes to process models, cell layouts, spice models, voltage thresholds, or if a custom corner at a special voltage is required. Without correctly characterized libraries, the entire design project and millions of dollars in design and fabrication time may be at risk. Designing at the wrong environmental corner or not taking advantage of a special operating voltage, may lead to a slower, larger design that wastes power or takes much longer to close timing. In many cases, a company does not need to build a library from scratch, but instead can reap many benefits by using ZChar to re-characterize the library to the appropriate conditions."

"At 90-nanometer geometries and below, speed and power consumption are much more sensitive to environmental conditions including voltage and noise. Therefore, producing accurate models at the appropriate conditions is critical to achieving design success. ZChar quickly generates accurate and complete timing/power models and incorporates unique methods for noise immunity and signal integrity to avoid design problems that otherwise might not be detected until failure analysis. Z Circuit keeps complex model generation methods up-to-date through customer requirements and tracking technology changes. As an active member of Synopsys’ Tap-in and Cadence Connections programs, Z Circuit works closely with leading EDA companies to incorporate the industry’s latest standard formats, such as Synopsys Liberty."

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** Zuken says it has lunched "CADSTAR Bundles" expressly for the Americas, which aim to provide "essential functionality at reduced prices. In recognition of the unique competitive nature of the EDA market in the Americas. Zuken has improved its value proposition with a Basic and Professional bundle, offering even greater value at more competitive prices." The Basic Bundles contains "all the necessary tools to design a PCB from concept through to final manufacturing output." The Professional Bundle is for high-speed PCB design applications from the design through to the manufacturing process.

** Royal Philips Electronics and Xilinx, Inc. demonstrated what the companies are describing as "the world's first programmable PCI Express endpoint silicon solution offered at a much lower cost than traditional solutions. The Philips-Xilinx programmable PCI Express solution costs less than $15.00 USD (in high volumes)."

Keith Odom, Director, Engineering Architecture and Technology at National Instruments, is quoted: "The Philips-Xilinx programmable PCI Express solution is making it possible to develop a cost-effective, PCI Express compliant card in significantly less time. Further, the programmable flexibility allows National Instruments to use this solution in multiple product offerings which greatly leverages development time and lowers costs."

Paul Marino, General Manager and Vice President for Business Line Connectivity at Philips Semiconductors, is also quoted: "This new PCI Express solution draws on the expertise of two industry leaders that enables manufacturers to bring a wide variety of video and audio applications to consumers everywhere. Working with Xilinx, we offer a flexible, two-chip solution to customers who are looking to take full advantage of the simple, fast connection applications PCI Express will bring to the connected consumer."

** Virtio Corp. says it has introduced a Linux version of its Virtual Platform technology. The company says that by porting the technology to Linux, it has "opened the door to closer integration between hardware and software development efforts."

Filip Thoen, CTO at the company, is quoted: "Integration issues are driving the synchronization of hardware and software development down to the RTL level, but typically EDA tools run under the Linux OS. This introduction marks the first time that functional models are available to the Linux community, allowing software and hardware developers to collaborate and use the same workstations."

** Synplicity Inc. announced AccelArray Pro, a new member in the Amplify family of structured/platform ASIC products. The company says the new product has received full qualification from Fujitsu Ltd. (Fujitsu) and Fujitsu Microelectronics America Inc. (FMA). Per the Press Release: "Fujitsu and FMA will recommend Amplify AccelArray Pro as the physical synthesis solution for design and development of its AccelArray platform ASIC devices upon production release of the product."

In addition, Fujitsu and Synplicity say they have worked closely since their joint development agreement was announced in September 2004 "to develop custom physical synthesis uniquely targeting Fujitsu's AccelArray platform ASICs. This customized version of Synplicity's software enables AccelArray customers to obtain greater performance, improved densities and faster overall timing closure. With this announcement, Synplicity has now received qualification of its structured/platform ASIC physical synthesis software tools from the three leading structured and platform ASIC device suppliers: Fujitsu, LSI Logic, and NEC Electronics."

** Synopsys, Inc. and Tower Semiconductor Ltd. announced that Tower's in-house set of 0.18-micron standard cells, I/Os and memory libraries are now available through Synopsys' DesignWare Library. The Press Release adds: "As a result, more than 25,000 DesignWare Library licensees now have access to Tower Semiconductor's 0.18-micron libraries, at no additional charge, for use in complex SoC designs. Starting in the third quarter of this year, licensees are expected to have access to Tower's 0.13-micron libraries. The 0.18-micron libraries include a complete set of views fully validated in silicon in high-volume production, as well as views for third-party EDA tools. The library distribution agreement with Synopsys also includes the future distribution of Tower's 0.13-micron libraries through the DesignWare Library."

Alan Tsun, Vice President of ESP Development Engineering at QuickLogic, is quoted: "Including the Tower library in the DesignWare Library means our designers will have easy library access with effective support and regular updates. This greatly simplifies our IP procurement and administrative processes."

** Mentor Graphics Corp. announced that its MPCIExp Configurable Port is compliant with the PCI Express specification from the PCI-SIG. The company says it has demonstrated that the Configurable Port works successfully with Rambus’ Physical Layer (PHY) IP.

Tony Pierce, PCI-SIG Chairman, is quoted: "Mentor has demonstrated the value of the PCI-SIG compliance program by successfully testing the interoperability of its MPCIExp-CP IP product. Compliance will enable Mentor’s customers to quickly implement the development of their systems based on the PCI Express specification."

** Magma Design Automation Inc. announced that it has "expanded" its relationship with NEC Electronics to include a new, multi-year license agreement. The companies say NEC will "expand its deployment" of Magma software and the two companies will collaborate on several technology development initiatives going forward, including work a 65 nanometers. The agreement is described as building "on an engagement announced in 2004 in which NEC Electronics began deploying Magma's complete line of IC implementation software, including Blast Create, Blast Plan, Blast Fusion, Blast Rail and Blast Noise, to its worldwide design teams and design centers."

Kazu Yamada, Associate Vice President for the Technology Foundation Development Operations Unit at NEC Electronics, is quoted: "Magma's unique approach to IC implementation – true concurrent optimization with a unified data model and a single executable architecture – has enabled our design teams to complete many difficult designs in a short time and meet our customers' requirements. We are achieving higher productivity and producing better-quality chips."

** LogicVision, Inc. announced its Embedded SerDes Test (EST) product, which the company says will be available in June 2005 as part of the company’s LV2005 product release. EST is designed to provide "test accuracy equal to or higher than that available on the highest performance and highest cost external equipment. However, EST can be used with any high or low cost tester. This capability combined with millisecond test times, results in dramatic test cost savings. EST is the only proven high performance embedded test solution introduced in the market."

Get down and get technical: "High speed serial I/O technologies, typically known as SerDes I/O, are being rapidly adopted in data storage, telecommunications and personal computer applications. This is because they offer a reliable, low power and high data bandwidth capability using low-cost backplane and connector technologies. Significant test challenges are emerging as multiple SerDes channels with data rates of between 1 Gbps and beyond 10 Gbps are being integrated into SoCs and FPGAs. IC manufacturers are finding it increasingly expensive and time-consuming to guarantee all of the critical signal integrity parameters of these high-speed I/O devices, especially while ramping-up yield."

"LogicVision’s EST product provides a comprehensive structural test solution for measuring the key parameters required to ensure the performance and quality of these high speed I/O circuits. The new technology includes a suite of very high precision signal integrity tests including jitter, jitter tolerance, duty cycle and rise/fall times. All of these tests have sub-picosecond accuracy, run in milliseconds, and can be run using any external test equipment. An advanced release of EST is already in the field with industry recognized companies, and has been successfully verified with SerDes channels running over 10 Gbps."

** Lattice Semiconductor Corp. and Synplicity Inc. announced a development and marketing agreement to "enhance and promote" Lattice's FPGA device performance in Synplicity's Synplify Pro FPGA synthesis tool during the second half of 2005. The companies say the agreement calls for "significant enhancements, including register re-timing, pipelining, and memory inferencing, to strengthen current support for Lattice FPGAs. The Synplify Pro software currently supports all Lattice digital PLDs."

Chris Fanning, Vice President of Software at Lattice, is quoted: "We are confident that Synplicity will deliver considerably improved performance and support for Lattice FPGAs, and that our customers will benefit greatly from Lattice and Synplicity's expanded relationship."

Joe Gianelli, Vice President of Business Development at Synplicity, is also quoted: "This agreement reflects our unqualified commitment to deliver unprecedented device performance for Lattice FPGA products in our Synplify Pro software. Performance is a hallmark of Synplicity's synthesis tools, and we are eager to continually expand and improve our support for Lattice FPGAs."

** Incentia Design Systems, Inc. announced that VIA Technologies has "extended its relationship" with Incentia to include logic, DFT, low power, and physical synthesis, as well as timing analysis and debugging software. The companies say the new agreement is for multiple licenses for use at VIA’s sites in Taiwan, China and the USA.

Bauli Yang, Manager of VIA, is quoted: "Incentia has kept pace with the technology hurdles we face and our customer requests. We have had success with Incentia’s synthesis and timing products, and are pleased to add additional licenses and new options to our worldwide design sites."

** Forte Design Systems and Oki Electric Industry Co., Ltd. announced that Oki has selected Forte's Cynthesizer behavioral synthesis product for use in designing its next generation SoCs.

Kazuhiko Maki, Silicon Platform Design Department Senior Manager at Oki Electric, is quoted in the Press Release: "It has been a challenge to convert SystemC to RTL in a short period of time with low power consumption for our mobile application designs. During our testing, Forte's Cynthesizer proved it produces a gate area that is equivalent to RTL conversion done by hand, as well as reduce development time and power consumption. Going forward, we will provide low power, high quality, and short time-to-market products to our customers by using Cynthesizer in our system LSI development; we plan to incorporate Cynthesizer into our standard design flow in the fiscal year ending March 2006."

** Concept Engineering GmbH announced the availability of a product that the company says "improves transistor-level debugging and optimization for IC and SoC designers, who are using the Virtuoso Schematic Editor environment from Cadence Design Systems, Inc. The new product, which Concept says it developed as a member of the Cadence Connections program, is an option to Concept’s SpiceVision PR, and is based on SKILL. SpiceVision PRO automatically creates easy-to-read circuit schematics from both pre- and post-layout transistor-level structures (Spice netlist descriptions). A schematic interface to the Cadence environment using SKILL enables mutual customers to easily process design data. For example, designers can now easily simulate a critical path at the transistor level. The path is created using SpiceVision PRO and is exported into the Cadence Virtuoso Schematic Editor environment."

SKILL is described as "a language developed by Cadence that enables users to customize the Cadence technology and to create interfaces with external tools that work with the Cadence environment. Once schematic fragments are imported into the Cadence environment, designers can use the schematic fragments to perform transistor-level debugging and optimization. Surrounding circuit structures do not affect the schematic fragments during debugging, so simulation takes less time to complete. "

Gerhard Angst, President and CEO at Concept, is quoted: "SpiceVision PRO and the new SKILL interface help with this process."

** Celoxica Ltd. and the Japan Advanced Institute of Science and Technology (JAIST) say they have developed a high-speed digital watermarking detection system with real-time operation across the Internet. The organisations say the joint research project used ESL design and C-based synthesis to "accelerate watermarking algorithms in a hardware co-processor. The project resulted in a low-power solution that runs detection scanning 148 times faster than software only configurations. The complex algorithm design was implemented using Celoxica’s DK Design Suite of ESL tools and RC Series hardware platforms."

Please note: "Digital watermarking is increasingly being used in response to the escalating misuse, and illegal copying and distribution of multimedia content. Digital watermarks embed hidden data into digital content or media. These watermarks contain copyright information identifying the origins, ownership and authenticity of the content. The research project at JAIST developed an accelerated watermarking solution for audio content. The project increased detection efficiency and implemented multiple watermarks in parallel using hardware co-processing."

Yasushi Inoguchi, Associate Professor at The Center for Information Science at JAIST, is quoted: "Digital watermark detection by software alone is too slow and power hungry, and it cannot catch illegal audio files that are exchanged over the Internet," said. "Using C-based design and synthesis technology we were able to easily capture the complex watermarking algorithms and accelerate the watermark detection scheme in a co-processor, exploiting the power and performance benefits of programmable hardware."

About JST – Japan Science and Technology Agency's mission is to promote science and technology in Japan by conducting a broad range of activities, including 1) Promotion of consistent research and development from basic research to commercialization with particular emphasis on the creation of new technological seeds, 2) Upgrading the infrastructure for the promotion of science and technology, including dissemination of scientific and technological information.

** Applied Wave Research, Inc. announced the AWR SI 2005 design suite, which the company describes as the industry's first cross-domain signal integrity (SI) solution specifically developed for designing and analyzing high-frequency, high-speed electronics circuits.

Per the Press Release: "Engineers can now identify, analyze, and fix signal integrity issues early in the design cycle, ensuring that their designs work correctly the first time and speeding time to market. This powerful new software suite combines the unique AWR Design Environment and unified data model with a signal integrity analysis environment, providing comprehensive, easy-to-use analysis capabilities that work seamlessly in one unified platform. The solution supports multiple process technologies, enabling concurrent design and signal integrity analysis of complex interconnects spanning chip, package, module, and printed circuit board (PCB) design boundaries."

AWR SI 2005's signal integrity analysis capabilities are built on top of the company's Analog Office Intelligent Net (iNet) technology, and includes support for multiple, electromagnetic (EM) simulation and analysis tools, as well various modeling formats such as SPICE netlist, IBIS models, and S-parameter blocks. AWR's harmonic balance simulator is integrated with Synopsys' HSPICE.

** Aldec, Inc. announced the release of Riviera 2005.04, which the company says includes a new system-level simulation engine and improved SystemC debugging. The new release also includes new simulation technology designed for use in system-level verification. Per the Press Release: "The System-Level Platform (SLP) incorporates a completely redesigned simulation engine that dramatically reduces simulation run times for gate-level and timing verification. This new simulation technology integrates seamlessly with the current environment and is completely transparent to the designer. Riviera with SLP will simulate any designs containing Verilog netlists and automatically distribute simulation tasks between the new SLP engine and the standard simulation engine. In addition to the Verilog performance, the new release has decreased VHDL timing simulation runtimes by as much as 3X through further optimization of the VITAL libraries."

Eric Seabrook, Director of Marketing at Aldec, is quoted: "The increased Verilog and VHDL simulation performance of Riviera 2005.04 will provide an enormous gain to our already industry standardized simulation performance. Adding the improvements for co-simulation with SystemC and MATLAB provides a completely new level of support from Aldec for system-level design." Surely this is good news.

** AccelChip Inc. says it is the industry’s first company to provide fixed-point linear algebra IP as stand-alone RTL cores. Currently available products are provided in the company's new AccelCore product line and include matrix inverse and factorization cores used in applications such as beamforming, software-defined radio, radar/sonar, Kalman filtering, and other wireless applications.

Per the Press Release: "Until now, performing matrix factorization and inversion in hardware has been difficult because the algorithms are complex and highly sensitive to numerical problems, particularly when using fixed-point arithmetic preferred in high-performance ICs. As a result, most designers have been compelled to implement these linear algebra algorithms in C on DSP or general-purpose processors. The demands of new linear algebra applications are increasing the demand for IP cores that can achieve higher performance and reduce form factors attainable by integrating DSP capabilities in FPGAs and ASICs."

Michael Bohm, CTO and Vice President of Engineering at AccelChip, is quoted: "Matrix factorization and inversion are used with algorithms utilizing linear algebra techniques, such as adaptive filters, which are used in a wide range of applications from radar to global positioning. AccelCore IP cores are off-the-shelf, pre-verified DSP cores that negate the need for designers to write their own core in VHDL or Verilog, then build a testbench to verify the model. AccelCore matrix cores are truly the first of their kind in the industry, and they can save customers months of RTL coding."

And surely, time saved is money earned.