Aldec, Inc. and Magma Design Automation Inc. announced availability of a design flow interface between Active-HDL 6.3 and PALACE version 2.4. The companies say "the integration of the two products automates the data exchange of graphical design capture, mixed VHDL and Verilog verification and physical synthesis providing an efficient, easy-to use solution for Actel, Altera and Xilinx designs."

Eric Seabrook, Product Marketing Manager for Aldec, is quoted: "The interface between Active-HDL and PALACE provides complete design flow management of large FPGA and PLDs, independent of the architecture. As designs continue to grow in complexity and FPGA users are becoming faced with the challenge of ASIC like flows an automated data exchange between the tools becomes increasingly important."

Behrooz Zahiri, Director of Product Marketing at Magma, is also quoted: "Aldec provides FPGA designers with a highly integrated environment to capture and verify designs. Through Magma’s and Aldec’s collaboration, FPGA designers familiar with the Active-HDL verification and design flow can now take advantage of PALACE’s advanced physical synthesis and speed-grade improvements."

Applied Wave Research, Inc. (AWR) announced that Silicon Laboratories, Inc. has adopted AWR's Microwave Office and Visual System Simulator (VSS) design suites. The companies say Silicon Laboratories teams will use the AWR software to simulate RFIC chips and modules. James Spoto, President and CEO at AWR, is quoted: "AWR is proud that its next-generation design software meets the exacting requirements of Silicon Laboratories’ world-class engineering team, which has unsurpassed expertise in mixed-signal technology."

Bluespec Inc. and Novas Software, Inc. announced that the companies have created "the first debugging environment for behavioral synthesis that allows hardware design engineers to easily debug high-level, untimed, behavioral source code. Resulting from collaborative efforts enabled by the Novas Harmony partner program, the debugging environment allows interactive cross-probing and communication between Bluespec's Blueview design visualization tool and the Novas Verdi Automated Debug System. This integrated solution reduces time spent tracing causes during debug, and is a major improvement over debug flows associated with previous behavioral synthesis approaches."

George Harper, vice president of marketing at Bluespec, is quoted: "Designing at higher levels of abstraction addresses the growing cost of design and verification. Our Novas partnership enables this by ensuring that designers can effectively debug high-level untimed behavioral descriptions using their favorite tools and environments."

David Kelf, Vice President of Marketing at Novas, is also quoted: "The trend toward larger, more complex designs continues to drive EDA innovation, and high-level synthesis represents a promising approach to effectively tackle several significant design challenges. By partnering with Bluespec, we have extended our debug system to let mutual customers effectively comprehend and analyze abstract source code targeted at this methodology."

Cadence Design Systems, Inc. announced what the company calls "substantial enhancements to its market-leading Encounter Conformal technology. Encounter Conformal 5.0 helps customers with enhanced verification capability to insure that the tapeout accurately reflects design intent. Important new capabilities in Conformal 5.0 include FPGA support, clock domain checking and advanced datapath verification."

"Conformal technology now extends equivalency checking to FPGA prototypes through the Synplicity design flow to Xilinx devices, with support of Altera devices to follow. The product also addresses the rapid increase in the number and complexity of clock domains with formal verification of clock domain crossings. This release of Conformal features SystemVerilog support, complex datapath verification enhancements, and across-the-board equivalence checking capacity and performance improvements." Good news.

Cadence Design Systems and Chartered Semiconductor Manufacturing announced that the companies have "jointly qualified the Cadence Fire & Ice QX cell-based extraction tool for Chartered's advanced nanometer processes." Not surprisingly, the companies add that "by integrating Fire & Ice QX into the Chartered-Cadence digital IC reference flow, companies can shorten the time from chip design to volume production." Also good news.

Kevin Meyer, Vice President of Worldwide Marketing and Services at Chartered, is quoted: "Collaboration with Cadence enables us to service mutual customers with faster access to pre-qualified technology files and broader support across Chartered's advanced process platforms. By qualifying Cadence Fire & Ice QX to help streamline the design-through-manufacturing flow, companies can predict with greater accuracy the silicon performance of their designs prior to tapeout."

CoWare, Inc. and Forte Design Systems announced what the companies call "the first integrated SystemC-based solution for ESL design to implementation. The tight integration of CoWare's SystemC-based ConvergenSC SoC design tools and Forte’s Cynthesizer SystemC behavioral synthesis product unites system architecture, simulation, and synthesis in a first-of-its kind flow. Users can explore and validate a design's system architecture in CoWare’s ConvergenSC, then synthesize to RTL using Forte's Cynthesizer, and verify the RTL in a system context with the same SystemC model."

Mark Milligan, Vice President of Marketing at CoWare, is quoted: "By joining forces with Forte, ConvergenSC and Cynthesizer will help ease the adoption of ESL methodologies for our customers. We are proud to partner with the leader in behavioral synthesis to deliver this solution."

Brett Cline, Vice President of Marketing at Forte, also believes customers will be happy: "By partnering with the industry leader in system-level design, our customers have access to a more complete SystemC design environment to ease adoption and allow them to realize the benefits of ESL design faster."

eSilicon Corp. announced that it has "successfully collaborated with Aarohi Communications and Synopsys in the tapeout of a complex chip design with subsequent first-pass functional silicon. The successful three-way effort represents the most comprehensive effort by eSilicon to date, and illustrates the momentum of the company and its Intelligent Design and Manufacturing business model."

The companies say the joint effort led to a "highly complex SoC containing over 100 million transistors, with over 9 million logic gates, 12 Mbits of memory and multiple I/O voltage levels."

Magma Design Automation Inc. announced that a "fully-validated RTL-to-GDSII design enablement kit for the IBM-Chartered Semiconductor Manufacturing jointly developed 90-nanometer process platform is now available online." Magma has undoubtedly noticed what everyone has also seen – a closely integrated effort between IBM East Fishkill foundry and Chartered's Fab 7 in Singapore. The kit includes technology files, a methodology guide and scripts and Magma-qualified libraries.

Kevin Meyer, Vice President of Worldwide Marketing and Services at Chartered, says it all: "Our comprehensive process offering with IBM at 90 nanometer - combined with Magma’s integrated, yet open design system – provide an effective solution that is available now to meet the requirements of products ranging from wireless mobile to high-performance networking. We’re very impressed with the technical expertise of the Magma team and with the speed at which the design enablement kit was developed."

PolarFab and Mentor Graphics Corp. announced the availability of a "production-proven" design kit (DK) which supports the PolarFab PBC4 BCD process technology. The DK is available for use with Mentor's Analog/Mixed-Signal (AMS) IC Design Flow. There's additional good news in that Apogee Technology Inc. says the company has taped out their next generation mixed-signal chip using the PBC4 kit.

Mentor Graphics Corp. also announced the availability of two new iSolve speed adapters from its family of emulation products supporting the USB and PCI Express industry standard protocols.

Per the Press Release: "The iSolve USB and PCI Express speed adapters provide a rapid path to system verification by creating an environment that combines real USB or PCI Express hardware and applications software, together with the SoC or ASIC design in a hardware emulator. As a result, corner-case bugs in hardware and software can be identified and fixed. Design teams can then address important interoperability and compliance issues that occur with new and evolving bus protocols. The iSolve solutions give designers the confidence in running billions of real world cycles on their SoC design before tape-out, meeting customer delivery schedules and financial returns."

Mentor Graphics Corp. announced, as well, a collaboration with Xilinx to supply Expedition and PADS users with reference data, "which allows them to more efficiently implement the multi-gigabit transceiver (MGT) technology available in Xilinx advanced FPGAs on their PCB designs. To ensure optimal multi-gigabit interconnect implementation, Mentor Graphics has teamed up with Xilinx to provide the Virtex-II Pro RocketIO MGT characterization board reference design for the PADS and Expedition product families." Turned out that was a good idea.

Henry Potts, Vice President and General Manager in the Systems Design Division at Mentor Graphics, is pleased for the customers: "The Xilinx reference designs enable our Expedition and PADS customers to accelerate their design process, improve design quality and achieve optimal system performance. Today, system designers are faced with significant chip to board implementation challenges, such as increased FPGA densities and speeds in the multi-gigabit per second ranges. These reference designs enable easy integration of complex FPGAs onto the PCB."

Synopsys, Inc. said that Micron Technology, Inc. has chosen Synopsys' SiVL silicon-versus-layout software to help implement its advanced DRAMs, flash memories, CMOS image sensors, and other semiconductor components. Micron selected the SiVL software, a component of Synopsys' DFM solution, because of its ability to catch "critical lithography errors prior to tapeout improving manufacturing efficiency at advanced technology nodes such as 90-nm and below." I would certainly hope so.

Tom Kingsley, Product Marketing Manager for Lithography Verification at Synopsys, is pleased: "The rapidly expanding use of RET in the 90- and 65-nanometer nodes dramatically increases the chances of killer lithography-related defects going undetected. The SiVL software helps finds these defects thereby preventing costly time-to-market delays and enabling RET closure. The importance of verifying that a chip will print to silicon correctly is one more way Synopsys DFM solutions help customers achieve manufacturable designs and accelerate their time to yield."

Synopsys and KLA-Tencor announced that they are "collaborating to develop a compact yield analysis and modeling system for Toshiba Corp. The new modeling system will enable Toshiba to improve parametric yields on its most advanced sub-100-nm SoC products by predicting the impact of process variations on final device performance as they occur during large scale integration (LSI) production. According to Toshiba, an important goal of this joint project is to enable improved information sharing between its IC design and process engineers in order to accelerate the company's advanced process development and yield ramp efforts. Toshiba will install the new modeling system at its 300-mm production facility in Oita, Japan, for use in both low- and high-volume SoC manufacturing." Look for more news regarding all of this going forward.

Tensilica, Inc. announced that the Seiko Epson Corp. has licensed the Xtensa configurable processor. Epson's engineers say they are using Xtensa processors in next-generation imaging products.

Katsuhiko Nishizawa, General Manager of IJP Design Department of Imaging & Information Product Division at Epson, has the last word: "We evaluated a number of emerging processor technologies and we selected Tensilica's configurable Xtensa architecture. We plan to use multiple Xtensa processors that we can specifically tailor for our exact applications."