Cadence Design Systems, Inc. announced the Allegro PCB SI 630 PCB design tool, which has been optimized for scattering parameter (S-parameter)-based interconnect characterization. The new release includes technology for high-capacity simulation of serial links in PCI Express, XAUI, Serial ATA II, Infiniband and other interface standards that operate at or above 2.5 gigabits per second. The company says Allegro PCB SI 630 has been added to the Cadence Allegro system interconnect design platform, and "delivers an integrated design and analysis environment for designing complex digital PCB systems with MGH signals."

Here’s the technology primer from the Press Release: "As data transfer rates increase, effects of discontinuities in the signal path can linger for many transfers and must be studied in detail to ensure timing and voltage margins are met. The Allegro PCB SI 630 solution enables detailed analysis of millions of data transfers on the board, across multiple boards, and across silicon-package-boards with unprecedented performance. It is the first commercially available product on the market with high-capacity simulation (channel analysis) technology that can simulate 10,000 bits in seconds."

Cadence Design Systems also announced the release of the Allegro Design Workbench software suite, which the company says is a new family of products for the Allegro system interconnect design platform that uses MatrixOne, Inc. product lifecycle management (PLM) technology.

Per the Press Release: "The delivery of this software suite, which can boost engineering productivity up to 50 percent, marks the formal entry by Cadence into the collaborative design and library data management market. Electronic design engineers throughout the design chain will benefit from the existing Cadence and MatrixOne alliance that brings tightly integrated technology from both companies into the Allegro Design Workbench. In contrast to competitive products in the market, this integrated solution is specifically designed for board design groups, enabling cross-team collaboration plus design and library management."

Surely all of this good news is only enhanced with the purchase of Synchronicity by MatrixOne, announced at DAC. Who knows what further good news will result from integrating these technologies?

Emulation and Verification Engineering (EVE) announced the ZeBu-XL high-end prototyping platform for large SoC designs. The new platform includes multiple new features including automated design mapping and the ability to support interactive hardware debugging. The platform, per the company, is "priced at pennies per gate." I saw the system at DAC and it’s pretty darn cool.

ZeBu-XL is compatible with previous generations of EVE's ZeBu-ZV hardware-assisted verification platform and associated software, but includes a 30x increase in capacity from one-and-half million ASIC gates for a single ZeBu-ZV board to 48 million gates for ZeBu-XL, and the system runs at MHz speeds. EVE reports that one project team (as yet, unnamed) is currently using a fully configured version of ZeBu-XL on a complex processor design.

Per the Press Release: "It is a high-speed, high-capacity prototyping platform based on the latest Xilinx Virtex-II 8000 field programmable gate arrays (FPGAs). It boasts the industry's largest capacity with up to 64 FPGAs, corresponding to 48 million ASIC gates in a single 19-inch rack box. It also rates a maximum performance of 30MHz in stand-alone or in-circuit emulation modes, with a memory capacity of up to 1.5GB."

"Integrated with the most popular FPGA and ASIC synthesizers, ZeBu-XL comes with a complete compilation software suite that includes automatic gate-level partitioning, automatic clock processing, and a memory generator. These features permit fast design compilation and incremental compilation as well. Further, ZeBu-XL implements patented reconfigurable testbench (RTB) technology that permits to switch between stimulation modes without recompiling the device under test."

Mentor Graphics Corp. announced it will make a GDS-to-OASIS translation utility available free of charge to promote the adoption of the new OASIS standard. Per the Press Release: "OASIS is the new stream format created in response to the need for more efficient handling of growing data volumes and is designed to replace the current GDS format. More than 40 people, representing more than 20 companies, worked together to develop the new format. Mentor Graphics was involved from the inception, serving for many months as editor of the draft specification, then developing and contributing the translator utility."

Meanwhile, remember the old battle cry of the dot.com era - Web-based Design or Bust! - well, some folks are still working to that end, including Mentor Graphics and Intraware.

Intraware, Inc. has announced that Mentor Graphics completed a pilot of the Intraware SubscribeNet "solution" and has signed an agreement for the service. Based on the agreement between the two companies, the SubscribeNet service will provide Mentor Graphics customers with immediate, "24/7 access" to their software, licenses and updates.

They will also have a variety of online tools to help them "maximize the value of these assets, including a personalized and secure archive of all entitled Mentor Graphics software, proactive email notification of updates, and the ability to monitor and track updates and downloads across their organizations. Mentor Graphics will also benefit from access to the SubscribeNet service's flexible, real-time administration functionality, including granular subscription management, extensive reporting and automated regulatory compliance features that enable technology companies to employ a single automated solution to smoothly integrate their delivery processes into their customer support, product management and other business systems to reduce their operational and support costs while increasing customer satisfaction."

Things are definitely looking up for the design community - things that were at one point in time just trendy, are now becoming a solid, less fleeting reality.

Sequence Design announced in early June the release of PhysicalStudio that the company says comes with "physical power" features that reduce power consumption and simultaneously preserve timing and signal integrity design objectives. Physical power features include leakage power optimization for multi-Vt libraries. The company says, "The specific power reductions that Physical Studio uses to trade-off slack timing for power are cell resizing and multi-threshold-voltage (Vt) cell swapping."

The current release also includes timing analysis script support for object collections, object attributes, report generation for improved compatibility with other static timing analysis tools, and support for signal integrity constructs in .Lib format. Per the Press Release: "PhysicalStudio's physical power optimization reduces dynamic and leakage power. Using PhysicalStudio, designers can concurrently optimize for power, voltage drop, timing and signal integrity, thereby ensuring the electrical integrity of the design.

In a similar timeframe, Sequence also announced their PowerTheater-nm suite for the analysis of power in large SoC designs.

Again per the Press Release: "In today’s nanometer design environment, designers must get an accurate estimation of power as early as possible in the design cycle. PowerTheater-nm includes clock-gating aware power analysis at the RTL level that can predict power savings. Clock-gating technology permits a designer to predict how downstream tools use integrated clock cells to optimize power and when additional optimization will be required to meet critical power budgets. PowerTheater-nm increases the confidence designers have in estimating power, while performing analysis at significantly higher speeds."

"[Additionally], PowerTheater-nm is compliant with every significant design language in the marketplace. Support is in place for Verilog2001, the new design language that has seen rapid adoption. PowerTheater-nm is 10X faster processing VHDL designs. The product offers full coverage for VHDL designs, greatly enhancing power estimation accuracy."

Synopsys, Inc. and Virtio announced that the two companies are collaborating on a "comprehensive" ESL solution that connects hardware and software development flows for leading SoC platforms. Under the collaboration, Virtio and Synopsys say they will integrate Virtio's high-speed software models for SoC platforms, including models for various commercially available embedded processors, with Synopsys' system-to-RTL verification tools in the Discovery Verification Platform.

Per the Press Release: "The integrated, ESL verification solution is unique in that it will enable the concurrent development and verification of hardware and software throughout the design cycle, resulting in significantly faster releases of platform-based SoC products."

Perhaps just as importantly, the two companies also announced that Synopsys has made an equity investment in Virtio. For those who may have criticized Synopsys in the past for appearing to be slow on the uptake to participate in a meaningful way in the emerging ESL paradigm - myself included - this news is a good step forward.

I had a chance to speak this week by phone with Rindert Schutten, Director of Marketing for the System Level Solutions Verification Group at Synopsys, and Shay Ben-Chorin, CEO at Virtio regarding the announcement. Our conversation was an animated one as both Schutten and Ben-Chorin were extremely jazzed about this joint announcement.

The last time the three of us has conversed was at DAC where I was moderating the Summit Design panel which addressed possible roadmaps for moving up a level of abstraction to ESL design. Schutten was on the panel and Ben-Chorin was in the audience.

As the collaboration between the companies was still officially under wraps at the time, neither Schutten nor Ben-Choirin could refute my criticisms of Synopsys, made from the podium, with their pending news. I now stand publicly corrected to a certain extent with regards to the level of commitment from Synopsys towards ESL design.

In fact, I believe this collaboration may represent a significant move on Synopsys’ part to enter into what by all accounts promises to be the design space everyone needs to be playing in going forward - if they intend to become, or remain, a significant force for the use of third-party design tools in the global design community.

Here are further technical details from the Synospys/Virtio Press Release: "Virtio's Virtual Platform software models provide engineers with high-speed, pre-silicon software execution environments that allow them to develop SoC-related software before hardware is available. The integration of Virtio's Virtual Platforms with the Synopsys System Studio system-level design environment will enable engineers to concurrently develop and verify SoC software and hardware, with the confidence that the software is fully compatible with the final hardware."

"The integration of System Studio with the Synopsys VCS RTL verification solution and the Vera testbench automation tool provides a unified system-to-RTL verification environment that combined with Virtio's solution will ensure that virtual software platform models, architecture models, and RTL models stay mutually consistent. The result will be a predictable, concurrent hardware and software development flow that substantially reduces the product design cycle and lowers project risk."

Ben-Chorin is quoted in the Press Release: "We have been working very closely with major SoC platform providers to move software development up in the design process. This collaboration provides the critical integration between Virtio's pre-silicon software development environment and Synopsys' comprehensive system-to-RTL verification solution, ensuring consistency between the hardware and software representation for a specific SoC platform."

Synplicity Inc. announced the availability of a version of its Synplify ASIC software which targets NEC Electronics' Gate Array products. It’s a single-vendor version of the Synplify ASIC software that the company says allows customers to get optimal results for their NEC Electronics Gate Array design, while also taking advantage of "low design tool costs, best-in-class runtime and performance, and design migration benefits. [Additionally], NEC Electronics' Gate Array customers have production support in both the standard, all-vendor version of the Synplify ASIC product, as well as in the single-vendor Synplify ASIC for NEC Electronics Gate Array product. NEC Electronics has performed full qualification testing for the Synplify ASIC products and has design support available immediately through its OpenCAD design environment."

Yutaka Hayashi, General Manager, Platform LSI Division, NEC Electronics, is quoted in the Press Release: "The low NRE costs of a gate array previously were encumbered with the high tool costs of traditional cell-based design tools. The availability of a dedicated product for gate array synthesis solves a real customer dilemma. By working with Synplicity, we have removed this barrier for both new and existing gate array customers."

The X Initiative, Cadence Design Systems, Inc. and Toshiba Corp. announced on June 7th that Toshiba has produced "the industry’s first" commercial SoC devices built on the X Architecture design. Toshiba’s new TC90400XBG chip is said to reflect the benefits of the X Architecture by delivering a "powerful, compact and highly integrated solution for next generation digital video broadcast and multimedia home-entertainment applications ... Compared to equivalent Toshiba products with the conventional "Manhattan" design, the new chip implementing the X Architecture is approximately 11 percent faster in speed and 10 percent smaller in random logic area. Samples of the new chip will be available in November 2004 and mass production is expected to begin in the second quarter of 2005."

Meanwhile, per the Press Release: "The X Architecture represents a new way of orienting a chip’s microscopic interconnect wires with the pervasive use of diagonal routes, in addition to traditional right-angle ‘Manhattan routing. This innovative architecture results in chip designs with significantly fewer wires and less vias to connect the wiring layers in SoC devices. By enabling higher quality device performance metrics, the X Architecture will bring significant advantages to next-generation digital media and other advanced consumer applications. Toshiba and Cadence have collaborated on the development of the X Architecture and are co-sponsors of the X Initiative, a consortium of more than 40 leading companies dedicated to facilitating the commercial adoption of the X Architecture by preparing the design chain for volume production."