** Agilent Technologies Inc. and Synopsys Inc. announced a new "industry-first" diagnostics reference methodology, which has been designed to "speed fault localization and failure analysis for semiconductor design and test engineers faced with identifying device failures under increased time-to-market pressure."

Per the Press Release, the work took 3 years and is a methodology "enabled by the Agilent 93000 SmarTest Program Generator (PG) 2.2 and the Synopsys TetraMAX ATPG solution, in conjunction with the Agilent 93000 SOC Series test platform. This combination of tools automates the bi-directional information sharing between EDA and ATE required for scan diagnostics."

Tom Newsom, Vice President and General Manager of Agilent's SoC Business Unit, is quoted: "Our customers want us to link design and test more closely in order to lower the overall cost of test. Our strategic alliance with Synopsys has successfully contributed toward bridging the gap between EDA and ATE."

Antun Domic, Senior Vice President and General Manager in Synopsys Implementation Group, is also quoted: "Automating failure and yield diagnostics is a critical business issue for our customers Synopsys' collaboration with Agilent is key to improving manufacturing test flows, and together we are demonstrating further leadership by delivering a diagnostics reference methodology."

** Aldec, Inc. announced the release of Active-HDL 6.3, the Actel edition. Per the Press Release: "The new version provides easy-to-use push button integration to Actel‘s Designer series advanced place-and-route software. When combined with a third-party synthesis tool, Active-HDL and Designer create a complete design capture through physical implementation solution for Actel FPGA devices."

"When Active-HDL is connected with Actel Designer (aside from synthesis) the system becomes a closed environment to the engineer, complete with Actel precompiled libraries. It offers unrestricted VHDL, Verilog, EDIF or mixed simulation that is capable of executing all Actel implementation tools from the Active-HDL graphical user interface. The entire process from design capture, synthesis, implementation and optimization is handled directly from the Design Flow Manager. Active-HDL is compatible with most third-party synthesis tools from companies including, Synplicity, Magma, Synopsys, and several FPGA-vendor provided tools.

Saloni Howard-Sarin, Director of Antifuse and Tools Marketing at Actel, is quoted: "Actel is delighted that Aldec has chosen to release an Actel edition of its Active-HDL design environment. We value best-in-class, third-party tools, and Active-HDL provides a robust set of design and verification tools that are easy to use, flexible and powerful." As is often the case, Actel leads the way for FPGA vendors partnering with third-party tool vendors.

** Altium Ltd. announced that its Nexar system design software has been updated to support v4.2 of Altera's Quartus II development software.

Nick Martin, Joint CEO and founder of Altium, is quoted: "Supporting Altera's Quartus II software ensures that our Nexar customers have access to the best place-and-route and synthesis technology so that they can get the most out of their Altera FPGA-based designs."

James Smith, Director of EDA Vendor Relations at Altera, apparently has very good relations with at least one of those vendors: "Altium's support for the Quartus II development software in its Nexar software demonstrates the growing success of Altera products across broad market segments. As the only development tool that supports FPGA, CPLD and structured ASIC designs, the Quartus II software allows Altium customers to easily target their prototyping and production solutions using our programmable logic devices."

** Cadence Design Systems, Inc. announced that NEC Corp. used Cadence's Encounter design platform to develop "the complete 90-nanometer chipset for one of the world's fastest vector supercomputers. With Encounter technology, NEC achieved a 2x improvement in chip performance on its most advanced, highest performance 90-nanometer vector supercomputer chipset to date. The NEC SX-8 chipset is comprised of four 90-nanometer designs, including a hierarchical 9-million instance chip that was routed flat for final engineering change order implementation and rapid design closure."

** Cadence also announced that Toshiba America Electronic Components, Inc. (TAEC) has introduced a design kit to support its Custom SoC and ASIC customers using Cadence's Encounter RTL Compiler synthesis. The new kit supports designs for implementing in TC280 (130-nanometer), TC300 (90-nanometer), and newer process technologies. Per the Press Release: "Customers now can use this smooth, qualified flow for RTL-to-netlist synthesis and netlist-to-netlist optimization with Encounter RTL Compiler."

** Celoxica announced that crucial algorithm IP, and a block-based graphical design entry platform, have been added to the company's portfolio of ESL design tools.

Per the Press Release: "PixelStreams development environment provides a library of powerful video data manipulation functions with an easy-to-use interactive graphical editor. The PixelStreams platform builds on Celoxica's best-in-class, C-based design and synthesis products to create an ideal design flow for the rapid prototyping, exploration and development of complex video processing systems."

"PixelStreams provides a broad range of macro calls that allow the user to gather, manipulate and output streams of video pixel data. These C-based models deliver enhanced parameterization capabilities and high-level interface abstraction. In addition, PixelStreams includes an IP reuse graphical editor as an entry tool for imaging algorithms to provide ease-of-use and design productivity in a familiar block-based methodology. From this block diagram entry, developers can quickly design, analyze and implement hardware prototypes for complex video imaging systems using the Celoxica DK Design Suite for C-based synthesis."

Jeff Jussel, Vice President of Marketing at Celoxica, is quoted in the Press Release: "There are two popular methods of design entry in ESL design tools; block-based schematic-style entry and software-style algorithmic coding using text-based descriptions. With PixelStreams, we've fused these approaches in a block-based graphical editor manipulating a library of C-based video processing models as well as custom C-language models. This delivers both ease-of-use and flexibility. When combined with C-language synthesis, PixelStreams provides the absolute fastest way to get from algorithm concepts to hardware implementation for applications using these imaging functions."

** Celoxica also announced the release of version 3.1 of its DK Design Suite, DK3.1, which per the Press Release: "provides high-level system co-design, verification and C-based synthesis for complex algorithm implementation to high-density FPGA and Programmable SoC devices."

"The new release extends the functionality, integration and silicon coverage of Celoxica's leading ESL design environment and improves the quality of results and designer productivity for generating production grade FPGA designs and rapid ASIC and SoC prototypes. DK3.1 also includes performance upgrades to the Nexus-PDK co-verification environment and new device support in the integrated Platform Developers Kit (PDK) board and processor support packages. DK3.1 improves support for the implementation path from prototype to SoC through advanced high-level synthesis featuring IEEE compliant VHDL and Verilog output, automatically generated from complex C algorithms."

** Denali Software announced that Ubicom, Inc. has selected Denali’s verification IP products for its chip design and verification projects. The companies say that Ubicom engineers use Denali’s PureSpec verification software to model and simulate interactions between its chips and other devices in the target system.

Jon Gibbons, Ubicom’s Director of Engineering, is quoted in the Press Release: "Our customers demand high-quality, ultra high-reliability SoCs that utilize leading-edge interface standards. Functional verification of these systems is critical, especially for the chip to chip protocols, and that’s why we chose Denali. The quality and completeness of its verification IP enables us to produce a high-quality product on time."

** Forte Design Systems announced that Toshiba Corp. has chosen Forte’s Cynthesizer SystemC behavioral synthesis product for use in their SystemC design flow. The companies say they have entered into a multi-year agreement to use Cynthesizer in Toshiba’s next-generation system-level ICs for the consumer, networking and computer markets.

Seiichi Nishio, Senior Manager of Methodology at Toshiba, is quoted: "As a leading supplier of complex system-level ICs, we are constantly working to improve the design process to get new products developed and into volume production faster. After extensive evaluations, we determined that by using Cynthesizer, we can substantially reduce the time to design and implement next generation products so that we meet customer needs while taking advantage of the increasing performance and complexity that our advanced technologies provide. Furthermore, Forte was the best vendor that shared our vision of a next-generation design flow and had the products to support it."

** HARDI Electronics AB announced availability of a new motherboard in the company's HAPS family, designed for access to multi-gigabit serial links, embedded PowerPC processors, and 1600+ pairs of LVDS signals. The board is named HAPS-20 and is for designers who need high-speed prototypes of large ASICs.

Turning to the Press Release for the technical details: "HAPS-20 is carefully designed for maximum performance, with respect to signal integrity, speed and other critical issues. The board can be used as a stand-alone device to prototype ASIC designs up to four million gates. Capacity can be further increased by stacking two or more HAPS-20 boards together. The HAPS-20 conforms to the HAPSTrak standard, which guarantees compatibility with previous and future generation HAPS motherboards and daughter boards (e.g. RAM, I/O, communication, connector boards, etc.)."

"The new board uses four Xilinx Virtex-II Pro XC2VP70/100 devices in the largest pin count package, offering 80 multi-gigabit serial links, 8 embedded PowerPC processors and over 3000 user I/Os. All I/Os can be used in differential mode (LVDS), enabling long distance drive capability at transmission rates exceeding 800 Mb/s per channel. More than 2000 interconnects between the FPGA devices make it ideal for large ASIC designs with wide busses."

Lars-Eric Lundgren, President and CEO of HARDI, is quoted: "We are proud to announce what we believe to be the most advanced FPGA platform for ASIC prototyping today. Our customers are facing complexity and time-to-market pressures like never before. Not only does our HAPS-20 keep pace with these challenges, but it offers even more functionality at as much as a 20% lower cost over the previous generation. In addition, our customers are able to verify designs faster using our best-in-class connectivity and Lego-like flexibility." Sounds fun!

** Knowledge*on Semiconductor announced the availability of new design kit for the Agilent Technologies' Advanced Design System (ADS).

Per the Press Release: "The company has provided foundry services based on the state of the art 6-inch InGaP/GaAs HBT technology for world-wide wireless business runners since 2000. At present three unique HBT processes with high power, linearity and speed characteristics are offered to meet customers' various design targets. The design kit, the company officially released for the first time, contains lots of passive components as well as the three types of HBT. RF engineers benefit from the design kit including accurate models for 214 inductors, 30 capacitors, resistors, via hole, pad and transmission line, which the foundry provides with. The design kit features a temperature scalable HBT model and the accuracy of the model is confirmed through temperature dependent DC and frequency measurements."

Sanghoon Cheon, Knowledge*on Device Engineering Group Manager, is quoted in the Press Release: "The most critical design factor of power applications is the thermal property of the HBT, which is well known for its superb power characteristics. We made dedicated efforts to build reliable thermal model of our HBT process. We believe that the design kit including our accurate thermal model offers trustworthy guidelines on circuit design."

** Mentor Graphics that its Platform Express XML-based rapid SoC design creation tool now supports the SPIRIT 1.0 specification for IP design reuse.

Ralph von Vignau, Chairman of SPIRIT and Director Technology & Standards of Philips Semiconductors, and CTO for the Reuse Technology Group, is pleased: "The success of SPIRIT depends on EDA vendors supporting the standard with their tools. Mentor is a technology contributor and active participant in creating the SPIRIT standard, so it's great to see this work being successfully deployed in Platform Express." (See below for more on the new SPIRIT Standard.)

** Synopsys Inc. announced that Winbond Corp. has achieved "first-pass silicon success" using Synopsys' Galaxy Design Platform for its latest 130-nanometer MPEG-4 multimedia chips. Per the Press Release: "Winbond's MPEG-4 chip is representative of leading-edge 130-nm designs, where utilization of greater than 80 percent of the silicon area is fast becoming the norm. Congestion and increased risk of SI issues are more prevalent in chips of this density, and can contribute to significant increases in chip failure, declines in yield at target frequencies, and reduced performance."

Shang-E Tai, Assistant Vice President at Winbond, is quoted in the Press Release as well: "Using Synopsys Galaxy platform, we signed off our MPEG-4 designs. In full production, we are expecting it to help us attain maximum yield at our target device frequency."

Meanwhile the eminently quotable Edward Wan, Senior Director of Design Services Product Marketing at TSMC, was heard to say: "Synopsys and TSMC have partnered to ensure that our mutual customers targeting TSMC's advanced technologies can take advantage of TSMC Reference Flow 5.0 and TSMC in-house library to achieve the best quality of results, accuracy, and time to volume. Winbond's silicon success demonstrates that our combined flow and TSMC in-house libraries are proving to be seamlessly integrated and highly effective for the most complex designs."

** Tower Semiconductor announced the availability of Virage Logic's Nonvolatile Electrically Alterable (NOVeA) embedded memories for production on Tower's 180-nanometer CMOS logic process. Per the Press Release: "NOVeA is the industry's first embedded reprogrammable nonvolatile memory (NVM) to be manufactured on a standard CMOS logic process without any additional masks or process steps."

** Verbatim**

The SPIRIT Consortium (Structure for Packaging, Integrating and Re-using IP within Tool-flows) announced the first public release of the approved SPIRIT specification. SPIRIT Version 1.0 is said to indicate that "for the first time SoC designers worldwide have access to an industry standard for IP reuse that will enable them to select, configure and integrate SPIRIT-compatible IP from multiple vendors using a range of different SPIRIT-compatible EDA tools and design environments."

"SPIRIT Version 1.0 addresses SoC design at RTL level, but work is already underway to draft Version 2.0 of the standard that will extend the specification to cover comprehensive interoperability between tools and explicit support of Electronic System Level (ESL) Design and Verification. This will include, for example, the ability to launch application-specific tasks operating on SPIRIT formats from within different EDA tools. It will also enable provision of configurable IP for automated ESL design, assembly, verification and simulation."

"In the period between the release of an alpha version in June of this year and today’s public release of Version 1.0, the SPIRIT specification has been thoroughly tested by the SPIRIT consortium membership on real IP and EDA tools with remarkable results. Furthermore, the excitement generated around the SPIRIT initiative and specification release has driven membership up to more than 30 members in total, further substantiating the released and proven SPIRIT specification as the de facto standard."

Let's close with a Press Release quote from Ralph von Vignau. As you recall, we met him earlier at Mentor Graphics: "The release of an approved specification that has already been validated by leading IP and EDA providers within the SPIRIT consortium is a real win-win situation for the industry and users alike. It represents a major step forward in short time-to-market integration of the complex system-on-chip solutions needed for today’s and tomorrow’s embedded systems."

** Quote of the Week **