Things - tools & technology

September 12, 2005


Editor's Note: There are numerous announcements out of Cadence that lead off this week's news. You can link down to those announcements, or skip the entire CDNLive! section to read In other news ....


************************************

CDNLive!

Here are the announcements that went out at 12:01 AM on September 12th in anticipation of the company's 3-day conference in Santa Clara, CA.

Product Segmentation Strategy
Physical Verification System
AMS Methodology Kit
Cadence/ARM extended alliance
Deepening relationship

 
* Cadence Design Systems announced a new product segmentation strategy to provide customers with "multiple levels of technology tailored to specific levels of design complexity. In support of this new strategy, the Cadence Encounter digital IC design platform now offers a tiered range of products scaled to different complexities of digital IC design, including its new MasterPlan automatic floorplanning technology."

The new Encounter offerings are tiered into three levels, Encounter L, XL and GXL.

The Encounter L product series provides an integrated, value-priced implementation environment for less complex, flat designs at 150 nanometers and above with gate counts below 5M gates.

The Encounter XL product series targets large-scale, high-performance, hierarchical designs over 5M gates at 130, 90 and 65 nanometers, and features MasterPlan automatic macro placement and floorplanning technology. The MasterPlan feature within the Encounter XL series reduces the design effort required to design the physical architecture for very complex SoC designs. This includes high-end networking, graphics and processor ICs with hundreds of embedded memories and hard IP blocks, which are typically placed manually. Unlike conventional automation approaches that focus strictly on projected wire length, the MasterPlan feature within the Encounter XL series works by optimizing overall chip signal flows. The result is an expert-quality chip plan in a fraction of the time typically taken.

The First Encounter L and First Encounter XL silicon virtual prototyping products, and SoC Encounter L and SoC Encounter XL full implementation products, will be available in September 2005.

Encounter GXL is scheduled for delivery in the fourth quarter of 2005.

Hisaharu Miwa, Deputy General Manager, Design Technology Division, LSI Product Technology Unit at Renesas Technology Corp, offers support: "We have successfully started to use MasterPlan automatic floorplanning in our production designs. It allows us to create an automatic floorplan for multi-million gate designs with hundreds or even thousands of hard macros in minutes or hours, as opposed to the days or weeks it formerly took. MasterPlan is key to our goal of reducing overall design cycle time on high-complexity nanometer designs."

Nobuyuki Nishiguchi, Vice President and General Manager, Development Department 1 of STARC, also offers support: "We have been evaluating MasterPlan from the beginning, and we have found that it automatically produces much better initial floorplan results than other existing tools available in the market. Starting with the MasterPlan results, our designers will dramatically shorten turn-around-time to reach the final floorplan. We are looking forward to current and future enhancements of automatic floorplanning features for our production deployment."

 
* Cadence introduced the Cadence Physical Verification System.

Per the Press Release: "The system's massively parallel approach facilitates multiple design turns per working day – even for the largest designs at 90-nanometers, 65-nanometers and below that would otherwise require overnight or multi-day runs … The Cadence Physical Verification System employs a multi-strategy partitioning approach that removes the throughput limitations of conventional physical verification solutions and which leverages the full power of cost-effective, distributed processing platforms. The dedicated processing engines simplify rule deck authoring and maintenance, enhance quality of results and take full advantage of the system's highly scalable, distributed processing environment to further improve performance. The new system features several industry-first capabilities that accelerate chip time to market. A concurrent debug capability ensures the most productive use of physical verification runtime. It delivers debug results during runtime, via OpenAccess 2.2, directly into an integrated Virtuoso-based environment. Designers can start to debug designs immediately after launching a physical verification run and fix errors in parallel with job execution. This allows them to quickly identify problems and eliminate wasted time by terminating the run if they discover serious design flaws."

Shoji Ichino, General Manager in LSI Technology Development at Fujitsu, offers validation: "The Cadence Physical Verification System is the leading solution that addresses Fujitsu's needs for advanced sub-90-nanometer designs and that also delivers the performance scalability we require to reach 65 nanometers and below. The system offers outstanding performance, concurrent results reporting, and superior integration with the Virtuoso platform and OpenAccess. The Cadence Physical Verification System is in production use by our worldwide design teams for 90- and 65-nanometer physical verification and its extensibility will be used in the future to address manufacturing and yield optimization."

 
* Cadenceannounced the Cadence AMS Methodology Kit designed analog mixed-signal (AMS) designers of wireless, wired and consumer electronics devices. The company says this kit will help "achieve shorter, more predictable design cycles while creating reusable AMS blocks … This methodology is enabled by the new Cadence AMS Block Flow with Reuse and Migration, the Cadence AMS Top-Level Flow, and the Cadence Analog Driven Physical Implementation Flow, along with a Generic Process Design Kit and simulation setups."

Note: "The goal of the Cadence kits approach is to simplify the application of Cadence technology and thereby shorten time-to-productivity. Customers can then focus their precious design resources on design differentiation rather than design infrastructure. Cadence kits address application-specific design challenges by combining a verified methodology, packaged in platform flows, with IP and consulting all demonstrated on a representative reference design.

Peter van Staa, Senior Director for Methods Tools and Technologies, Automotive Electronics, at Robert Bosch, GmbH, offers his endorsement: "In line with Cadence's kits approach, Bosch made the move to Cadence's AMS design methodology and flows to address the challenges of handling increased silicon complexity within shorter, more predictable design cycles, while maintaining zero-defect levels of quality. These increased design capabilities and productivity, resulting from Cadence's silicon-accurate methodology and VCAD services for flow implementation, will be of key importance to Bosch going forward."

Ken Torino, Director for Foundry Products for IBM Systems & Technology Group, also offers praise: "Now IBM's industry-leading Process Design Kits (PDKs) will be compatible with the Cadence AMS Methodology Kit, beginning with CMOS8RF, which allows IBM's Foundry customers to focus on their design problems by having access to Cadence's integrated methodology solutions."

The second new kit is the Cadence Optimization Methodology Kit for ARM Processors, which is designed to help design teams "enhance performance, power utilization, and area when designing with ARM cores and physical libraries. The results of the kit build on the long-standing alliance between ARM and Cadence to more tightly integrate the companies' products to meet customer market requirements."

 
* Cadence and ARM announced they have extended their design chain alliance to deliver further benefits to their mutual customers. The result is the Cadence Optimization Methodology Kit for ARM Processors, which helps design teams enhance performance, power utilization, and area when hardening synthesizable ARM processors … The Cadence Optimization Methodology Kit for ARM Processors builds on the success of the silicon-proven ARM-Cadence Encounter Reference Methodology.

In addition to the reference methodology, the kit includes Cadence Encounter RTL Compiler synthesis, First Encounter silicon virtual prototyping, front-end views for the ARM Artisan SAGE-X standard cell libraries for TSMC's 0.13-micron and 90-nanometer G processes, and service and support to help designers achieve high performance, low power and small area levels, while reducing development time.

Jan Willis, Senior Vice President of Industry Alliances at Cadence, commends the leverage: "Today's disaggregated design chain requires a more integrated, collaborative approach to massively simplify the design process. This Methodology Kit leverages expertise from both companies to help our customers rapidly reach the target frequency, die size, and power consumption requirements for their particular markets."

Mike Inglis, Executive Vice President of Marketing at ARM, seconds the motion: "As the complexity of design tasks has increased with lower-power and higher-performance requirements, we have increased our level of integration and validation with Cadence through efforts such as the Silicon Design Chain Initiative. The new Methodology Kit builds on this collaboration by providing the technology, support and training necessary to enable our Partners to achieve their specific power, performance and area goals in hardening synthesizable ARM processors."

Masakazu Urahama, Manager of the Silicon Platform Design Department, LSI Design Division, at Oki Electric Industry Co., Ltd., speaks out: "We are excited to see Cadence and ARM working together to deliver further benefits in a streamlined flow with the Cadence Optimization Methodology Kit for ARM Processors."

 
* This deepening relationship between ARM and Cadence will result in additional projects to ensure more optimized products from both companies are aligned to meet customer market requirements. Areas of collaboration include extending the companies' continuing work in advanced processor cores, system verification, and on extending the effective current source delay model (ECSM) which Cadence pioneered. The companies will expand work done through the Silicon Design Chain Initiative to add additional low-power design capabilities, and also extend support for system languages, including the e, SystemC, and SystemVerilog languages.


************************************

In other news ...


* Altium Ltd. announced Agilent Technologies' new joint venture, Agilent-Qianfeng Electronics Technologies, is going to use Altium Designer as its design system.

Xiaofei Ma, General Manager of R&D at Aglient-Qianfeng, describes a process of building consensus: "Our engineers voted for Protel from the beginning because it was able to provide exactly what we needed. In conjunction with our engineering team, Altium's China team worked closely with us to determine and meet our scheduling, training and support requirements for a smooth adoption of Altium Designer's Protel license. We are excited about the implications of a solid partnership for the future."

Edward Qu, General Manager of Altium's Shanghai Representative Office, says the vote was appropriate: "Our advanced products, strong knowledge of the local electronics industry and dedication to customer relationships supported by our Global Customer Care Division, allows us to form very productive partnerships with electronics companies in China. This is a time of very high growth in the region's electronics industry, and Altium is well placed to support the advanced electronic product design needs of facilities like the Agilent-Qianfeng R&D labs."

Meanwhile, did you know – "Formed in January 2005, Agilent-Qianfeng Electronics Technologies is a joint venture between Agilent Technologies' test and measurement organization and Chengdu Qianfeng Electronics Ltd., and is responsible for the development and manufacturing of test equipment for the Chinese and world markets. The new joint venture is a key component of Agilent Technologies' involvement in China's rapidly growing electronics industry. Chengdu Qianfeng is a prominent, industry-leading company in electronic equipment, household appliances and electronic machinery, and is recognized as a premium brand in China."


* Altium also announced its new online DEMOcenter, which the company says includes 89 short, narrated online demonstration videos of the company's Altium Designer system. Per the Press Release: "The first in its class, the DEMOcenter provides a much higher degree of detail than static screen captures and text, and allows engineers to see exactly how Altium Designer performs specific tasks."

Rob Irwin, Product Marketing Manager for Altium, says the new on-line learning tools are really cool: "We know from our experience at trade shows and other events that when we show engineers the system operating live, the concepts underpinning the software become clear and they get really excited about the possibilities of this new soft design paradigm and the potential benefits that Altium Designer brings to the table. We believe that the DEMOcenter's extensive use of video to showcase Altium Designer has the potential to bring this same level of understanding and excitement to a broader audience, and make them aware of the importance of the emerging soft design paradigm and the need to prepare for it."


* ATI Technologies, Inc. says it has received "functional samples" of its IMAGEON 2240 media processor for high-volume camera phones from Chartered Semiconductor Manufacturing. Meanwhile, Chartered says it will start volume production on its 0.13-micron low-power, all-copper process; therefore providing ATI with additional manufacturing capacity for its IMAGEON 2240.

Jim Seto, Vice President for ASIC NPI and Production Engineering at ATI, is jazzed: "Expanding production with Chartered who has proven 0.13-micron manufacturing capabilities, gives us added flexibility in our capacity needs to meet strategic growth market opportunities."

Mike Rekuc, Senior Vice President of Worldwide Sales and Marketing at Chartered, is also happy: "Being chosen by a system and product leader as a foundry source for one of its hottest-selling products further reflects our enhanced position in enabling advanced technologies and world-class manufacturing."


* Chartered also announced availability of "high-performance value-added solutions for advanced consumer and wireless products. Currently in prototyping, the additional solutions include: 0.18-micron ultra-low leakage (ULL) high-voltage process for FPD drivers for mobile products, 0.18-micron and 0.35-micron silicon germanium (SiGe) BiCMOS processes for single-chip ultra-wide band (UWB) communications and noise-sensitive TV tuners, 0.18-micron and 0.25-micron one-time programmable (OTP) solutions for RFID chips and microcontroller units (MCUs). The solutions are developed as plug-in modules on top of Chartered’s baseline CMOS processes and leverages existing design infrastructure, therefore enabling designers to optimize performance and cost efficiencies, while realizing high yields in volume production."

Kevin Meyer, Vice President of Worldwide Marketing and Platform Alliances at Chartered, is committed: "We are committed to innovating and extending our value-added solutions platform to be well-positioned to collaborate with our customers at the product development stage and support their product differentiation and volume ramp."


* Cadence Design Systems, Inc. announced support for OpenAccess 2.2. The Press Release is quite specific: "Building on its current support for OpenAccess 2.0, Cadence's adoption of OpenAccess 2.2 will further improve the efficiency of design-data exchange and enhance customers' ability to tightly integrate internal applications with Cadence products into a seamless flow."

Jim Miller, Senior Vice President of Development at Cadence, takes it from there: "Going forward, all new IC Implementation product developments will leverage OpenAccess, specifically our Virtuoso custom design platform, where we are leveraging the expanded data model to build new features and capabilities on top of OA."

Philippe Magarshack, Group Vice President of FTM – Central CAD & Design Solutions at STMicroelectronics, also sends kudos via the Press Release: "We've been very impressed with the ease of data exchange enabled through support of OpenAccess by both the Virtuoso and the Encounter platforms used in our mixed-signal design flow, and we intend to deploy the OpenAccess-based chip-integration flow for our 65-nanometer process designs going into tapeout later this year."


* Cadence Design Systems also announced that Elan Microelectronics Corp. has "validated its standard cell libraries and embedded memories using the Cadence Encounter Conformal Custom equivalence checking solution."

L.C. Lin, Assistant Director of the EDA Department at Elan Microelectronics Corp., is delighted: "Conformal Custom greatly improved the quality of our libraries by helping find a number of modeling inconsistencies and functional errors. Conformal Custom also ensures high-quality memory models by verifying the logic function of memory circuits with the RTL model. The memory models developed using Conformal Custom work seamlessly in our simulator and emulator."


* Cadence Design Systems announced, as well, that the SoC Technology Center (STC) of the Industrial Technology Research Institute (ITRI), a Taiwan-based non-profit R&D organization, has taped out a low-power test chip using Cadence Encounter and its RTL-GDSII low power methodology.

Chien-Wei Jen, General Director of STC, commends Cadence: "This chip tests the Application-aware Power Management Solution Package and the important functionality of a dual-core multi-media application processor SoC which we will be taping out early next year. The support of multi-VDD methodology in implementing this chip represents a significant achievement by the Encounter multi-VDD low power design flow."


* Cadence also announced that Magnum Semiconductor Inc. is "the 100th customer of Encounter RTL Compiler global synthesis … Encounter RTL Compiler has achieved this level of adoption faster than any other synthesis tool. " Not exactly sure how one proves that …

Eka Laiman, Principal Hardware Engineer at Magnum, is unequivocal: "At Magnum we decided to adopt Encounter RTL Compiler because it can synthesize our full chip top-down overnight, and the netlist it produces converges on our timing goals faster in physical implementation. Because of its ability to reduce our overall project turnaround time, we are currently using Encounter RTL Compiler in production for our next-generation DVD chip." That makes sense.

Cheng-Tie Chen, Vice President of Engineering at Magnum, adds via the Press Release: "When we formed Magnum we wanted to use the front-end tools that would make us most competitive. It turned out that Cadence has an impressive front-end solution. Encounter RTL Compiler, Conformal Equivalence Checker, and Incisive functional verification combine to deliver a very strong offering that will improve our productivity and competitiveness." That also makes sense.


* Catalytic Inc. announced that Genesis Microchip Inc. has selected Catalytic RMS to "simplify the design flow for its image processing solutions. Catalytic RMS works seamlessly with MATLAB from The MathWorks to provide fast floating-point simulation for MATLAB code, accurate fixed-point modeling capabilities, and fast fixed-point simulation."


* Celoxica and Sundance have announced an agreement that the companies say, "bridges the gap between conventional design flows for DSP and FPGA systems. The companies will combine expertise to offer out-of-the-box system design solutions backed up by their established partnerships with Texas Instruments and Xilinx … The result of this partnership is the development of algorithm acceleration solutions for vertical applications, including C-based IP modules, optimized FPGA hardware accelerators, and reference board prototypes built on Sundance boards programmed using Celoxica software tools. The companies will initially focus their efforts on software-defined radio (SDR) and complex image processing."

Phil Bishop, President and CEO of Celoxica, starts: "System designers commonly choose between DSP for signal processing systems and FPGAs to implement complex algorithms and signal processing systems. Combined they can offer a compelling solution for optimization of power, performance and flexibility. The key to unlocking this potential is providing design ease-of-use from both the DSP and FPGA perspectives."

Flemming Christensen, Managing Director of Sundance, is next: "Many of our customers have already moved to model-based design and IP reuse to help streamline design and boost productivity. With more and more effort now being placed on value-added IP and customization inside a mixed DSP/ FPGA system, the addition of C-based design that tackles complex algorithm development in hardware and software is inevitable."

Ram Sathappan, SDR Business Development Manager at TI, continues: ‘With this improved design flow for DSP plus FPGA based systems, customers can more easily integrate the performance of TI DSP with FPGA based co-processors. C-based design and synthesis for hardware and software in DSP/ FPGA based COTS systems will address the needs of a wide range of designers."

Robert Bielby, Senior Director for Vertical Markets and Partnerships at Xilinx, closes: "Xilinx and our Alliance Program members are seeing increasing market acceptance of our FPGAs for a broad range of DSP applications. We are gratified that Celoxica and Sundance have combined their expertise to make DSP development more accessible to design engineers to further accelerate this growth."


* Cray Inc. announced that it is collaborating with Celoxica to make Celoxica’s DK Design Suite available to customers who "want to use a software design flow to accelerate their applications using FPGAs integrated into the Cray XD1 supercomputer."

Celoxica President & CEO Phil Bishop is jazzed: "Cray XD1 system users who want to realize the full potential of reconfigurable computing will now be able to choose an easy-to-use C programming environment. The Celoxica DK Design Suite offers tools that deliver a rapid and flexible implementation methodology specifically designed for reconfigurable architectures We are excited to be working with a company of Cray’s stature as part of our strategy to expand our business in the high-performance computing arena."

Amar Shan, Product Manager for the Cray XD1 system, is also sensing the magic: "The unique design of the Cray XD1 system maximizes FPGA operation by directly linking the FPGAs to the system’s high-speed interconnect, accelerating communications between the FPGAs and the processors. Software engineers seeking to optimize the performance of their applications with FPGAs can use Celoxica’s tools to program in the familiar C language, rather than having to master low-level languages such as VHDL or other tools more suited to hardware development. Cray is pleased to be partnering with Celoxica as we continue to add tools to help our customers get the greatest advantage from their supercomputing investment."


* Cray also announced that Cray XD1 supercomputers will support the newest Xilinx Virtex-4 FPGAs, including the Virtex-4 LX and SX platform. Per the Press Release: "The Cray XD1 system is designed to employ the Xilinx FPGAs as advanced co-processors that let users accelerate high-performance computing (HPC) applications involving compute-intensive operations, such as digital signal processing or searching and sorting routines. The Cray XD1 supercomputer is one of the first platforms to deliver true reconfigurable computing. The system overcomes communications delays by integrating Xilinx Virtex-4 FPGAs at the operating system level and linking them to AMD Opteron processors through a high-bandwidth, low-latency interconnect."

Amar Shan, says 'yes' to FPGAs: "We believe reconfigurable computing based on FPGA technology will continue to prove invaluable for researchers and engineers who want to accelerate HPC applications. Companies like Celoxica and others have developed software tools that enable users to take even greater advantage of the Cray XD1 system's FPGA capabilities."

Craig Ulmer at Sandia National Laboratory's Visualization & Scientific Computing group, seconds the motion: "At Sandia National Laboratories, a central part of our reconfigurable computing research effort involves work with the FPGA-equipped Cray XD1 supercomputer. The Cray XD1 system's architecture provides unique opportunities for accelerating scientific applications using FPGA co-processors. We are looking forward to being able to leverage the latest generation of Xilinx FPGAs in order to improve our reconfigurable computing capabilities."


* Fluent Inc. announced a new version of its Icemax circuit extraction tool for IC package designs. The company says, "Icemax 2.1 is a major new update to the tool, targeted specifically toward providing a more integrated design flow for customers using Cadence's Allegro Package Design environment. The direct Icemax-Allegro interface minimizes setup time by allowing the user to automatically import most complicated package layouts in a matter of minutes. The interface also provides the user with several cleanup options (smoothing, sliver removal, spike removal etc.), which can help eliminate unnecessary features in the layout geometry before feeding it to the meshing and solution engines.

Rajesh Nair, Icemax Product Manager, says his customers are fortunate: "IC package design cycles are shrinking continuously, while the layouts are getting more and more complicated. Semiconductor companies worldwide are constantly looking for cost savings in their design flow to maintain their competitive edge. Our customers continue to realize significant return on investment due to the superior performance of Icemax compared to any other tool in the market today. Icemax 2.1 further strengthens Fluent's partnership with customers by providing a smooth and seamless data transfer from their design environment to the extraction tool."


* Mentor Graphics Corp. announced a new Seamless processor support package (PSP) for Freescale's PowerQUICC III MPC8548E communications processor containing a PowerPC core. Per the Press Release: "The Seamless product and new PSP provide designers with a virtual platform on which to concurrently develop board-level hardware and software in systems powered by the MPC8548E. This approach increases simulation throughput, thereby allowing designers to quickly validate that the system hardware and embedded software are functionally correct before prototypes are manufactured, thus reducing the risk of lengthy hardware design iterations."

Lakshmi Mandyam, PowerQUICC III Product Marketing Manager, Networking and Computing Systems Group at Freescale, says: "We’re seeing strong interest in the MPC8548E processor from our customers in the networking industry, and we are very pleased that Mentor Graphics is ready with a turnkey solution that extends the benefits of a leading co-verification environment to early adopters of one of our most advanced communications processors."


* Mentor Graphics also announced support for 64-bit Linux platforms by "declaring full operational qualification for its analog/mixed-signal tool set. Mentor's entire line of Eldo and ADVance MS analog and mixed-signal products have been certified for operation on Opteron and EM64T processor architectures using the Red Hat Enterprise Linux 3 platform … The move to 64-bit processing will become more crucial as engineers begin to design at 65nm and below and populate each chip with millions of gates."

Jue-Hsien Chern, Vice President and General Manager of Mentor's Deep Submicron Division, is bullish about the future: "Linux on X86-64 hardware is proving to be a great performance platform for our products."

Tim Yeaton, Senior Vice President of Marketing at Red Hat, is almost incredulous: "Red Hat Enterprise Linux for 64-bit architectures delivers unbelievable performance at a great value, especially for compute-intensive workloads found in the EDA market. Red Hat is proud to partner with Mentor on this first-class solution for our mutual customers."

Please note: Mentor Graphics products are also available on Novell Linux SLES 9, Red Hat Enterprise Linux 3 for Xeon-64, and Opteron platforms.


* "Starbridge Systems and Nallatech announced a worldwide strategic partnership that offers a unique combination of software, hardware and services suited for high-performance computing applications. These combined offerings make the power of FPGAs accessible to system engineers involved in high-performance computing applications in markets such as defense and military, homeland security and bioinformatics."

"The agreement follows the porting of Starbridge Systems Viva FPGA development software to Nallatech’s reconfigurable computer systems. This combination provides ease of algorithm development on a wide range of FPGA platforms – from inexpensive low gate-count boards to powerful high-end multi-FPGA architectures."

Allan Cantle, CEO of Nallatech, is quoted: "This strategic alliance is truly a case of taking the best elements of two companies to establish a powerful, scalable and affordable computing system for demanding applications. Starbridge’s Viva provides a powerful and easy-to-use front end tool for Nallatech’s FPGA-based hardware systems."

Kurt Dobson, CEO of Starbridge Systems, is also quoted: "Offering Viva with Nallatech’s scalable, modular hardware platform extends the benefits of Starbridge’s expertise in Hypercomputing to a much broader range of users. The Nallatech/Starbridge relationship makes high-performance reconfigurable computing accessible to the entry level user as well as the power user."


* Zuken says, "it has launched Circuit Adviser to the western market for systematically checking errors in a schematic; helping identify design problems early in the development cycle for improving quality and eliminating the requirement to re-run design cycles. Circuit Adviser is a module created to find hidden electrical problems in the schematic design held within CR-5000 System Designer using predefined electrical rules set by the library administrator. A task that would ordinarily involve considerable analysis time using SPICE-based simulators, can now be performed effortlessly using simple automatic rule checks. This module is an add-on solution that is fully integrated with the CR-5000 enterprise wide design environment."

"By implementing combined technologies that use a singular database throughout the portfolio, designers can benefit from the advantages of unified design information. Circuit Adviser can perform eight different electrical rule checks including voltage rating and ground supply polarity. This tool provides a methodical form of increasing quality, particularly important for companies adopting the six sigma approach."

*************************

* Somebody got a definitive explanation for this six sigma thing?