* AccelChip Inc. announced its 2005.3 version of the AccelChip DSP Synthesis and AccelWare IP toolkits for model-based design of DSP applications. New features include pipe-line insertion to increase design performance while lowering chip power, enhancements to the tool’s automated floating-point to fixed-point conversion utility, and updates to all third-party tool integrations to enhance interoperability.

Ken Karnofsky, Marketing Director for Signal Processing and Communications at The MathWorks, is quoted: "Model-based design enables engineers to quickly evaluate multiple design options by testing and optimizing their algorithms in the Simulink modeling environment before they deploy them in an embedded system, reducing design time and development and implementation costs. AccelChip DSP Synthesis and AccelWare can complement The MathWorks’ Model-Based Design solutions by providing a direct path to FPGAs and ASICs."

* ACE (Associated Compiler Experts) announced the latest release of the company's CoSy compiler development system. In so doing, the company says it's the first "to offer support for the new ISO/IEC Embedded C language extensions and to demonstrate highly efficient Embedded C compilers."

Per the Press Release: "Embedded C provides programmers of embedded systems with the appropriate handles to address specific hardware features in a standardized portable C-programming language. Conformant compilers translate the Embedded C sources into highly optimized code, taking full benefit of the target processor’s capabilities, thereby removing the need for non-portable DSP assembly-code and chip- or vendor-specific intrinsic functions."

Marco Roodzant, Vice President of Marketing and Sales for ACE, is quoted: "We are very pleased that quickly after the standardization of the language extensions by ISO, Embedded C compilers are now available. From this point on, there is no longer any excuse for not programming high-performance DSP-algorithms and embedded applications in the plain, readable and above all portable C-language."

* Ansoft Corp. announced HFSS v10. The company says the new release "introduces new capabilities for design-flow efficiency that allow users to easily share CAD models and results across existing CAD/CAE products. HFSS v10 further offers dynamic-link technology, which allows HFSS to co-simulate with other Ansoft products and extends HFSS applications to include RF/analog IC co-design, EMI/EMC and microwave heating."

Zoltan Cendes, Ansoft's Chairman and CTO, is quoted: "With the introduction of HFSS v10, I am excited that we are providing significant productivity gains to our current install base while empowering co-design for a new class of engineer working in the areas of EMI/EMC, microwave heating, RF/analog IC and Multi-gigabit designs."

* Ansoft also released a Windows XP Professional x64 version of HFSS v10. The company says, "The migration of Ansoft electromagnetic technology to a 64-bit operating system delivers additional capacity and speed to the simulation of high-performance electronic designs."

Zoltan Cendes, is also quoted in this Press Release: "Ansoft's support of 64-bit operating systems delivers the speed and capacity to solve the complex components characteristic of today's most challenging electronic designs and allows engineers to realize a true simulation-based design cycle."

* Denali Software Inc. and Samsung Electronics Co. Ltd. announced an agreement to develop and deliver IP products "that enable fast, efficient deployment of OneNAND interfaces for SoC designs. The first such product – Denali's Databahn OneNAND controller – deploys OneNAND memory by extending the read/write performance of OneNAND for designs of handsets and other embedded platforms that support synchronous burst NOR memory. The Databahn OneNAND controller also will work with designs that do not support synchronous burst NOR."

Jon Kang, Senior Vice President for the Technical Marketing Group at Samsung, is quoted: "Our goal is to enable customers to track the performance of OneNAND without leaving anything on the table, allowing customers to optimally differentiate their products, while accelerating the adoption of converged mobile solutions," said. "By working with Denali, we are providing customers with critical IP products for integrating OneNAND technology in order to extract maximum performance from their product designs."

* Denali Software also announced its Blueprint product, which "automates the generation and management of the hundreds, and often thousands, of control registers used in complex chip designs as a source for efficiency improvements in SoC design. Created for chip developers, Blueprint addresses all elements of register management, including description and generation of control register logic, assertions and verification models, firmware interfaces, and the accurate documentation necessary for system-level design.

Michael Uhler, CTO at MIPS Technologies, is quoted in the Press Release: "There is a great deal of value in having a tool to generate the hundreds or thousands of registers in today's ASIC designs. More importantly, Denali's Blueprint product gives system designers the ability to automatically synchronize and generate all the different views for these registers. Having accurate documentation, assertions, field maps, and header file information has a huge effect on both hardware and software developers – it can ultimately make or break a chips development schedule."

Serge Leef, General Manager of the SoC Verification Division at Mentor Graphics, is also quoted: "As a leading provider of SoC design and verification solutions, Mentor Graphics is committed to delivering high-quality products that provide real value to our customers. A key part of this value lies in enabling integration with other best-in-class products. For several years, our Seamless and Platform Express customers have enjoyed a very complementary relationship with Denali's products, and we see that same synergy with Blueprint, especially for IP-based design. Blueprint automates the generation of accurate, consistent specifications and integration views that are key for rapid integration of IP. This type of product can provide significant value for both IP providers and IP consumers."

* EMA Design Automation announced the release of its Power IC Model Library. The company says the PSpice library "incorporates over 150 time-domain simulation models for power electronic designs and gives designers capabilities previously unavailable for these popular parts – the ability to plug in a model, representative of the actual IC, and simulate the switching performance under actual operating conditions."

* Incentia Design Systems, Inc. and ITE Tech. Inc. announced that ITE has adopted Incentia DesignCraft and TimeCraft software as the logic synthesis and timing analysis tools in its production tape-out flow.

* Mentor Graphics Corp. announced release 2005.1 of the Capital Harness Systems (CHS) product suite. Mentor says it releases a new version of the CHS toolset twice per year – each new version being available to new customers, or as an upgrade for existing customers with a valid support contract. Version 2005.1 has 140+ enhancements including: preferred component declaration and selection, configurable release behaviors, extended name composition capabilities, flexible electrical analysis scoping, and whole-vehicle wiring diagram synthesis, among others.

Nick Smith, Product Marketing Director for Mentor’s Integrated Electrical Systems Division, is quoted: "Many of the enhancements we’ve introduced with CHS version 2005.1 have originated from customer requests. Because we have worked closely with our customers on this, we are confident this release strongly boosts the value to be gained from CHS, whenever any of the various tools in the toolset are deployed."

* Open Core Protocol International Partnership (OCP-IP) announced availability of the SystemC Transaction Level Monitor (TLM) Channel version 2.1.1, which includes a methodology white paper entitled "OCP TLM for Architectural Modeling."

Per the Press Release: "Version 2.1.1 improves module interoperability by unifying the way time is modeled in transaction level 1. Some TL1 API functions have also been redesigned to ensure interoperability, and new timing interfaces have been added to the TL1 channel for automating the setting of module timing parameters. Improved support for OCP thread busy signaling has also been added to TL1. In addition, a wrapper channel, which includes a clock input port is provided for TL1 to make the channel easier to use with EDA tools. Single-request, multiple-data OCP transactions have been implemented for TL2.The methodology package outlines the use of the OCP TLM in the same flow with the OSCI TLM, and introduces a newly defined modeling abstraction level, Architects View, using OCP TL2 or TL3 for interface modeling. The methodology package has extensive examples for modeling in different abstraction levels, and for making models of different abstractions interoperable.

Ian Mackintosh, OCP-IP President, is understandably proud: "Our System Level Design Working Group is full of the best and brightest engineers in the world from leading companies working on Transaction Level Models. We are particularly proud of the quality and ongoing evolution of the modeling standard we have pioneered."

* Silicon Canvas, Inc. introduced its Laker PnR Editor, which the company says is designed for complex SoC post-place-&-route editing and design closure. The company adds, "With this extension to our product line, our Laker solution greatly increases its capability in satisfying various layout applications including bottom-up full custom design, and top-down cell-based design."

Laker PnR Editor includes a grid-based router, "advanced" ECO editing functions, auto DRC correction, "tight integration" with Mentor Graphics' Calibre and Synopsys' Hercules verification tools, and integration with Novas' Verdi/Debussy/nECO tool set. In addition, the company says that the Laker PnR Editor is "the only layout editor that can directly access Synopsys' Milkyway, Si2's OpenAccess and Magma's Volcano databases." If that's not covering all the bases, what is?

Hau-Yung Chen, President of Silicon Canvas, is quoted: "The design concepts and features of conventional layout editors are based on the polygon-pushing methodology. This does not meet the needs of post-P&R editing requirements. The pain of time-consuming data translation and interoperability issues are intolerable during final post-P&R editing, just prior to tape-out. Designers either suffer with unfriendly editing capabilities of their current APR tool, or spend a lot of time on data translation using custom layout editors. Silicon Canvas continues to help its customers compete and win by speeding up time to market. The introduction of the Laker PnR Editor provides a tailored application-oriented solution to speed up the time required to tape-out SOC designs."

* SMSC announced its support for the royalty-free ULPI specification, which the company says it demonstrates through its USB3300 ULPI stand-alone peripheral, embedded host or On The Go (OTG) transceiver.

Steve Nelson, Vice President of Marketing – Connectivity Solutions at SMSC, is quoted: "As a promoter and one of the founding members of the ULPI Working Group, we are delivering breakthrough products for ASIC, SoC and FPGA designers considering the benefits of a stand-alone Hi-Speed USB PHY. As designs migrate towards the 90-nanometer technology node and beyond, we are seeing a dramatic shift towards utilizing a stand-alone PHY due to complex issues that exist when integrating a transceiver at these densities. These designers are now fully empowered to add Hi-Speed USB connectivity to their products while avoiding the risk and cost of trying to integrate 5-volt tolerant analog PHY circuitry. Customers are also looking to SMSC to implement multi-port embedded host expandability via a single ULPI controller and interface, which is expected to further tip the scale in favor of designs leveraging the ULPI interface and the USB3300."

* SynaptiCAD announced it has ported all of its products to Linux operating. The company says that all the tools share a common platform-independent graphical interface "that provides users with the ability to easily move from one OS to another and share their work across different platforms."

Dan Notestein, President of SynaptiCAD, is quoted: "The speed of Linux on relatively low-cost x86 based hardware and the increasing availability of high quality EDA software has made it an attractive environment for digital design. For some time we have had our console-based simulation tools available on Linux since these were relatively easy to port, but the increasing demand for our GUI-based products, especially our timing diagram editing products, made it a logical next step to port these products as well."

The next logical step is to go fishing!