May 11, 2005

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Telelogic and MatrixOne, Inc. announced a "Customer Needs Management solution" that integrates the Telelogic DOORS requirements management tool with the MatrixOne Product Central tool, that the companies say is designed for "managing a portfolio of products, features and configurations throughout the product lifecycle."

The Press Release says that, "Together, MatrixOne and Telelogic deliver a solution that closes the gap between requirements definition and design and provides an enterprise-wide view of product requirements to all product stakeholders – sales and marketing, product management, systems and software engineers, electrical, electronic and mechanical engineers, manufacturing and even customers and suppliers – in one single version of truth."

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** Accent and Giga Scale Integration Corporation (Giga Scale IC) announced that Accent has chosen Giga Scale IC's InCyte software tool for its "early silicon chip estimation and architectural exploration needs."

Claudio Fasce, Vice President of Business Area Electronics for Accent, commends his vendor: "InCyte is alone among EDA tools in facilitating accurate chip estimation and cost-saving design exploration. InCyte adds value that we can pass on to our customers as we realize the cost savings that accrue by analyzing our design and IP choices early."

** In a similar vein, DongbuAnam Semiconductor and Giga Scale IC announced that DongbuAnam has selected InCyte for its "early silicon technical and economic estimation and analysis."

Heung Joon Park, Senior Executive Vice President, of DongbuAnam Semiconductor, says his company is now well armed: "InCyte fills a critical gap in our arsenal of EDA tools. Early, accurate estimations of die size, power, leakage, and yield made possible by InCyte help us to deliver higher quality, lower cost IC's to our customers."

** Agilent Technologies Inc. announced that NEC Compound Semiconductor Devices Ltd. has selected the Agilent heterojunction bipolar transistor (HBT) model as its standard simulation model for high-frequency gallium arsenide (GaAs) HBT development.

Per the Press Release: "The Agilent HBT model, developed for use with Agilent’s Advanced Design System (ADS) electronic design automation (EDA) software, provides greater accuracy and improved convergence over other available HBT models. It reduces design turns and shortens the design cycle of high-frequency integrated circuits for applications such as power amplifiers for wireless handsets and wireless local area networks."

Agilent’s HBT model was designed specifically for GaAs and indium phosphide (InP) processes used in high-frequency design, and supports both single and double heterojunctions. The new model is based on research originally performed by a working group led by the University of California at San Diego for a GaAs physics-based model known as the DARPA/UCSD HBT model. Agilent engineers developed an integrated nonlinear transit-time and charge storage formulation for the model, removed discontinuities and integrated the new model into its Advanced Design System EDA software. The result is an enhanced HBT model for high-frequency circuit design that provides the unsurpassed accuracy and an increase in successful simulations due to improved convergence."

** Modelithics, Inc. says it is now shipping a "comprehensive and feature-rich Non-Linear Transistor (NLT) library." The NLT library is now available for use with Agilent Technologies’ Advanced Design System (ADS).

Joe Civello, ADS Product Marketing Manager at Agilent's EEsof EDA Division, endorses the release: "Designers choose ADS for its industry leading simulation technology. Good models are critical to getting accurate results from our simulators. I am pleased, but more importantly our customers are pleased, with Modelithics' continued expanded offering of high-quality, well-documented model libraries for commercially available components."

** Altium Ltd. announced the "unification" of the company’s DXP 2004-based products under the Altium Designer name.

Per the Press Release: "The latest 2004 versions of Altium’s Protel, Nexar, CircuitStudio, and CAMtastic products all are based on the company’s DXP 2004 technology integration platform. What’s more, each of these products is a subset of an overall DXP 2004-based design system that provides a complete and diverse set of capabilities for electronic product development. To coincide with the release of Service Pack 3 for DXP 2004, Altium has introduced the name Altium Designer to represent this complete DXP-based design system. The capabilities of Protel, Nexar, CircuitStudio, and CAMtastic remain unchanged, but these brands now represent licensing options of Altium Designer. Altium has introduced Altium Designer to better reflect the unified nature of its overall DXP-based design system, which provides a single, integrated application that encompasses all the capabilities necessary for electronic product development."

Nick Martin, Founder and CEO of Altium, is quoted: "Today the availability at relatively low cost of high-capacity, high-performance programmable devices such as FPGAs is shifting the balance again and allowing previously fixed design elements such as the processor and its peripheral components and logic blocks to be moved into a ‘soft’ domain. To harness this ‘soft’ future and take advantage of the benefits that it offers, a unified approach to electronic product development is required. This is the approach we’ve taken with our product development and is represented by Altium Designer."

** Aprio Technologies Inc. announced a technology partnership with NEC Electronics, which calls for collaboration on new RET technologies and the integration of that technology into NEC Electronics' manufacturing flow. Aprio says its DFM products "will be applied to NEC Electronics' methodologies in advanced IC manufacturing throughput, robustness and accuracy by employing modular, hierarchical, and incremental approaches in the handling of reticule enhancement technology (RET) … The agreement includes commitments by both companies for collaboration and the commitment of resources, both financial and staffing. Sumisho Electronics, Aprio's distributor in Japan, played a key role in defining the objectives and the details of the partnership to the satisfaction of all parties."

Kazu Yamada, Associate Vice President and General Manager at NEC's Technology Foundation Development Division, is pleased: "We are quite impressed with the technology Aprio has developed so far. We feel they truly understand DFM issues and are eager to work with them on extending and deploying their solutions to give NEC Electronics a competitive edge in advanced semiconductor processes."

Mike Gianfagna, Aprio's president and CEO, is pleased as well: "For a relative newcomer such as Aprio to receive a firm validation by a company of NEC Electronics' stature is a sign that we are on the right track."

** Atrenta Inc. announced several product offerings that the company reports are major releases of new technology from the company.

The 1Team:Analyze design automation tool is, per the company, designed to "greatly improve the quality of chip designs at the point of creation, slashing the risk and improving the economics of developing SoCs and complex ICs. 1Team:Analyze helps chip designers ensure at the outset that designs are correct and optimized for testability, power consumption and other crucial objectives. Using advanced static and dynamic analysis, 1Team:Analyze diagnoses structural, coding and consistency problems early in the design cycle, at the register transfer level (RTL)."

"It traces problems to their source, guides users to successful resolutions and can even automatically fix errors. It pinpoints critical problems and sub-optimal design elements normally discovered, if at all, much later, after time-consuming simulation, synthesis and gate-level analysis. Examples include synchronization and SoC integration requirements, combinatorial loops and inefficient resource utilization. 1Team:Analyze also validates that design constraints are correct and consistent throughout the design cycle, and it performs comprehensive and extensible electrical rules checking (ERC)."

"In addition, 1Team:Analyze Test and 1Team:Analyze Power options enable users to tune and automatically correct their RTL designs to meet testability and power consumption goals. The 1Team:Analyze Test option predicts ATPG (automatic test pattern generation) test coverage and pinpoints testability issues as the RTL description is developed. … The 1Team:Analyze Power option enables users to tune their RTL designs for power consumption, eliminating much of the back-end work traditionally required."

The 1Team:Verify chip verification tool is, per the company, the "first solution to bring the benefits of best-of-breed assertion-based verification (ABV) to logic designers. With 1Team:Verify, designers can apply sophisticated ABV at the initial, RTL (register transfer level) stages of development, automatically and without any verification expertise. 1Team:Verify … catches bugs earlier, and detects many critical "corner-case" bugs that traditional simulation-based verification methods miss. Examples include errors involving clock domain crossings (CDCs), finite state machines (FSMs), handshake mechanisms and bus structures. 1Team:Verify can perform many of these checks automatically, without user intervention. In addition to its fully automatic checking, 1Team:Verify allows more experienced users to write their own assertions using the assertion language of their choice."

"1Team:Verify can pinpoint functional corner-case bugs and hard-to-target problems that sneak through simulation. These include CDC errors such as cross-domain fan-ins, reconvergence, handshake violations, gray code and data hold violations; as well as FSM problems such as deadlocks between communicating state machines, unreachable states, transitions that may not fire due to asynchronous signals and FSM registers stuck at constant values. In addition to catching problems that conventional tools miss, 1Team:Verifiy minimizes the many false CDC violations that traditional tools over-report."

If you have time, the following technical info from Atrenta is useful:

"ABV is an important complement to traditional simulation-based verification. While simulation is inherently incomplete and explores only a few paths through the state space of a design, ABV can exhaustively verify design structures. Whereas cycle-based simulators are not intrinsically capable of detecting timing-dependent effects that underlie CDC errors and many other bugs, ABV can. And while simulation provides no means of tracing many problems to their source in the RTL, ABV provides feedback on exactly how and where the bugs occurred."

"Until now ABV has demanded significant expertise, requiring hand-off of RTL designs to verification specialists, who then applied ABV. If bugs were found, the design was handed back to the RTL team for corrections, then back to the verification team for re-checking, and so on. 1Team:Verify minimizes these time-consuming iterations by allowing RTL designers to carry out many ABV checks themselves, automatically. 1Team:Verify generates and validates a large number of assertions (over 10,000 assertions for a 500,000-gate design on average), providing a high degree of verification coverage without any user intervention."

** Beige Bag Software, Inc. says it has signed a formal agreement with Zuken that arranges for the inclusion of Beige Bags B2 Spice circuit simulation software in Zuken¹s new CADSTAR promotional bundles for the Americas. Beige Bag also says it is currently in the process of advanced development for further integration into the CADSTAR design environment. Coding for the first stage of integration has already been completed. Beige Bag is also planning to release B2 Map CS a collection of tools for the automatic mapping of simulation models for CADSTAR user libraries.

** Cadence Design Systems, Inc. and Faraday Technology Corp. announced that Faraday has joined the OpenChoice IP program to co-develop with Cadence a list of library views. The companies say the libraries are being designed to facilitate digital implementation and signal integrity under UMC's 130-nanometer Fusion process. The library view generation process will be qualified and validated by both Faraday and Cadence research and development teams. Under the process, Faraday's customers will have the ability to handle digital implementation and SI signoff in the Cadence Encounter(TM) digital IC design platform.

** Cadence Design Systems, Inc. announced that Ricoh Company, Ltd. taped out a 3-million-gate chip "ahead of schedule and with reduced gate count using the Cadence Encounter digital IC design platform, including RTL Compiler synthesis. "

Kenji Wakabayashi, General Manager at the Imaging System LSI Development Center, Electronic Devices Company, at Ricoh, is quoted: "Ricoh is a diversified office automation equipment and electronics provider doing advanced IC designs for complex applications. The top-down synthesis approach enabled us to quickly and easily fix our scripts for the 3-million-gate design within two days, which we had expected to have taken two weeks. Since time to market is important for us, Encounter RTL Compiler synthesis will help make us more competitive."

** Denali announced that its PureSpec verification IP product now supports the verification of Ethernet designs.

Vic Juneja, Product Marketing Manager for Denali, congratulates his employer: "PureSpec is the most trusted verification IP solution in the industry. Denali has an excellent track record for providing high-quality verification IP for other interfaces such as PCI Express and DDR memory and we are leveraging the same proven architecture to now support Ethernet interfaces. Our customers rely on us to provide a very high-quality solution that works with all the latest testbench tools and languages for out-of-the box productivity." Good news, indeed.

** FishTail Design Automation announced that it has been issued a patent (No. 6,877,139) by the U.S. Patent Office. The new patent, titled "Automated approach to constraint generation in IC design," encompasses the ability to generate timing exceptions (false paths and multi-cycle paths) from synthesizable design descriptions.

The Press Release says, "Previous approaches have attempted to identify false paths at the gate-level and have inevitably run into computational limits. The fundamental innovation that FishTail has brought to the marketplace is the ability to quickly discover false and multi-cycle paths on large and complex designs by examining their RTL descriptions. While the patent is not limited to a specific approach to timing exception generation, the Focus product from FishTail automatically identifies the control logic on a design and performs a functional abstraction of the non-control portions of a design. Functional abstraction ensures that the downstream formal analysis of the design to identify false and multi-cycle paths is fast and memory efficient."

Ajay Daga, Founder and CEO at FishTail Design Automation, is confident: "The patent that has been awarded to us confirms what our customers acknowledged when we launched the Focus product early last year – that we have achieved a fundamental technical breakthrough in the EDA industry. We are the only game in town when it comes to a production-ready tool for the generation of timing exceptions on multi-million gate designs.

** Flarion Technologies said it used Emulation and Verification Engineering’s (EVE) hardware-assisted verification platform to design Flarion's new FLASH-OFDM mobile broadband chipset. Flarion said it used EVE’s tools for regression testing of the ASIC that will soon be tested in silicon.

Frank Lane, Senior Director of Product Architecture at Flarion Technologies, is quoted: "Flarion selected ZeBu after evaluating several hardware emulation systems and found it was best suited for the regression testing that Flarion does throughout the design project to tapeout. Our design demands are rigorous and we expect the same from our design tools."

** Impulse Accelerated Technologies, Inc. and Pico Computing, Inc. announced a joint release, a Platform Support Package which the companies says will allow the Impulse C tools to compile C algorithms to Pico’s new E-12 line of CompactFlash FPGA accelerator cards. The companies also says that the "resulting software-programmable hardware accelerator offers the potential for 10X to 400X increases in processing speed of desktop and embedded applications, in a form factor the size of a standard CompactFlash memory card."

Also per the Press Release: "The Pico E-12 PCMCIA cards provide massively parallel hardware computing resources in a low-power (less than one watt), self-contained CompactFlash package. Impulse C and the Impulse CoDeveloper tools give software programmers access to this computing resource by allowing hardware accelerators to be compiled directly from C. Impulse tools optimize the C code to exploit the FPGA’s parallel processing capability, resulting in potentially large factors of acceleration."

Robert Trout, founder and President of Pico Computing, is pleased: "We are excited by the growth of FPGAs as general-purpose computing platforms. To that end we are providing a design environment designed more for software programmers. The Impulse tools provide such an environment."

David Pellerin, Cofounder and President of Impulse, is pleased as well: "We are great believers in FPGAs for general-purpose computing. The Pico E-12 lets software engineers accelerate algorithmic hot spots in a fraction of the time it would take to do it in VHDL."

** Mentor Graphics Corp. and LSI Logic Corp. announced the Seamless processor support packages (PSPs) for the LSI Logic ZSP400 and ZSP500 DSP cores. The companies says that by "Utilizing the Seamless PSPs with the ZSP cores, designers have a platform in which to concurrently develop hardware and software in complex SoCs, saving time and money, and validating that hardware and software are synchronized before prototypes are manufactured."

Ai Wei, Vice President of HiSilicon Technologies Co., Ltd., is delighted with the technology: "Seamless has become an important part of the verification flow for the SoCs we design. LSI Logic and Mentor’s collaboration in delivering Seamless models for the ZSP cores enables us to efficiently verify the hardware and software in systems that embed them."

Meanwhile, Tuan Dao, Vice President and General Manager of the ZSP Product Division at LSI, likes Mentor: "By easing the co-verification burden, Mentor Graphics allows our customers to achieve design closure quickly and correctly, enabling the successful deployment of ZSP-based products to the market."

Similarly, Serge Leef, General Manager of the Mentor Graphics SoC Verification Division, likes LSI: "By enhancing its DSP architecture with robust tools and solutions, such as the Seamless PSPs, the LSI Logic ZSP Division is demonstrating its commitment to the market and its strength as a leader in licensing DSP cores and software."

** Open Core Protocol International Partnership announced that the OCP interface is the "latest addition" to the Mentor Graphics CheckerWare lverification IP library. The CheckerWare solution is comprised of a library 100+ assertion checkers and protocol monitors. The monitor currently supports OCP v2.1, the organization's newest standard, announced in March. OCP 2.1 includes profiles for the most commonly coupled OCP features and an advanced tagging scheme for enhancements in out-of-order processing.

Ian Mackintosh, President of OCP-IP, is pleased: "OCP has a robust, thriving infrastructure supported by many independent companies such as Mentor that provide excellent services and products. This is a testament to the tremendous adoption we have seen throughout the industry."

** Prolific Inc. announced that Spansion LLC purchased Prolific's ProGenesis software to automate its internal development of standard-cell libraries. The companies says software will be used "to accelerate creation of standard cells for Spansion's award-winning Flash memory products."

Jim Thomas, Vice President of Product Development at Spansion, is quoted: "As Spansion expands its product portfolio, we are finding significant advantages to having control over our library IP. What began as a library service deal became a software purchase when we saw ProGenesis' power and flexibility."

** SMSC announced the USB2230 USB-to-Infrared and 15-in-1 flash media device controller. The company says this product combines flash media and infrared technology, "enabling designers to deliver a simple point-and-shoot experience. Consumers can now easily and affordably transfer digital images from their camera phones and other Infrared Data Association (IrDA) enabled devices in a manner consistent with how they transfer images from their Digital Still Cameras (DSCs)."

Morry Marshall, Vice President of Strategic Technologies at Semico Research Corp., celebrates products that enhance quality of life for consumers: "Cell phone cameras have expanded the boundaries of digital photography. However, many consumers don’t know how to download the photos from their camera phone, so the pictures are shown to friends or family and then erased. Downloading requires a connecting cable, too challenging and cumbersome, or a telephone data connection, too slow and expensive. The SMSC infrared solution, combined with a flash card reader provides a simple, speedy, intuitive connection, point and download, which should find a ready market."

** Stelar Tools recently announced a new release of its HDL Explorer product, which the company says is the first EDA tool to deliver "rapid RTL closure, the process of getting a design clean at the register-transfer level, before synthesis."

The Press Release says, "HDL Explorer provides a unique combination of technology for creating new designs and for exploring new and legacy designs and testbenches – all while using best known methods (BKMs). To enhance design reuse, HDL Explorer lets designers automatically route signals, move blocks, and connect signals through the hierarchy. In addition, it provides the ability to encapsulate random logic into a new block or break an existing block into smaller blocks. And the tool now features full Verilog, VHDL and mixed Verilog/VHDL support."

Stelar Vice President of Marketing Steve Sapiro, is quoted: "Our customers spend a great deal of time manually routing signals and moving and reconnecting modules in a design hierarchy. HDL Explorer now automates these manual tasks, making it a must-have tool for anyone doing HDL design."

** Synopsys Inc. introduced a new product, PrimeRail for power network sign-off. The company says the new product is "tightly integrated within the Galaxy Design Platform [and] allows designers to predict voltage drop during floorplanning, perform post-layout static and dynamic analysis with on-chip decoupling capacitance and full-chip sign-off with package parasitics. PrimeRail features the new hybrid technology for highly accurate gate and transistor-level GDSII-based power network sign-off. The hybrid technology simulates arbitrary RLC (resistance-inductance-capacitance) networks enabling sign-off quality dynamic analysis while minimizing memory usage."

Antun Domic, Senior Vice President and General Manager for the Synopsys Implementation Group, is quoted: "We introduced our PrimeTime product for static timing sign-off in 1996, and extended its capabilities to address signal integrity effects with PrimeTime SI in 2001. With the introduction of PrimeRail, we are now enabling PrimeTime customers to address the increasing impact of voltage drop on timing. As a result, the Galaxy Design Platform now offers a comprehensive design sign-off solution that continues to ensure first-pass silicon success."

Alex Shubat, CTO and Vice President of R&D at Virage Logic, is quoted: "Today, embedded memory IP contributes up to 70 percent of a chip’s area – and accurate power network sign-off is essential to verify these memories for high reliability and yield. We will continue collaborating with Synopsys on our memory verification flow, and will look to standardize on PrimeRail for sign-off of our 90 and 65-nanometer Area, Speed and Power (ASAP) Memory and Self-Test and Repair (STAR) Memory System product lines."

** Synopsys also announced that its DesignWare PHY and digital controller IP for the PCI Express standard is the "first Data Link and PHY solution from a single vendor" to pass compliance by the PCI-Special Interest Group (PCI-SIG).

Guri Stark, Vice President of Marketing in Synopsys' Solutions Group, is quoted: "As the leading provider of PCI Express IP, we have taken an active role in lowering the total cost of ownership for our customers using this faster protocol. Our customers depend on us to save them money when they deploy PCI Express technology because they get a solution that is verified to their application and hardened with substantially less Link-PHY integration risk."

** Synopsys announced, as well, that Faraday Technology Corp. used Synopsys' VCS verification tool and Vera testbench automation tool to verify Faraday's FA series of 32-bit RISC processor cores. "Synopsys' industry-leading verification solutions enabled Faraday's verification team to complete verification with a high quality of results and a high degree of confidence." Wow.

Thomas Hsieh, Associated Vice President of R & D at Faraday, is quoted: "We are committed to providing our SoC customers with high-quality processor cores and the means to achieve design success. In our endeavor to deploy the best verification solution for our CPU cores, we used the native coverage features in Synopsys' VCS RTL verification solution to quickly and easily check the completeness of our RTL verification. We also used the Vera tool to create a comprehensive verification environment to allow us to ensure that the functional coverage goals were met as specified."

** Tensilica, Inc. and Emulation and Verification Engineering (EVE) have announced an agreement that the companies say, "speeds the design of complex SoCs with multiple Xtensa processors." The agreement will allow Tensilica's customers to download RTL code produced by Tensilica's Xtensa Processor Generator into EVE's hardware prototyping platform for verification. Tensilica's Xtensa Xplorer development environment will be linked to EVE's ZeBu hardware-based verification product to provide hardware/software co-verification.

Alain Raynaud, EVE's technology center director, is quoted: "With this methodology, we significantly accelerated the development of the whole-chip hardware prototype, so engineers can spend their time designing the application and running it on the prototype at MHz speed. It significantly reduces the need for block-level hardware verification and eliminates the pain traditionally associated with hardware emulation."

Larry Przywara, Director of Strategic Alliances for Tensilica, is also quoted: "While our processors are guaranteed correct by construction, they must be integrated into a highly complex SoC. By providing our users with easy access to EVE's ZeBu prototyping platform, they should be able to quickly verify their entire SoC designs."

** TransEDA announces its imPROVE-HPK AXI automated formal verification tools, which the company says is to be used for the verification of designs using the AMBA AXI (Advanced eXtensible Interface) protocol.

Per the Press Release: "The AMBA AXI Hardware Protocol Kit (HPK) automates the verification of AXI compliant hardware designs and adds to the existing range of TransEDA HPKs for AMBA AHB and APB, OCP1.0 and OCP2.0, PCI and PCI-X. Providing over 150 coverage scenarios, more than 100 properties, worst-case performance analysis and support for multiple-interface designs, the use of imPROVE-HPK AXI saves weeks of modelling time by automatically creating complete protocol environments around your design to provide fast, accurate and exhaustive verification. Protocol violations caused by design bugs are swiftly identified and counter-examples - generated in VCD format, or as Verilog or VHDL test benches - allow speedy targeting and resolution of any design problems." This is good news.

** Verific Design Automation announced that Calypto Design Systems, Inc. has licensed its HDL component software.

Gagan Hasteer, Calypto’s Vice President of Engineering, likes Verific: "The decision to work with Verific was an easy one for us because its HDL Component Software is the standard front-end source code. Verific’s team is exceptional and its support is unmatched. Our experience working with Verific has been excellent."

Happily, Verific’s COO Michiel Ligthart likes Calypto as well: "The Verific team takes great pleasure in working with a company like Calypto whose goal is to reduce the verification bottleneck."