Synopsys, Inc. announced that NVIDIA Corp. has adopted Synopsys' Galaxy 2004 test tool for its latest designs. That win is based on yet another nod to what's going on downstream: "On large DSM devices – where increasingly more silicon area is consumed by wires rather than transistors – there are relatively more manufacturing defects arising from bridging (wire-related) faults than from stuck-at (transistor-oriented) faults. Synopsys' Galaxy 2004 test solution addresses this challenge and allows NVIDIA to use layout extraction information to generate bridging fault tests with TetraMAX DSMTest."

Dan Smith, Director of Hardware Engineering at NVIDIA, remembers a moment of revelation: "We worked closely with Synopsys to improve modeling of DSM defects when we realized this would become a key test requirement for our upcoming graphics processor designs. Synopsys now provides us with complete automatic test pattern generation support for bridging faults. Using TetraMAX DSMTest enables us to test for transition, bridging and path-delay faults, and thereby improve the quality we deliver to our customers."

Synopsys also announced that the Galaxy Test flow has enabled STMicroelectronics to "significantly increase its fault coverage and reduce tester time on its latest high-volume printer chipset." ST says that it can, today, reduce its test data volume by a factor of 40 and test application time by a factor of 13, detect seven percent more faults, and significantly reduce defective parts per million without increasing test costs." Jot down those stats. You'll be tested on them later.

Meanwhile, Loris Valenti, Design Manager at ST's Computer Peripherals Group, Printer System Division, offers more numbers for you to memorize: "Using the SoCBIST solution in Galaxy Test, we can compress our scan test data volume by 97.25 percent to significantly reduce time on the tester while increasing the amount of defect coverage. We estimate that, even with a test time reduction of four times over traditional scan, we can increase our transition fault coverage by seven percent. We actually were able to reach a test time reduction of 13 times and thereby reduce our defective parts per million by several hundred units over previous runs where SoCBIST was not used. In volume production, the net result is a significant improvement in the quality of shipped parts without an increase in test cost."

QuickLogic Corp. announced a partnership with Renesas Technology Corp. that the companies say will "enable low-power solutions for the rapidly expanding WiFi market."

They add that the partnership will allow OEM customers who use the Renesas embedded SH processor to develop additional consumer WiFi applications targeted at users in the home, office, and public places. The technology underpinning of the partnership consists of Renesas Technology's SH processor and a programmable companion bridge from QuickLogic that allows for connectivity to miniPCI and Cardbus based WiFi modules or chipsets. The companies also want you to know that initial chipsets from the partnership will target wireless voice-over-IP (VoIP) – referenced by the euphonic, though unpronounceable acronym, VoWLAN – and battery-operated handheld applications that support the IEEE 802.11a/b/g specifications.

PowerEscape, Inc. introduced what the company describes at its second generation products, PowerEscape Architect and PowerEscape Analyzer. The company says that the tools "open a new era of power optimization strategies for both hardware and software engineers. The tools reveal the ideal memory architecture to the system architect while exposing power bottlenecks in embedded code to the software developer." This should be very good news for the masses. That at the fact that enhancements to PowerEscape Architect allow "virtually any target platform, including processor registers, internal memory, caches and external memory to be characterized and then analyzed using C application code. Near real-time execution of embedded C code reveals the optimum cache size, cache policies, and memory hierarchy."

Guido Arnout, President and CEO of PowerEscape, is clearly jazzed: "Traditional approaches to analyzing cache efficiency and memory interactions are too slow and provide no details about dynamic power consumption. Outstanding simulation performance, power-aware platform models and detailed reports correlating software and memory interactions are key reasons why tradeoff studies can be conducted in just a few hours using the PowerEscape tools. PowerEscape's energy-efficient software strategy extends and complements existing power optimization strategies such as clock gating and voltage-frequency scaling." He forgot to add that where time is saved, money is earned.

Mentor Graphics Corp. announced that ATI Technologies Inc. is using Mentor's VStationTBX verification accelerator, which is based on Mentor's behavioral testbench compilation and transaction-based verification technologies. Not surprisingly, the companies say the VStationTBX tool "significantly accelerates the functional verification of ATI's high-performance graphics processors used in high-end desktop personal computers, set-top box and game applications."

Mentor Graphics also announced that the Institute of Computing Technology (ICT) of the Chinese Academy of Sciences has selected the VStationPRO emulation system as its verification platform for its Goodson series CPU chip. Tang Zhimin, the technical principal of the Goodson chip project at the Institute of Computing Technology of the Chinese Academy of Sciences, is thrilled: "With the great help of Mentor's advanced VStationPRO verification system, ICT will be able to slash verification time and supply its customers with fully verified Goodson CPUs in a short time period, which will accelerate its adoption."

Finally, Mentor Graphics announced its XtremePCB design tool that the company says is a technology that allows multiple members of a PCB design team to work simultaneously on a design from a single database on a global network, whether they are in the same office or dispersed all over the world. The Press Release says, "It allows electronic companies to significantly reduce their design cycle time, to meet today's accelerated time-to-market demands."

MatrixOne, Inc. announced the availability of its Synchronicity Developer Suite V4.1. Per the Press Release: "Developer Suite V4.1 introduces a new DesignSync package, DesignSync CTS (Custom Type System). DesignSync CTS allows customers to extend DesignSync's core EDA Data Awareness and create a plug-in to recognize and manage data from other EDA tools that are not supported out of the box."

"MatrixOne is the only semiconductor design data management provider that offers production-level integrations to multiple data formats from leading EDA vendors such as Cadence OpenAccess, Cadence CDBA, and Synopsys Milkyway. With the addition of DesignSync CTS, the Synchronicity Developer Suite now has the ability to interface to any EDA tool, even customer proprietary tools. Developer Suite V4.1 is the first Synchronicity-based product release since Synchronicity was acquired by MatrixOne in August of this year and demonstrates MatrixOne's dedication to extending and enhancing the Synchronicity product line." Always nice to hear that the parent company is dedicated to supporting and enhancing the acquired technology.

Impulse Accelerated Technologies, Inc. announced the newest edition of its CoDeveloper C to RTL design tools, which adds support for Altera’s SOPC Builder and the Quartus II, Version 4.1 design software. Per the Press Release: "CoDeveloper makes it possible to describe, debug and test mixed hardware/software applications using standard C development tools such as Visual Studio™ and GCC/GDB – and compile those applications directly to Cyclone or Stratix devices without writing low-level VHDL or Verilog. CoDeveloper optionally generates the Avalon interface used in SOPC Builder."

Joe Hanson, Director of Marketing for System Level Tools at Altera, "CoDeveloper is an excellent complement to existing software and FPGA development tools. The Impulse C philosophy is to allow parallelism to be expressed at the system level – within the context of standard ANSI C – while the CoDeveloper compiler frees programmers from the drudgery of extracting process-level parallelism and creating equivalent HDL code. With SOPC Builder support, the connectivity of these specialized blocks to other system resources is fully automated."

Hong Kong Science and Technology Parks Corp. (HKSTP) and Synopsys announced that HKSTP has licensed Synopsys' DesignWare IP cores portfolio. C.D. Tam, chief executive officer of HKSTP, is quoted in the Press Release: "It is fundamentally important that designers have access to complete, well designed and verified IP cores to accelerate time-to-market and time-to-volume for new SoC ICs being designed. Designers can now focus on their core competencies, because they can rely on Synopsys' standards-based IP cores that have been pre-verified and proven in silicon by many leading IC companies." Couldn't have said it better myself.

Cadence Design Systems, Inc. and ARM announced signal integrity (SI) views from the ARM for Foundry Program Partners (not sure where the hyphens belong in that compound modifier).

Meanwhile, for the technical among you, the Press Release says, "For designers incorporating hardened ARM processors into their designs, these views give access to critical data required to perform detailed voltage drop and SI analysis. This analysis speeds time-to-market of nanometer-scale SoC designs by rapid detection and resolution of critical SI issues. …As customers move to 130 nanometers and below, voltage drop and SI issues pose increased risks of chip failure and poor yield. When combined with the growing use of hardened IP, the risk of critical design problems due to SI issues is even greater because designers previously had no SI views for the hardened IP. This joint solution provides the critical characteristics of hardened IP processors provided by ARM that will enable designers to find and correct SI problems earlier in the design process, speeding time-to-market for ARM Partners."

Cadence also announced that Toshiba Corp. and Toshiba Microelectronics Corp. successfully taped out a 24-million-gate chip using Cadence SoC Encounter. The chip, with an end application in digital consumer electronics, is Toshiba's largest to date, and was designed using Toshiba's TC300 process for 90-nanometer technology. (I've asked this rhetorically before, does anybody ever announce an unsuccessful tapeout?)

Anadigm introduced two new field programmable analog arrays (FPAAs) that the company says offer "twice the processing capability of the company’s entry-level device at an aggressive price point. These new devices open the way for programmable analog implementations in high-volume audio, industrial, and medical systems." (Query, what's a passive price point?)

The AN122E04 and AN222E04 both have "streamlined" I/O configuration options, and the same configurable analog block (CAB) resources as Anadigm’s original FPAA products, which the company adds will give designers "all the signal processing capabilities they need for high-volume analog filtering, sensor conditioning, and basic PID control applications."

Get with the program if you don't know that FPAAs serve as the analog equivalent to an FPGA, but the newly introduced FPAA products can be used to replace discrete components and analog ASICs and ASSPs with a programmable, pre-tested, single-chip device that puts analog functions under software control.

Altium Ltd. announced support for an expanded range of FPGA daughter boards for its LiveDesign-enabled, FPGA-based development board, the NanoBoard. The additional daughter boards cover popular devices ranging from CPLDs to high-performance, high-capacity FPGAs and greatly enhance the versatility of the NanoBoard platform. Both Altera and Xilinx are mentioned in the announcement.

Altium separately announced a new plug-in daughter board supporting the Xilinx Virtex-II Pro FPGA as part of a comprehensive FPGA daughter board release for its LiveDesign-enabled FPGA-based development platform.

Per the Press Release: "The NanoBoard. Altium's NanoBoard is unique among FPGA development boards in that the target device is housed on a swappable daughter board, allowing engineers to develop for a variety of devices using the same platform. The new Virtex-II Pro daughter board incorporates a Xilinx XC2VP7-6FG456C(TM) FPGA that contains 11,088 logic cells arranged in 4,928 CLB slices. The device features a 'hard' Power PC 405 processor core and four high-speed Rocket-IO transceivers to provide a high-performance, fully embedded systems platform. Direct access to two of the Rocket-IO transceivers on the chip is provided by eight gold-plated coaxial connectors mounted across the top of the daughter board. The board comes with four coax loop-back connector cables for the transceivers, and includes Nexar design examples showing the use of the transceiver channels." More on this topic next week.

Accelerated Technology announced it has combined its UML (xtUML) modeling tool with its prototyping product. The company says the Nucleus BridgePoint for UML modeling suite and the Nucleus SIMdx prototyping environment provides "a complete hardware-independent platform for developing embedded applications. Software developers can now develop entire applications and verify them graphically on the development host, dramatically increasing the availability of the development platform." Excellent news.

Getting technical: "The use of high-level modeling in the embedded world allows embedded application developers to focus on the application rather than the deployment hardware by raising the development abstraction level above the traditional high-level languages. The use of xtUML language specifically allows the modeled application to be executed and hence verified at design time, and then translated into either C or C++ to be compiled directly for an embedded system. By importing this translated code into the Nucleus SIMdx prototyping environment, a new level of system level prototyping is realized."