Adveda B.V. announced its Univers Modeler, an extension to Adveda’s RTL simulator, which generates a SystemC wrapper or a PLI wrapper around a native simulation model, compiled within this simulator. The company says this gives users up to 100x faster simulation speeds within their own simulation environment through its PLI or SystemC interface.

Per the Press Release: "Univers Modeler takes the original RTL-code and converts it automatically to a cycle-accurate simulation model at a higher level of abstraction, wrapped in SystemC. The generated model runs faster than an RTL simulation, similar to the speed reached with manually written SystemC models. Using Univers Modeler saves designers many man months of writing models by hand. It also guarantees correct functional and cycle-accurate behavior, allowing designers to debug their real RTL design rather than just a model of the design. The Univers Modeler can also wrap these models with a PLI interface, allowing the models to be used within existing RTL simulators. It handles the full synthesizable RTL syntax, including multiple asynchronous clocks, asynchronous resets as well as tri-state signals. The first production release will support the VHDL RTL language, and is available immediately."

Altium Ltd. announced that it’s adding support for Xilinx, Inc.'s new Spartan-3 platform FPGAs to its Nexar system design software. Spartan-3 device support will be added to Nexar, and Altium is currently developing a Spartan-3 daughter board that will plug into its FPGA-based development board, which it calls a NanoBoard. Altium has also added support for Xilinx Synthesis Technology and Xilinx's ISE logic design software to Nexar.

Also from Altium - The company released version 3.0 of its TASKING M16C software development toolset that includes new Viper compiler technology. The company says various benchmarks have shown that this version of the toolset enables an increase in code efficiency, with increases in execution speed of up to 40 percent and code size decreases of 15 percent, compared to using the previous TASKING M16C toolset.

David Noverraz, Product Manager, Support tools, Renesas Technology Europe, is quoted in the Press Release: "Altium has already proved to be a powerful tool partner with its TASKING M16C compiler chain. However, the version 3.0 release represents a huge step forward in terms of the performance of generated code and I expect it to have a significant impact on increasing application speed and decreasing development time for M16C applications."

Applied Wave Research, Inc. announced Finisar Corp. will purchase AWR's Analog Office 2004 design suite. Finisar's optics division says it will use the software suite for the design of its high-speed optical transceivers.

Atrenta Inc. has introduced PeriScope, which the company describes as an "automated functional analysis solution that significantly reduces time and effort spent in the verification process for complex SoCs." The tool verifies and predicts back-end design problems during the front-end RTL development cycle, and aims to help engineers first determine if their RTL descriptions are functionally correct and then fix any problem areas without lengthy and repetitive simulation and synthesis runs. Atrenta says the PeriScope product complements the company’s existing SpyGlass predictive structural analysis product.

Barcelona Design, Inc. announced two new equation-based modeling and optimization products. Barcelona says its new products will allow analog designers to design their circuits to achieve both performance and yield targets within their required schedules. Per the Press Release: "With this launch Barcelona increases its focus and charges ahead to be the leading EDA vendor providing next generation analog tools and libraries that meet leading-edge requirements."

Barcelona’s new tools are Studio Circuit Modeler and Sculptor Circuit Synthesizer.
Studio, which allow users to capture the design intent of any circuit ­ at the system, block and device levels ­ into synthesizable equations and constraints. Studio includes a variety of modeling techniques that allow analog designers to trade off development effort, operational ranges, and accuracy as they develop their circuit models. The company says designers can use Sculptor to synthesize these models into optimally sized circuits that meet performance and manufacturability specifications. Barcelona’s synthesis technology allows for the simultaneous optimization of performance goals, process variation, voltage, and temperature constraints with over 100,000 parameters.

Per the Press Release: "The speed and accuracy of Sculptor delivers performance and yield targets one to two orders of magnitude faster than traditional simulation-based methods - Studio and Sculptor work with Barcelona’s synthesizable model libraries, which cover a broad range of applications from building blocks such as op-amps to clocking and data converter systems. Barcelona’s analog synthesis solution is integrated with Cadence-based design flows for schematic entry, importation of parasitic data, and SPICE simulators for model validation. Additional design flows will be supported in future releases."

Concept Engineering announced the release of its SpiceVision PRO 2.4 interactive visualization tool, which the company says supports 64-bit chips and CPUs from AMD, Intel, IBM, and Sun.

Cadence Design Systems, Inc. and CoWare Inc. announced the availability of an integrated flow from ESL design through verification for complex SoC designs. The companies say their ESL design-for-verification solution "marks a major milestone on the strategic alliance roadmap between the companies [and] enables customers to capture system-level design knowledge and apply it later in the design process to reduce verification time by up to 50 percent." The companies also say the flow is based on an integration between the releases of CoWare's SystemC-based ConvergenSC SoC design tools and ConvergenSC Model Library and the Cadence Incisive functional verification platform.

Meanwhile, Cadence Design Systems and Virage Logic Corp. announced support for both Area, Speed and Power (ASAP) Logic structured-ASIC metal programmable and standard cell libraries within the Cadence Encounter digital IC design platform. The companies say this support "leverages the production-proven capabilities of SoC Encounter's IC implementation in the structured array, as well as standard cell markets. Further, it enables mutual customers to make trade-offs between density, cost and performance according to their requirements. This capability is deployed with SoC Encounter 3.3, in production now."

Lavi Lev, Cadence Executive Vice President and General Manager, is quoted in the Press Release: "Cadence support of Virage Logic's structured-ASIC libraries provides a real advantage to customers. It expands our industry-leading support in this critical emerging marketplace from traditional ASIC vendors to COT customers, who now can enjoy the benefits of the structured-ASIC approach within the integrated RTL-to-GDSII design environment of SoC-Encounter." Lev also sits on the Board of Directors of eASIC Corp.

eASIC Corp. announced the adoption of two products from Golden Gate’s GoPower suite. The IC-Plan and PowerPlacer tools will be used for eASIC’s Structured eASIC array. The companies say the partners will incorporate Golden Gate’s clock-aware physical design into eASIC’s tools set for Structured ASIC, responding to the market requirements of less power consumption, reduced wire length and guaranteed routability. As part of the agreement, two of Golden Gate’s products, the advanced power managing floorplanner (IC Plan) and the advanced power reducing placer (PowerPlacer), will be integrated into eAISC’s tools kit for designer’s use.

Zvi Or-Bach, eASIC President and CEO, in quoted in the Press Release: "After evaluating the tools, eASIC was very impressed with the Golden Gate’s PowerPlacer quick run-time, reduced wire length and superior routability. We found it is a perfect match for our customer’s needs. Using Golden Gate’s floorplanner helps us in providing design-friendly Structured ASIC, which is NRE-free, removing design-entry barrier and allowing low-cost and high performance ASIC. This integration of powerful EDA tools and innovative technology allows us to create a comprehensive Structured eASIC offering from RTL to complete physical design."

Incentia Design Systems, Inc. announced that Faraday Technology Corp. has integrated Incentia's software into its ASIC synthesis and timing flow. Jim Wang, Director of the Design Development Division at Faraday, "Because our benchmark showed Incentia's logic synthesis and timing analysis software successfully reduced chip area and greatly shortened run time, we were confident about adopting Incentia's tools into our ASIC flow. Our real design examples showed that Incentia's software achieved high performance and facilitated our customers' projects."

Incentia Design Systems also announced that Goyatek Technology Inc. has selected Incentia's DesignCraft for the logic synthesis of its USB 2.0 device controller IP design. Nai Yin Sung, R&D Division Director of Goyatek, is quoted in the Press Release: "With Incentia's DesignCraft, we completed our USB 2.0 Device Controller design on our first try. We are very pleased that DesignCraft reduced our runtime significantly and achieved a smaller area usage than our previous USB designs, while meeting our timing constraints."

Finally from Incentia - The company announced the availability of the 2004.05 release of its timing analysis, logic and physical synthesis software products: TimeCraft, DesignCraft and DesignCraft Pro. The company says the new release improves runtime, capacity, and quality, when compared to its 2003.09 release. Arthur Wei, Vice President of Operation at Incentia, is quoted in the Press Release: "We have made significant improvements to our synthesis software, and are very pleased to have our customers report runtime reductions from 12 hours to 2 hours on a 3 GHz Linux platform with our new release."

Magma Design Automation Inc. announced that Toshiba Corp. and Toshiba Microelectronics Corp. have implemented an SoC in Toshiba's TC300 90-nanometer technology using Magma's Blast Fusion APX, Blast Plan and Blast Noise tools.

Takashi Yoshimori, Technology Executive, SoC Design of Toshiba Corp. Semiconductor Co., is quoted in the Press Release: "The unified datamodel of Blast Fusion APX and its 64-bit Opteron support provided very high capacity and predictable timing closure, greatly enhancing the productivity and performance of our 90-nanometer designs. This enabled hierarchical design with fewer blocks, significantly simplified the design process and reduced design cycle as expected."

Seiichi Hirai, Executive Vice President and General Manager of Toshiba Microelectronics Corp.'s ASIC Division, is also quoted: "We are committed to meeting our customers' expectations for performance and turnaround time. Our design teams were able to quickly learn and adopt the Magma flow in order to meet the schedule requirements of our customers."

Mentor Graphics Corp. announced its Catapult C Synthesis product, which the company says uses "pure" untimed C++ to create RTL descriptions up to 20 times faster than traditional manual methods. Mentor says the new tool targets designers developing ASICs or FPGAs for next-generation, compute-intensive applications such as wireless communication, satellite communication, and video/image processing. Catapult C Synthesis tool combines with the Mentor Graphics ModelSim simulator to create the central foundation for a C-based design flow. Simon Bloch, General Manager, Design Creation and Synthesis Division, Mentor Graphics, is quoted in the Press Release: "Our Catapult C Synthesis tool will no doubt have a major impact on future C-based ASIC and FPGA design."

Mentor Graphics Corp. also announced that Siemens Information and Communications Networks (ICN) has reduced C source to RTL implementation time by 50 percent on an important project using Mentor’s Catapult C Synthesis tool. Siemens ICN says it has now adopted the tool, which will be used by the Munich-based design team to develop an ASIC for a VoIP application. Rudolf Krumenacker, Vice President, SoC Design at Siemens ICN, is quoted in the Press Release: "We were impressed by the results. The fact that we could synthesize our untimed, system-level C/C++ source code with minimal modification played an important role in the success of this project. It provided a precise path from our system-level models all the way to RTL, which allowed us to meet our required design goals in significantly less time."

Novas Software, Inc. announced that Seiko Epson Corp. is integrating Novas software as the company’s standard platform for IC debug. The companies say the volume purchase agreement doubles the number of Novas licenses already in use within Epson’s Semiconductor Operation Division. Shigeo Tsuruoka, Manager of IC Design Department, Semiconductor Operation Division at Seiko Epson Corp., is quoted in the Press Release: "Novas Debussy Debug System has been the standard logic design debug tool at Epson for several years. We’re now making it more widely available within our entire engineering organization to further enhance the efficiency of our semiconductor product development teams."

OEA International, Inc. announced an update to its popular SPIRAL, a specialized 3D inductor design toolset for synthesizing embedded spiral inductors in analog and RF chips. The new version of SPIRAL adds support for balanced inductors, differential inductors, and transformers. SPIRAL also adds features for 65-nanometer and 90-nanometer support with dummy metal fill and slotted wide metal support. The update also includes a new linear Spice solver, 'panther,’ for improved performance. Additionally, a new DRC checker is now implemented assuring the GDSII layout conforms to the foundry DRC rules, and a new Monte-Carlo analysis allows emulation of foundry variations to test all corners of the inductor performance

OEA International also announced an update to its P-GRID 3.0 tool for the analysis of IC core power distribution networks for excessive IR drop and electromigration violations. Per the Press Release: "In today's large SOC devices and advanced ASICs there are major concerns about the low voltage margins caused by small voltage differentials, the effects of switched power for large sections of the chip, and real worries about excessive power leakage in nanometer technologies. P-GRID helps eliminate those concerns by giving an accurate analysis of the current distribution through the core of the chip."

The new P-GRID features include 10x+ speed improvement, more compact and efficient data model for handling via arrays accurately while saving time, color-coded report outputs showing block currents, outputs detailing average current in by area in the contact layer, and details on voltage drop in the via layers.

Sierra Design Automation, Inc. announced the availability of Pinnacle, which the company describes as "the industry’s first IC implementation solution developed specifically to meet the high capacity, short turn around time and quality of results demands of large designs targeted at manufacturing processes of 90 nanometer and below." The company says this physical synthesis technology and product architecture will speed up design closure by 5x to 10x over last-generation tools, and that Pinnacle’s open architecture and compact database can handle 10 million gates flat, chips or blocks, on a 32-bit machine. Pinnacle can scales to 50+ million gate hierarchical designs on a 64-bit machine.

Noboru Yokota, Director in the Advanced Technology Development Group of Fujitsu Microelectronics America, Inc., is quoted: "Sierra’s Pinnacle physical design system has demonstrated the capacity, speed and implementation quality needed for our ASIC evaluation designs. Fujitsu is incorporating Pinnacle’s physical design system into our IC implementation flow. Additionally, we are analyzing Pinnacle's flexible product architecture for use with AccelArray, Fujitsu’s new ASIC design platform, and expect it will enable us to offer a very high-capacity, fast turn-around-time design flow for our AccelArray customers."

Silicon Canvas, Inc. announced it has acquired Cohesion's AMS product. Cohesion is a privately held company and AMS is a schematic entry tool widely used in the analog/mixed-signal custom IC and FPGA design.

Per the Press Release: "For some months prior to the acquisition, the company has been working with Cohesion on behalf of a major mutual customer, to jointly integrate AMS with the Silicon Canvas Laker suite of IC design tools. Combining the two companies is simply the natural progression of a very synergistic working relationship. Existing ECS and Laker customers will immediately benefit from the integration of AMS with Laker. Customers can expect Silicon Canvas to widen the lead in the schematic driven layout methodology by offering this advanced technology for hierarchical manipulation, ECO, and layout reuse.

Summit Design, Inc. has expanded its Visual ESC package to support the MIPS64 5K core family and verification IP from Denali Software. The expanded Visual ESC package has an integrated ISS that’s tightly linked with vendor-specific software environment tools for platform-based design. Most of the major components are integrated into a SystemC environment with built-in verification capabilities. Visual ESC allows interface of the ISS at a signal-level, or at a transaction-level for higher performance, and provides synchronized hardware and software debugging and visibility. The company says this enhanced packed will "reduce the adoption cycle for those who want to start with SystemC."

Additionally, Summit Design is introducing an addition to its Visual Elite ESL product, which will include advanced SystemC modeling and analysis with complete native text support.

Per the Press Release: "other tools have been oriented specifically to either hardware or C/C++. Summit Design is delivering the first tool that can bridge this gap and take full advantage of the language abstraction and power, freeing engineers to successfully use it in the context of their complex system chips. Visual Elite 4.0 is the very first product offering built-in SystemC-native constructs that accelerate modeling and verification, making it intuitive for hardware designers as well as to C/C++ coders. One of the primary barriers in the adoption of SystemC is that it is software-oriented for hardware designers, while lacking some of the hardware notations. Today, this is being addressed through the newest Visual Elite platform that allows users to employ the powerful language constructs through an intuitive front-end and powerful verification and analysis tools. By supporting a complete native SystemC file structure, there is no need for importing or special instrumentation that are limiting the scope of the language that can be supported. Visual Elite users are free to utilize any existing designs with the Visual tool-set."

Synopsys, Inc. announced that Royal Philips Electronics signed a multi-year volume purchase agreement with the company, extending the use of Synopsys’ Galaxy design platform on Philips projects. Philips says it will use the products for designs targeting its CMOS090 (90-nanometer) and CMOS065 (65-nanometer) semiconductor processes.

Lambert van den Hoven, Vice President and General Manager of Philips’ Design Technology Group, is quoted: "With the recent electronics recession behind us, Philips' semiconductor division has turned its attention to growth and the Synopsys agreement is structured to grow with our business. We have been successful with Synopsys' tools for many years and we look forward to continue this successful partnership."

Additionally, Synopsys announced "significant performance enhancements" and high-frequency design support for the company’s HSPICE circuit simulation product. The company says the new release yields upwards of 20 x runtime improvement for transient analysis and a new harmonic balance engine for simulation of high-frequency designs. Per the company, designers will be able to simulate designs faster than before and perform analysis of high-frequency and RF circuits, while maintaining "the golden level of accuracy expected of HSPICE."

Per the Press Release: "An enhanced time-step control algorithm, combined with a simplified simulation control interface, is the key enabler of HSPICE's improved performance. With the new features, all simulation tolerances are scaled simultaneously using a single control option, eliminating the need for users to adjust multiple option settings. HSPICE automatically maximizes each time- step size to meet the desired accuracy level. With the addition of the harmonic balance engine, HSPICE now supports high-capacity non-linear simulation for high frequency designs. HSPICE performs periodic steady-state (PSS) analysis, periodic noise and phase-noise analysis, and periodic AC analysis."

A quote from Neal Carney, Vice President of Marketing at Artisan Components, Inc., is included: "HSPICE has long been a key simulator for characterizing our widely-used semiconductor IP. We rely on HSPICE's foundry-certified models to accurately characterize libraries for timing, power and noise," "We are impressed with the new features of HSPICE, which deliver up to 20 times performance improvement over previous versions with the same high level of accuracy. We have already deployed it into our production flow."

VaST Systems Technology announced the availability of its CoMET 5 System Engineering Environment (SEE) ESL design and embedded software development tool suite, which the company says supports SystemC and is for architects, hardware designers, and software engineers to use in quantitative architectural design and evaluation, hardware refinement and verification, and software development.

Per the Press Release: "Using CoMET 5, engineers can work together early in the system design process to evaluate architectural choices and their implications for both hardware and software development - CoMET 5 includes two new tools, Virtual Prototype Constructor and Peripheral Builder, which enable semiconductor and systems engineers to create and modify their virtual prototypes without compromising the high performance and accuracy that VaST delivers. CoMET 5 also now includes the Communication Infrastructure Fabric (CIF), a foundation technology that extends the performance and accuracy of virtual prototypes from processors out to buses and peripheral devices."

Verific Design Automation announced that NEC’s System Devices Research Laboratories has purchased a license of its HDL Component Software. Masao Fukuma, Vice President and General Manager of NEC System Devices Research Laboratories. is quoted: "NEC spends significant resources in advancing state-of-the-art EDA research to maintain its leadership position in SOC design. Using Verific’s software fits right into our best-in-class strategy."

X-FAB Semiconductor Foundries AG says the company now offers customers a 650-Volt power technology (XD10H) based on a trench-isolated SOI process. XD10H is a modular process suitable for any type of power net application up to 230 volts, and combines DMOS, bipolar and 1-micron CMOS processing steps with dielectric insulation. Per the Press Release: "This approach enables the integration of a wide variety of MOS and bipolar devices with different voltage levels. In addition to predefined 650- and 350-Volt n-channel DMOS transistors with different on-resistances, CMOS transistors are available with voltage levels from 5-20V. Complex CMOS logic also can be integrated, based on 1-micron design rules."