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* KLA-Tencor and Aprio Technologies announced "their intent" to collaborate on the development of an integrated advanced mask design inspection and repair tool. Per the Press Release: "This collaboration signals KLA-Tencor's latest step forward in providing critical yield management solutions for the growing DFM market. Both companies assert that this partnership will encourage better collaboration between their customers' design and manufacturing teams. As part of this collaboration, Aprio will provide new functionality to products under development at KLA-Tencor that address automated mask layout inspection … Initial availability of an integrated product from KLA-Tencor and Aprio is expected in 2006. "

Harold Lehon, Vice President of DFM solutions at KLA-Tencor, is quoted: "Our customers that are moving to the 65-nanometer process node can no longer afford to wait to find design issues in the manufacturing process. KLA-Tencor and Aprio share similar views on the most optimal way to link the design and manufacturing domains, and we're pleased to be working with an EDA company that is making real inroads into both sides of the tape-out wall."

From a philosophical point of view: "While many DFM companies first create tools for designers, KLA-Tencor and Aprio both see the greater need to address DFM challenges on the manufacturing side first, since that is the source for most DFM problems. Both also agree on the need to shift from a rules-based handoff procedure to a models-based DFM methodology in order to address the yield impact of shrinking process windows and growing process variability on the design. A models-based approach allows companies to reduce their sampling and target their process control methods to design areas that matter most, reducing the amount of design re-work needed as well as improving yields."

* Synopsys, Inc. announced that it has jointly developed reference design flow 2.0 with Semiconductor Manufacturing International Corp. The companies say that SMIC and Synopsys Professional Services "worked closely on the complete RTL-to-GDSII flow, which is based on Synopsys Galaxy Design Platform and SMIC's advanced 0.13-micron process."

New features include floor-planning capabilities from Synopsys' JupiterXT, signal integrity and IC reliability (IR/EM) analysis capabilities using Synopsys PrimeTime SI, Astro-Xtalk and Astro-Rail tools, and voltage-drop (IR-drop) analysis.

Paul Ouyang, Vice President of Design Services at SMIC, is quoted: "SMIC has been providing advanced 0.13-micron CMOS processes to customers worldwide for mass manufacturing since the first half of 2004. Version 2.0 reference flow provides customers a complete and proven design solution in advanced floor planning, SI closure, and IR/EM analysis, which are important to 0.13-micron designs. The development of version 2.0 reference flow builds on our success and collaboration in developing the first version. We look forward to a continuing relationship with Synopsys as we move towards more advanced processes."

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In other news ...

* AccelChip Inc. says it is "the first company to provide a family of fixed-point linear algebra IP cores for Xilinx FPGA devices … The AccelChip cores, the first of their kind, directly implement linear algebra-based matrix operations used in applications such as sensor array processing, beamforming, global positioning, radar/sonar, Kalman filtering, and wireless communication applications. Targeted at hardware designers and system engineers who implement these applications in silicon, AccelCore DSP IP delivers synthesizable, VHDL/Verilog linear algebra cores that are highly optimized in terms of speed, power, and size."

David Squires, Director of DSP Marketing in the DSP Division at Xilinx, is quoted: "Our DSP customers use a combination of both HDL and Xilinx System Generator for DSP Design. The addition of AccelCore into the Xilinx Alliance Program has the potential to save months of development time, regardless of design entry methodology with proven linear algebra-based matrix cores for advanced wireless and signal processing applications."

* Accelerated Technology, a Mentor Graphics division, announced that its Nucleus EDGE software development environment is now available for the MIPS32 and MIPS64 architectures from MIPS Technologies.

Russ Bell, Vice President of Marketing for MIPS, is quoted: "Our customers need to accelerate their time to market in order to excel in the highly competitive digital consumer space. Leveraging the industry-leading MIPS architecture and the Nucleus EDGE software environment allows designers to meet and exceed their development objectives and deliver superior products."

* Accent, ARM and Cadence Design Systems, Inc. announced that Accent has validated a low-power design flow using Cadence's Encounter digital IC design platform and ARM Artisan physical IP. The companies say the design was implemented with a multi-supply multi-voltage (MSMV) design flow utilizing three power domains.

More details: "High voltage threshold (low leakage) optimization was performed on both the MSMV implementation and a baseline implementation with a single supply voltage to further reduce leakage power, and the low-power design flow reduced dynamic power by 34 percent. Additionally, the low voltage section of the design also showed 40 percent less leakage power than the baseline flow implementation."

Claudio Fasce, Vice President of Business Area Design and Supply Chain Management Services for Accent, is pleased: "Using the Cadence Encounter platform and the ARM Metro IP supporting MSMV design, we were able to quickly validate our low-power design flow and significantly improve our overall low-power design methodology. Close collaboration with ARM and Cadence expands our design skills and enables us to deliver better performing devices and a greater competitive advantage to our customers."

* Actel Corp. announced its Fusion technology, which the company says launches "The Era of the Programmable System Chip (PSC) … The Actel Fusion technology is the first to integrate mixed-signal analog capabilities with flash memory and FPGA fabric in a monolithic PSC … In addition, when used in conjunction with Actel’s ARM7 and 8051-based soft MCU cores, the Actel Fusion technology represents the definitive PSC platform … The Actel Fusion technology presents new capabilities for system development by allowing designers to use the same silicon for a variety of applications and/or quickly adapt to rapidly changing standards."

To better understand: "The new Actel Fusion technology will enable designers to design at both very high and very low levels of abstraction. Fusion peripherals include hard analog IP and hard and/or soft digital IP. Peripherals will communicate across the FPGA fabric via a layer of soft gates ¾ the Fusion Backbone. Much more than a bus interface, the Actel Fusion Backbone integrates a micro-sequencer within the FPGA fabric and will configure the individual peripherals and support low-level processing of peripheral data. The Actel Fusion technology will also give designers unprecedented levels of flexibility by allowing them to easily reconfigure analog block settings to perform widely different functions by simply downloading data from embedded flash memory. To support this new groundbreaking technology, Actel is developing a series of major tool innovations to help maximize designer productivity. Implemented as extensions to Actel’s popular Libero Integrated Design Environment (IDE), these new tools will allow designers to easily instantiate and configure peripherals within a design, establish links between peripherals, create or import building blocks or reference designs, and perform hardware/software verification. This tools suite will also add a comprehensive hardware/software debug capability as well as a suite of utilities to simplify development of embedded soft ARM and 8051 processor-based solutions."

John East, President and CEO of Actel, says customers have an insatiable appetite for integration/flexibility technology: "The insatiable demand for increased integration and flexibility continues to fuel the industry’s race toward programmable system chip solutions. With the creation of the Actel Fusion technology, we aim to simplify the way systems are designed. Leveraging the unique expertise acquired while creating the industry’s leading flash-based FPGA devices, we have brought together the reprogrammable advantages of Actel’s advanced flash FPGAs with analog components and large flash memory blocks into a landmark single-chip solution."

* Also – Actel and HDL Works announced "the optimization of HDL Works’ EASE design entry tool for Actel’s Libero IDE design flow." The two companies also announced that HDL Works has joined Actel’s EDA Alliance Program.

Saloni Howard-Sarin, Director of Antifuse and Tools Marketing at Actel, is quoted: "We are pleased to partner with HDL Works because EASE complements the Libero IDE and offers the combination of both power and ease of use that FPGA designers value. When our customers use EASE, they can save time and money by eliminating costly errors in HDL code. They can then use the RTL generated by EASE in the Libero environment to complete their design."

Meanwhile, Thomas Rode, Design Manager for Siemens’ Automotive and Drives Division in Nürnberg, is pleased: "We’ve used EASE for implementation of many designs in Actel devices very successfully. The major benefit we experience is the enormous reduction in time necessary for editing, debugging and modifying the HDL code. The close integration of the design tools reduces design time and eases the interaction between the different stages of the design flow, which greatly enhances productivity and optimizes exploration of multiple design implementations."

* Aldec, Inc. announced the release of its Riviera-SNA (Simulator for Networking Applications). The company says, "The new product is aimed at 64-bit Linux design verification server farms and is priced starting at less than $200 per seat. Riviera-SNA addresses changing customer needs as ESL and ASIC manufacturers require an increased number of high-performance simulators online … Aldec is currently installing Riviera-SNA on a 10,000-node server farm for a renowned ASIC manufacturer that is supplying electronic devices to the automotive and wireless industries. This installation is the largest design verification server farm in the electronics industry. The installation should be completed and tested within the next month, a separate announcement will follow."

Stanley Hyduke, President of Aldec, is quoted in the Press Release: "Because tools such as Synopsys Vera and Cadence Specman Elite are being increasingly used for automatic testbench generation, engineers now need a way to verify hundreds, or even thousands, of testbenches in a fast and economical way."

Eric Seabrook, Director of Marketing for Aldec, is also quoted: "Riviera-SNA is a simulator product for networking applications that makes economical sense for the new era of automatic testbench generation. Riviera-SNA will be well-suited for simulation farms at medical, military, communications and consumer goods manufacturers."

Meanwhile, Aldec offers an update on the EDA Paradigm Shift ... "Despite that over 70% of the design effort goes into design verification alone, there are still many ASIC re-spins and product cancellations due to poor design quality. To cope with these issues, the industry has seen a surge in automatic testbench generation tools. This surge has caused an explosion in the number of testbenches and, in turn, simulation time needed for verification. Because of this, current simulation farms with access to 100 - 500 simulators can no longer do a satisfactory job. The ESL, ASIC and large consumer goods manufacturers now need farms with 1,000 to 10,000 or more high-performance simulators online."

* Applied Wave Research, Inc. (AWR) announced that it will offer open access of its proprietary Xmodels technology to third-party electromagnetic (EM) analysis software vendors who wish to integrate with AWR’s Microwave Office circuit design software suite.

Sonnet Software, Inc. says it's the first EM tool vendor to take advantage of AWR’s offer.

James Rautio, President of Sonnet, is quoted: "AWR and Sonnet participated in a panel discussion on the importance of EDA tool integration at the 2005 International Microwave Symposium last month. Both companies were inspired to explore mutual opportunities to integrate the best features of AWR’s Microwave Office circuit design software and Sonnet’s EM software and to demonstrate how easily two companies can work together in order to provide our customers with timely and superior solutions. In this spirit of cooperation, we were able to integrate AWR’s Xmodels with the industry's most accurate and reliable high-frequency planar EM software in a matter of days; truly a testament to the openness and integration of the Sonnet and AWR environments."

James Spoto, AWR president and CEO, is also quoted: "While AWR continues to develop its own industry-leading EM solutions, we recognize that no single EM solver delivers the best solution for all applications. The decision to provide open access of our proprietary Xmodels to third-party vendors was made as part of AWR’s commitment to the open design platform concept and our leadership position in providing designers with the flexibility to integrate tools of choice for a superior design methodology."

* ARM says it has recently demonstrated the first test chip of its ARM11 MPCore synthesizable processor which the company says has "demonstrated performance equivalent to a 1.2GHz ARM11 family processor, with power consumption of approximately 600mW while delivering 1440 DMIPS of aggregate performance … The ARM11 MPCore processor test chip is 'right-first-time' and is the result of an ongoing collaboration between ARM and NEC to co-develop a next-generation multiprocessor core based on Symmetric Multi-Processing (SMP)."

The announcement also says: "The test chip, which comprises four processors running with cache coherence, was constructed using a generic 130-nanometer technology with no process optimizations for performance or power, and achieved this high-performance and scalability with existing applications developed for non-multiprocessing system technology. It features a full Linux SMP OS port and applications, and shows the automatic balancing of application loads among processors with overall reduction of consumed energy.

* Cadence Design Systems, Inc. announced the latest release of its OrCAD PCB design software product line. The company says the release "introduces new technology and feature enhancements aimed at solving today's design challenges and increasing productivity." Surely a good thing.

Per the Press Release: "With these enhancements, OrCAD enables faster time to market with new automation and technology. This includes OrCAD Signal Explorer for signal integrity analysis and validation throughout the design process. PCB topology exploration drives correct-by-design processes and reduces PCB respins for less time spent in lab debug."

Ronald Weber, PCB designer at DesConTec in Munich, Germany, is quoted: "OrCAD PCB Designer is a great tool for a service bureau like us. With PCB Designer, we can use OrCAD Capture, the popular schematic entry tool used by many of our customers. We also do PCB layout based on the solid Allegro database format. This allows us to reuse designs, if necessary, and addresses high-speed issues within the Allegro Environment."

* Cadence Design Systems also announced its Engineering Services team helped Sequans Communications "meet a challenging time-to-market goal for a high-performance SoC. The wireless broadband chip was successfully taped out within a year of the company's initial funding." Also a good thing.

The Press Release says: "The chip was designed to comply with the IEEE 802.16-2004 standard and WiMAX system profiles for broadband wireless access. … As part of the engagement, Cadence also supplied analog IP designed using the Virtuoso custom design platform.

Georges Karam, CEO at Sequans, is unequivocal: "Cadence was instrumental in this tapeout. The wireless design expertise of Cadence Engineering Services, coupled with world-class technology and methodologies, gave us the edge we needed to minimize our design time and deliver a successful tapeout."

* Cadence has been busy, because they also announced that the latest release of the Cadence Allegro system interconnect design platform.

You'll want to know that: "The latest Allegro technology shortens design cycle time by enabling team-based PCB system design throughout the design flow. The entire breadth of the Allegro product line has been enhanced with greater productivity and ease-of-use capabilities. It further strengthens the design chain by helping IC companies distribute Spectre transistor-level models so that their customers can design-in complex ICs faster. The release includes new technology for multi-style design creation, real-time design for assembly (DFA) driven placement and an improved constraint-driven design flow."

Charlie Davies, ECAE Application Engineer in Harris' Government Communication Systems Division, says: "We are especially pleased with Allegro's new real-time DFA driven placement capability. This feature guides component placement, allowing us to create manufacturable designs appreciably faster. This capability further enhances Cadence's Constraint Driven PCB Design Flow."

* Meanwhile, Cadence has been busy in synthesis as well …

Cadence announced: "During the last 12 months, over 80 new customers have adopted Encounter RTL Compiler."

Yasuhiro Tani, Senior General Manager at the SOC Design Center, Platform Technology Development Headquarters at Canon, Japan, says: "We have adopted Encounter RTL Compiler for future tapeouts because of its proven ability to increase chip performance, reduce power, reduce turnaround time and increase productivity. We will now make support for Encounter RTL Compiler a requirement for our ASIC vendors."

Satoshi Andou, General Manager, Design Methodology Development Division, Electronic Devices Business Group at Fujitsu, says: "Fujitsu will support Encounter RTL Compiler for our internal and external ASIC customers."

Kazu Yamada, Associate Vice President, Technology Foundation Development Operation Unit from NEC Electronics, says: "As a result of increasing customer usage and its ability to produce high-quality netlists for implementation, NEC Electronics has adopted Encounter RTL Compiler as part of our ASIC design flow and will support Encounter RTL Compiler for synthesis," said "We want to ensure that our customers are enabled to take the most out of our ASIC offering to achieve their design goals in the shortest time possible."

Shin-ichi Imai, Senior Manager, System LSI Design Dept. System LSI Division I at Toshiba, says: "Our evaluation of Cadence Encounter RTL Compiler for synthesis of ASIC designs has demonstrated to us its value for producing optimized netlists for large designs and meet design goals for performance and die size. As a result, we will support RTL Compiler for production tapeouts."

Cadence also announced that Global UniChip Corp. of Taiwan has adopted Encounter RTL Compiler. The companies say, "Using Encounter RTL Compiler to synthesize the ARM926EJ-S from RTL resulted in an eight-percent reduction in die size after place and route."

Jim Lai, COO and President at Global UniChip, is quoted: "We have successfully completed more than 10 tapeouts at 130 nanometers using the Encounter platform, and are currently using it for 90-nanometer tapeouts. Based on our successes with Encounter RTL Compiler on customer designs, we are also using it to harden an ARM9 core, and we were pleased that the netlist the tool produced resulted in a smaller die area."

Cadence also announced that Sunplus Technology Company, Ltd. "achieved an important production tapeout of a reduced die-size consumer-electronics chip using Cadence technology. Using Cadence Encounter RTL Compiler global synthesis, Sunplus completed the DVD chip in just one month. … Encounter RTL Compiler created a small enough design that engineers could meet their die size requirement with margin to spare. This extra margin helped speed physical implementation and reduce the project schedule to one month. As a result, Sunplus was able to cut its project costs for this high-volume DVD chip and get it to market more quickly."

Chih-Hao Kung, Vice President of R&D at Sunplus, is quoted: "Sunplus participates in the highly competitive consumer electronics market. We are always looking for a competitive edge. We found that Encounter RTL Compiler gave us both cost and time-to-market advantages that measurably impact our bottom line."

Then, Cadence and Fujitsu Microelectronics America, Inc. announced that FMA will ship initial production volumes of "a new, highly complex, structured ASIC using Cadence Encounter digital IC implementation in August … The design incorporates 3.5 million logic gates, 119 instances of 2RW SRAM (40bx512w), 33 instances of register file (40bx32w) and 12-channel, 3.125G SERDES for high-end servers developed for consumer applications."

Noboru Yokota, Senior Director of Engineering at FMA, is quoted: "We chose the Encounter platform as the netlist handoff and for completion of physical design such as the placement and routing, because it provided excellent flexibility in implementing standard ASIC and structured ASIC designs."

* Catalyst Systems Corp. recently announced availability of the latest version of its Openmake development tool for automated build management.

Per the Press Release: "New features of Openmake 6.4 include a Build and Deploy Manager, Build Activity Schedule and enhanced Audit Reporting. Through audit information consistently recorded during build processes, Openmake can create advanced audit reports and impact analysis that helps isolate complex problems and improve quality. These reports also make it easier to isolate components during problem diagnosis by determining the pedigree of code executing in a complex system. Compatible with a variety of development language and tool environments including Eclipse-based solutions like IBM Rational Application Developer for WebSphere Software, Borland and Microsoft .NET. Openmake integrates fully with version control systems from Rational, Serena and more.

Jim Duggan, Research Vice President for Applications Development at Gartner Research, is quoted: "Next to documentation, build management is likely to be the least satisfying task a developer must address every day. A lot of software investment ends up in the time it takes to constantly tweak the make files needed to keep a system maintainable. Developers are looking for innovative solutions that will reduce software coding by a factor of five."

* Catalytic Inc. says it is now shipping Catalytic RMS (Rapid MATLAB Simulator), software for streamlining the algorithm design of signal processing systems eventually implemented in register transfer level (RTL) code.

Per the Press Release: "Catalytic RMS works seamlessly with MATLAB (from The MathWorks) to provide fast floating-point simulation for standard MATLAB code, accurate fixed-point modeling capabilities, and fast fixed-point simulation. The result is a streamlined algorithm design process that accelerates the simulation of standard MATLAB and assists with the conversion of floating-point MATLAB to optimized fixed-point MATLAB, which accurately models the behavior of the final RTL design. Catalytic RMS speeds floating- and fixed-point MATLAB simulations using Catalytic’s proprietary compiler technology, which generates a compiled library from MATLAB code. This library executes much faster than the original interpreted MATLAB code."

Randy Allen, Catalytic’s Founder and CEO, is quoted: "With the introduction of Catalytic RMS, Catalytic is greatly assisting signal processing design groups who implement their algorithms in RTL. As an example, engineers creating wireless ASICs describe their entire chip in MATLAB because it is an excellent language for describing the highly mathematical algorithms that comprise the core intellectual property of wireless systems. But the algorithm engineers must quickly move out of MATLAB because of the slow simulation speed and the lack of fixed-point modeling and analysis capability. Catalytic RMS can simulate core wireless algorithms 200 times faster than existing methods. MATLAB users no longer have to spend time hand translating MATLAB to C to achieve acceptable simulation speeds."

* Denali and NextIO, Inc. have announced an agreement that provides NextIO with Denali's PureSpec verification IP for functional verification of the PCI Express interface of its enterprise server chips.

Chris Pettey, CTO of NextIO, is confident: "Denali's PureSpec is the most trusted solution for verifying PCI Express designs. We have a veteran design team with extensive experience in the server market and they asked for Denali's PureSpec. In addition to its superior technology for exposing design issues, the widespread use of PureSpec gives us the added confidence in verifying interoperability with other PCI Express designs."

* Macraigor Systems LLC announced additional support for several new processors in the Applied Micro Circuits Corp. (AMCC) PowerPC 440 family. The companies says that debugging and control of these chips will be supported by all Macraigor debug solutions when used with the OCDemon family of products … Macraigor has added support for the AMCC PowerPC 440GP, 440EP and 440GX processors and has also updated their free, pre-built Gnu tools suite to include example configurations for the AMCC Bamboo, Yosemite, Ebony and Ocotea evaluation boards.

If nothing else, you gotta love those names!

Charlie Ashton, Director of PowerPC Software for AMCC, is quoted: "Developers need a full-featured alternative to more expensive JTAG emulators. Macraigor’s OCDemon family of products offers an extensive feature set and robust debug capabilities geared for complex designs."

* Magma Design Automation, Inc. announced that Renesas Technology Corp. has "achieved first-pass silicon success on a car audio microcontroller developed using Magma software. The multimillion-gate, 0.13-micron chip was designed by Renesas' microcontroller design group."

Katsumi Iwata, Senior Manager of the MCU Product Marketing Department in the MCU Business Unit at Renesas Technology, is impressed: "To meet ever-increasing market demands for better quality of results (QoR) and faster turnaround time (TAT), we needed to move from a point-tool-based flow to an advanced, integrated design environment. Magma's integrated design solution delivered remarkable predictability and also provided fully automated low-power design capabilities for EMI-specific issues. This was critical to the success of this design. Magma's software provided better QoR than we expected while reducing design TAT. With the tremendous support of the Magma team we were able to develop a custom power-routing utility based on Magma technology. This utility enabled us to dramatically reduce the TAT for building the power grid. We are very impressed with the results. The first silicon worked well and we were able to deliver it to our customer on time. That's why we adopted Magma and why we plan to use their design flow and our utility for future versions of this device, as well as for other highly reliable products in the future."

* MatrixOne, Inc. announced that Imagination Technologies has adopted MatrixOne's Synchronicity Publisher Suite with IP Gear to manage its portfolio of innovative silicon and IP.

John Metcalfe, Vice President of Operations at Imagination, is quoted: "Our customers are very demanding. We needed a solution that could better manage, catalogue and distribute our wide ranging IP. MatrixOne provides us with several key business benefits, but most importantly, it will significantly streamline and improve customer service."

* Mentor Graphics announced PCB tool support that the company says will enable OEM customers "to achieve Restriction of Hazardous Substances (RoHS) compliance. Mentor's solution helps OEMs ensure compliance early and throughout the design process, eliminating costly iterations. Customers are able to leverage the component library data field flexibility to implement filtered search and Bills of Material (BOM) capabilities, enabling OEMs to design for RoHS compliance and avoid expensive redesign time. Using component data captured in Mentor's DMS (Data Management System), LMS (Library Management System) and DxDataBook systems, designers can now search for approved, hazardous material-free parts for their PCB designs, as well as produce work-in-process BOMs containing summations of hazardous material content in their products."

Read about RoHS Regulations "The RoHS regulations that go into effect July 2006 require electronics companies to provide proof that they have complied with regulations limiting the amount of six hazardous materials, including lead, in their products. Today, these materials can be found in the components, fabrication of the PCB, and in the assembly parts. Component suppliers are being asked to document the material content of their parts in data supplied to the OEMs. By adding this material content to the component library data and flagging parts that are RoHS compliant, OEMs can ensure that their designers have the information they need to make the proper choices."

"To accommodate lead-free soldering, the external layers of the PCB are now made from different materials than the internal layers. These new materials must be correctly modeled for their electrical characteristics when designers perform delay and signal integrity analysis. Mentor's automated layer stack-up analyzers, driven by the manufacturer's materials data, allow designers to quickly and accurately model the new heterogeneous layer stack-ups and accurately perform high-speed signal integrity and EMI analysis. In addition, special component placement rules and new solder mask configurations can be followed by Mentor's Board Station, Expedition and PADS PCB layout and manufacturing checking products."

* Mentor Graphics also announced the successful certification of its UTMI + low pin interface (ULPI) support for the Universal Serial Bus (USB) On-The-Go (OTG) standard from the USB Implementers Forum.

Per the Press Release: "ULPI is a new interface standard for hi-speed USB IP systems designed to reduce the pin count of discrete hi-speed USB physical interfaces (PHYs). Most UTMI + PHY require between 40-60 pins from the USB IP controller, but this solution reduces the number of pins down to 12 when using an off-chip or discrete PHY, resulting in a lower cost solution."

"Mentor's USB OTG controller combined with a reliable third-party PHY, such as SMSC's USB3300, currently the only PHY certified by the USB-IF, enables quick, proven integration and design reuse benefits, for a complete USB OTG solution. The ULPI 'wrapper' is a no-cost option provided with all of the Mentor hi-speed USB cores, and has been rigorously tested on real hardware for risk-free implementation. "

Steve Nelson, Vice President of Marketing for Connectivity Solutions at SMSC, is quoted: "Building on the Hi-Speed On-The-Go certification achieved with Mentor in April, the certification of our USB3300 ULPI PHY with Mentor's USB OTG controller further demonstrates the robust interoperability of the combined ULPI solution. The ULPI standard is gaining momentum across the board with its low pin count interface and low-risk implementation of hi-speed USB. Many of our mutual customers are discovering the positive impact that our ULPI solution can make in bringing consumer electronics products rapidly into production."

* PolarFab announced it has incorporated high-power lateral DMOS devices into its Polar35 process family. The company says its Polar35 LV process features modular 5V analog CMOS as well as 7V and 12V power device suites, and uses a modular device and mask approach that gives designers the ability to optimize their design for performance versus cost. In addition, "designers can reuse design IP across many product families."

Also per the Press Release: "The process incorporates stacked via placement, enabling increased packing density … The 0.35-micron design rules of the new process enable dense digital blocks for higher levels of integration for smaller 5V, 7V, and 12V switches. Polar35 LV also incorporates silicon proven, space-efficient ESD protection solutions for efficient design qualification, reducing time to production. Polar35 LV comes with a fully documented design tool kit, including scalable models and p-cells, a Cadence process design kit (PDK) and design and layout manual, as well as a wide range of modeling platforms including Spectre, PSpice, and HSpice. Monte Carlo mismatch models are also included."

* Sandwork Design, Inc. announced that its analog and mixed-signal circuit debugging tools have been incorporated into the design flow of Faraday Technology Corp.

George Hwang, Vice President of R&D and Marketing at Faraday, is quoted: "WaveView Analyzer lets us easily process large waveform files with multiple formats. We especially like the way we can view eye diagrams, ADC analysis, and the dynamic meter for design analysis, and compare them in a single environment."

* Synopsys announced that Silicon Logic Engineering (SLE) has adopted Synopsys' VCS RTL verification tool and Vera testbench automation tool to accelerate its chip development process. SLE says it has also adopted Synopsys' Magellan hybrid formal analysis, Leda RTL checking and Formality formal equivalency checking tools from the Discovery Verification Platform. Obviously, a good customer.

Bob Solberg, Vice President of Operations and co-founder at SLE, is quoted: "Synopsys was able to deliver the breadth of tools, proven methodology and responsive support we needed to be confident in our aggressive schedule and quality targets. In particular, Synopsys' RVM enables us to cut our verification development time, while promoting industry best practices within our verification team. The collaborative relationship we have with the Synopsys teams was also a significant factor in our decision making process." Obviously, a happy customer.

* SynTest Technologies announced that a software product called UltraScan is now available for beta use.

Per the Press Release: "The UltraScan architecture consists of three major parts: A Time-Division De-Multiplexing (TDDM) circuit placed between high-speed I/O pads for driving scan chains and the internal VirtualScan broadcaster input ports; A Time Division Multiplexing (TDM) circuit placed between the internal VirtualScan compactor output ports and high-speed I/O pads to bring out scan chains; and VirtualScan broadcaster and compactor circuits "

Ravi Apte, SynTest's Senior Vice President for Business Development, is quoted: "Testing for stuck-at faults and Iddq is adequate to ensure acceptable quality levels for ASICs designed for geometries larger than 130 nanometers. However, for ASICs designed for 130 nanometer or smaller geometries, many defects are no longer static. They become delay defects and it becomes necessary to use delay tests to detect the transition faults and path delay faults. Since these delay tests are more complicated than tests for stuck-at faults, many more test patterns are required resulting in more time on ATE and more memory to store patterns. End result greater is test cost. It is in this environment that UltraScan together with VirtualScan help in reducing the cost of ASIC testing."

* Zuken announced an upgrade to its VISULA PCB Design environment, which allows users to directly integrate with the company's high-speed CR-5000 Lightning tool. The new design environment also provides analysis and what-if capabilities for exploring design scenarios; and trading off signal integrity parameters such as crosstalk, timing or EMI requirements, against mechanical and thermal constraints.

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* Toumaz Technology Ltd. announced that its joint venture with Advance Nanotech – Bio-Nano Sensium Technologies – has developed a board-level demonstrator of the Bio-Nano Sensium (BNS) ultra-lower power wireless monitoring system. The BNS system – the Sensium – is an ultra low power and very small battery size device that can be implanted in or worn on the body with complete freedom of movement, unlike existing bulky monitoring solutions. Trials of the single chip BNS system are planned for the second quarter of 2006.

Per the Press Release: "Bio-Nano Sensium Technologies is a joint venture between Toumaz Technology and Advance Nanotech, formed to create bio-nano sensors that can be implanted within the body to diagnose and treat a wide variety of medical conditions. The development effort will focus on the information and communication technology systems necessary for these sensors to interact with their surrounding environment."

"The Sensium is compatible with a wide range of sensors and can be configured to detect vital signs such as ECG, blood oxygen and glucose, body temperature, and even motion and mobility. With the ability to wirelessly transmit 'problem' event data to network nodes, these locally intelligent sensor interface devices herald a new area in the monitoring and treatment of chronic conditions, promising improved quality of life for patients."