Multicore Expo 2006: CAL prof looks at low-cost MPP systems ...
April 5, 2006
In the past, people demonstrated concepts by building chips, because the chips could be created and once completed, the hardware was hard to change. Power was free while transistors were expensive and a multiplication was slow but memory access was not a bottleneck. Now, due to costs, time, and (un)available tools, researchers don' try to build chips. Power is a problem for large systems while in small process geometries, transistors are virtually free. Memory access and latency is the choking point in a system while a multiply function is a few clocks. In addition, it is now harder to get working software than working hardware for experiments. Historically, a new processor architecture appears about every 6-8 years. The VAX gave way to RISC machines for improved performance. Monolithic microprocessors started with the Intel 4004 with 2312 transistors and have progressed to today's large chips with hundreds of processors on a single chip. All processors are moving towards greater parallelism with 2 to 32 microprocessors in a piece of silicon. The rest of the world is not ready for this advance. Algorithms, languages, compilers, operating systems, are still focused on single computers. Because only the big companies can afford to develop new chips, it now takes years to see new architectures. Programmers don't start to develop tools and programs until after the silicon arrives and is working. So the current problem is that 1000 microprocessor systems cannot become reality unless some type of prototyping system gets into the hands of the researchers and programmers. One research project is looking at this problem, according to Patterson; the conclusion is that if a person could put up to 25 CPUs into a large FPGAs a thousand CPUs would only take 40 chips. All of the FPGAs can fit on a single board, providing a platform for development of computers and languages. RAMP is the current project working on this issue, and Patterson is part of RAMP. He said RAMP is providing researchers access to low cost, low power parallel compute systems. By emulating the open source software community, the hardware in the RAMP project will develop a community that can have capabilities for simplified debug and reconfigurable computing, Patterson said. By having a common platform, researchers could confirm others' results without the time and expense of redeveloping the complete system, and additionally, could view a good percentage of massively parallel supercomputer performance without spending millions of dollars. The RAMP platform starts with working RTL and uses existing hardware. It is capable of running operating systems; its target is to emulate a full system, a clock-cycle accurate system. The goal is to eventually support multiple microprocessors such as the PowerPC, SPARC and the Xilinx MicroBlaze, as well as their major operating systems. Current plans are to forego ARM and the x86 architectures due to licensing issues. Patterson emphasized that everything will be based on the open source philosophy and models. The current RAMP board under evaluation has 4 banks of DDR2-400 memory per CPU with memory bandwidth of over 12,800 MB per second. The intent is to increase emulation efficiency while creating reproducible platforms. Due to the nature of the FPGAs, the board is interconnect-rich and reasonably scalable. More details of the existing boards and processors are available at ramp.eecs.berkeley.edu/. RAMP is a hardware platform and includes a design language for hardware scripting. The design language describes the internal plumbing to the interconnected units. Patterson said that current versions include the HDL and wrappers to add additional functions to the CPUs and can handle designs in any HDL, C, Java or any other language. The platforms will help to address the challenges of organizing large units without having to design all of the unit components. The platform has the potential to check parallel reconfigurable systems. It can simulate any massively parallel processor (MPP) and can be used to teach programming of a MPP without needing access to one of the existing supercomputers. Patterson said the emerging capability to emulate MPPs and its corresponding teaching applications will help to bring a generation of programmers into the environment. Parallel programming is not easy with single threaded uniprocessors and the currently available programming tools. So, getting a large group of people working with MPP systems will facilitate the development of new tools and languages for parallel computing and will enable new research into architectures. Patterson closed by saying that RAMP has the potential to become the standard platform across the industry -- much as the VAX from DEC was in the 1980's -- and can potentially accelerate the development of hardware and software generations. Its abilities to emulate any MPP will expedite changes in all areas as computing moves from sequential to parallel processing. Patterson was enthused when he said that the Lego approach to computers allows interactions and verifiability of many designs. ******************************** EDA industry observer Tets Maniwa can be reached at maniwa_at_sbcglobal.net
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