CEO Forecast 2006: Only Meyer and Rhines are willing to chance a prediction ...
February 14, 2006
Clark opened by lamenting that the Wall Street Journal mostly neglects EDA companies and its markets. He said that should change and received a round of applause. Then, each panelist was invited to make a short position statement. Except for Gary Meyers and Wally Rhines, no one made a forecast – despite the title of the panel. John Bourgoin noted the drivers for IP and reuse include hardware and software standards and programmable logic. System-level design demands an increase in the use of ESL, he said, as well as platform-based design tools and increased hardware-software verification capabilities. Due to the long lead-times for designs, the recent increase in licenses implies good long-term growth for IP in royalties. Aart de Geus, per usual, stated that Synopsys is in a quiet period, so he couldn't actually say anything. He then proceeded to offer up a lot of generalizations and commonly accepted trends for his presentation. He did note that some of the drivers for products will require extensive changes in infrastructure equipment and dramatic reductions in the costs of those services. Mike Fister tried to make a case for value-based tool pricing and a change for the EDA industry from focusing on a refinement model (fix it again) to a correct-by-construction methodology. The role of EDA must change to address the customers' profitability and imperatives, he said. He also noted that Cadence has grown 11 percent on a year-to-year basis during his tenure. John Kibarian attempted to explain that the DFM space is too narrow to be able to address all of EDA for a forecast. He demurred from making any forecasts, however, since he said his domain is a detailed manufacturing knowledge base. He did disclose that overall steady-state yields are dropping with each new process node. The silicon engineering offers the tradeoff of performance and variability, he said. But the DFM knowledge base needs to move to the design areas to be useful. Future design criteria will include some metrics on expected good die per wafer, so increased circuit redundancy will be necessary. Gary Meyers proposed an increasing viable lifetime for silicon processes. He noted that the lithography progression from peak to half of peak volume for 0.5 micron to 0.35 micron took 1.7 years. It took an additional 2.7 years to get to .25 micron. The 180-nanometer generation seems to be on a 3.3-year run, and the 130-nanometer process may be around for as many as 9 years. Meyers added that because so many ASICs are built in the older processes, FPGAs are becoming cost and performance competitive. The industry is seeing the introduction today of new software engineering tools that automatically generate the patterns for the programmable hardware. Xilinx expects to do over $1 billion in DSP functionality devices within 5 years, new programmable logic companies are starting up, and structured ASICs are moving closer to critical mass. Meyers was the first CEO to give an actual forecast for the year – about 7 percent EDA growth for 2006 Wally Rhines tried to show the dependency of EDA growth on the first derivative of R&D funding. If R&D spending is in an increasing pattern when the 3-year licenses are renewed, EDA grows. If the R&D spending is falling in the semiconductor industry when licenses renew, the EDA industry falls. Because the semiconductor R&D is rising now, Rhines predicted an EDA growth of about 2.3 percent for 2006, and a more robust 5.8 percent for 2007 During the Q&A session, Aart de Geus said that future designs would have different goals and approaches. The driver will be integration, and not performance, with economics is the principal target. Any new design must make or generate income for someone to be viable. Mike Fister said that without causality for success, there is no way to increase revenues. Design levels will move up to the system and architectural level. In response to a question on globalization, Fister observed that there is no significant difference in intellectual capabilities between U.S. and foreign (Indian and Chinese) engineers, but the Asians lack the levels of experience that the US engineers have. Labor rates will have to adjust over time, so the engineering costs will become level. Aart de Geus added that the number of engineers is not the issue, but the lack of management. This is changing as their designers get more experience and also as more of the former expatriates return to India and China, he added. In response to a question on changing the market to grow the whole of EDA rather than continuing to simply grab share from the other players, Rhines noted that EDA grows with new technologies – from PCB to ASIC to COT flows. New dollars are generated by new methodologies, while the design complexities are growing so fast that only new tools can address the totality of design issues. There is a need to move to higher-level tools and acknowledge that many new applications are software intensive. Fister opined that growth requires a focus on finding new, vertical markets and a greater view of causality for profitability. Some of the tools will have to target end markets and not the intermediary design flows. Gary Meyers closed by suggesting that finding new markets and new niches can be addresses by programmable logic. ******************************** EDA industry observer Tets Maniwa can be reached at maniwa_at_sbcglobal.net
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