DVCon 2006 Keynote: Synopsys' John Chilton compares
March 7, 2006 John Chilton, senior vice president at Synopsys, Inc., compared and contrasted the design and construction of buildings with the design of integrated circuits in his keynote address entitled "Skyscrapers and Chip Design" at this year's DVCon in San Jose. The intent of the talk was to get designers to consider characteristics other than just functionality as important criteria for their designs. One issue he emphasized is that cost and productivity are now primary drivers in design. Various definitions of productivity are available, but the relevant one is the amount of work output per unit of labor input. To help define the concept, Chilton started with a small construction project as illustration – remodeling a house. Architecture and specifications are analogous to picking cabinets and appliances, he said. Design and verification are the process of building and installing the pieces, while just before "tape-out," the most common disasters are related to specification changes. In the case of a remodeling project, that's a color or pattern change. As an example of a larger-scale project, Chilton cited the Taipei 101 tower currently underway, which he said encapsulates the construction equivalent of Moore's law – it's bigger than anything else out there. If all of the floor space were laid out on a flat surface, it would cover one square mile of earth. In addition, the 101 floors in the building require large quantities of power and air conditioning, and a data and voice communications infrastructure. This building is equivalent to a 20-million-gate IC in complexity, he said. Chilton went on to describe the Center of India Tower in Katangi, which is expected to include 224 floors. It's scheduled to be competed in 2008. This building will be the design equivalent of a 100-million-gate IC, according to Chilton. He said these big buildings are like big designs – they are very sensitive to costs, while relying heavily on the concept of zero errors upon completion. When you're doing a 100-plus-floor building design, Chilton said, you don't have the luxury of a respin to fix problems with materials or structures after the fact. Big buildings and large chips share another common characteristic – large teams of specialists work on these designs. For large chips, the economics dictate that the total revenue for the design be at least 10x the cost of the chip development. Unfortunately Chilton said, most companies cannot determine specific costs for each phase of the design – conversion of specifications to HDL, verification of specifications to RTL and to the final implementation, and finally, physical design. The Synopsys services group has now started measuring the costs Chilton outlined, and has found that about half of the costs are associated with some point function and the balance in design. Such costs are related to specific chip attributes – internal complexity and functionality. When the Synopsys group reviewed the data and other results, Chilton said they found that improvements are result from attention to flows and tools. They also concluded that greater improvements are possible on the smaller, simpler designs. The design infrastructure contributes to productivity in the following ways, Chilton said. First, changing from Verilog and VHDL to SystemVerilog builds verification tools and technologies into the process, and reduces the total number of lines of code needed to describe the design. Reducing the number of lines of code tends to reduce the number of possible bugs needed to be found and cleared. Second, using SystemC for verification tasks is important. The advantages of transaction-level modeling and the ability to include system-level software as a part of debug greatly reduce the time and effort needed to complete verification. Third, moving to more parallel processing through the use of Linux farms and multi-threaded tools reduces the time needed to process the HDL. Fourth, changes in the place-and-route tools, including improved algorithms, higher levels of abstraction, and reduced data transformations in the P&R flow contribute to additional overall improvements. Finally, changes in the design environment help improve productivity. By changing point tools to integrated, full-featured suites the design teams can reduce data translations, data errors, and achieve higher throughput. In addition, using a tool that generates new scripts for the tool flows for each new design eliminates out-of-date scripts and tedious, error-prone script modifications. Together, these infrastructure changes can provide up to a 2x improvement in design team productivity according to the Synopsys calculations. At the next level – project level – project management is the key to productivity improvements. Important tasks for the project manager include deliverables control, managing the quality of IP, and increasing the use of IP in the design. In general, the quality of most deliverables is not great and is likely to be incomplete, Chilton said. Over time, the quality can be improved if the IP is functionally correct, and has integration and usability support. Changing from block-level design to chip-level or platform-level design reduces the amount of detail work needed for any design. The next step is to have all blocks, per function and associated operating code, available and verified at the start of the project. This pre-fabrication approach minimizes redundant and incomplete verification at the regression stages, since they are verified as complete entities including wrappers and interconnect as well as software drivers. Chilton said that all of the previous steps depend on a divide-and-conquer approach with respect to the tasks of design and verification. Increases in development time are much more expensive than any other cost increases, since the development costs far exceed any other manufacturing and support costs. The need for better control of development costs, therefore, shows up in time-to-market types of surveys and has been proven to be the driver for total-project lifecycle costs. To get the best results and greatest productivity improvements, according to Chilton, companies will need to partner with experts in the field to adopt the best tools and methodologies to their environment and work standards. Using a divide-and-conquer approach coupled with a change to higher levels of abstraction – namely, system-level design – can contribute a significant amount to the productivity of an IC development team. Chilton concluded with advice for his audience: Plan to change and improve your productivity by building up your design capabilities. By achieving better design productivity, you will have greater overall success in building your business. ******************************** EDA industry observer Tets Maniwa can be reached at maniwa_at_sbcglobal.net
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