Bernard Meyerson, vice president of technology at IBM Corp. talked about "Watts happening in technology" or "Why has GHz disappeared from the marketing lexicon?" in his keynote presentation at CDNLive! on September 12, 2005 in Santa Clara, CA.

Although Peggy Aycinena may not have liked his presentation style, I like the idea that a serious scientist can lighten up and enlighten people on a very technical set of topics.

Meyerson started by noting that Moore’s Law was really about economics and technology and did not really address the issues associated with classical scaling. Moore only discussed changes in linear dimensions and didn’t look at the other 18 or so parameters that must be addressed to achieve rational results. Essentially, you must scale all of the parameters of devices and processes to keep power density a constant or the results quickly become unacceptable and unreasonable.

Among Meyerson´s many other comments:

Power scaling cannot be avoided. Historically, computers become smaller and faster over time, but this also leads to higher power density. The old mainframes got up to 5 Watts/cm2, equivalent to a steam iron. The transition to CMOS from bipolar reset the power-density curve to low levels by allowing increased parallelism and lower standby current, but power density is still on an exponentially increasing curve.

There is no obvious, next, simple silicon technology to keep power in check. Even worse, the scaling that drives increases in performance and reductions in cost are now making the standby power a significant, mandatory consideration for designers.

Technology and process innovations have replaced scaling as the way to see increases in performance. Strained silicon and its successor, symmetrically strained silicon, have increased individual device performance by over 35,000 percent, compared to only a doubling of performance possible from linear scaling.

Furthermore, changes in the technology roadmap will require major developments in gate oxides to high-K values, double gate and finFET topologies. Physical extrapolation is no longer viable.

In the area of interconnect, all metals have increased resistivity at dimensions approaching 1000 angstroms due to the increase in grain boundaries. To make things worse, the capacitance is increasing at lease as fast as the resistance. The ideal interlayer insulator would have a dielectric constant of 1. Unfortunately, materials that approach unity have the physical characteristics of a vacuum. So, the next generation of devices will need to change materials to address the physics requirements.

Current research is looking at low-K materials, leading to ultra-low K materials for interlayer dielectric materials to enable lower parasitic capacitance. After the solid materials, will come porogens and eventually air gap materials. Innovation in technology and not physical scaling will, therefore, drive CMOS performance.

The 65-nanometer process node will be the last one to depend on classical scaling. The inevitable increase in variability will move design for manufacturing (DFM) into all design areas. DFM automation will measure, model, mitigate, and calibrate designs against manufacturing requirements.

An example of this integration of design and manufacturing is at-speed wafer testing which can extract DC parameters at the 2nd metal for critical device characteristics. This dynamic in-line analysis requires increased model sophistication and the merging of design and technology CAD (TCAD) databases. In addition, the tools need the ability to modulate performance with the layout and mitigate risk by thermal simulation in the TCAD.

Process variability will have serious effects on timing and other parameters. Some alternatives to solve this problem are to increase the 3 sigma width, increase guardbands, or move to true statistical timing. The next generation devices will need a unified yield model that incorporates a virtual fab as a part of the device characteristics.

In addition to the changes in design that include manufacturing, the next set of design tools will need to have a holistic approach from atoms to systems software and will need to model all facets of the end system.

The old semiconductor-centric view focused on integrating intellectual property into silicon for better system performance. In reality, however, semiconductor performance improvements have resulted in an approximately 15-percent increase in system performance over time, while system architectures and software have accounted for about a 90 percent improvement in the same time frames.

Improved system performance will come from increased virtualization and micro-partitioning as well as more processing cores or engines within the system. The increased granularity will demand more communications capabilities, from very low latency to very high bandwidth channels.

As an example of this approach, the IBM Blue Gene/L supercomputer resulted in a machine that is 100x smaller and uses 1/28th of the power of the previous generation of machines. At the chip level, the new Cell chip, developed with Sony and Toshiba achieves the equivalent of 256 Gflops in a 64 bit environment.

Among Meyerson´s conclusions – innovation and not device scaling will become the driver for performance. This will change processor and other device design and metrics to reflect system performance rather than core operating frequency.

Systems will have to be designed in a holistic manner to address the complete range of requirements from system through to manufacturing. These systems will have to incorporate application specific functional units to meet system throughput and power requirements.

Finally, the complexity and cost of the next generation designs will force more companies to form alliances and will increase overall industry consolidation.

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