Places November 9, 2004 So many places to go, so much to learn ...
The second forum - "How Does the Design Chain Need to Reconfigure Itself to Address the Manufacturing Challenges of the Nanometer Era?" - will be held during the Cadence Partners Event on December 2nd, in San Jose. Organizers say that discussion will center on "how significantly increasing complexity has severely hindered the ability to effectively develop, integrate, and ramp new technology nodes, as experienced at 130 nanometers. Design and photomask costs are skyrocketing and are dramatically affecting the business model for lower-volume ASICs and SoCs. The disaggregated design chain must invest in new, more integrated solutions, form strategic alliances to increase collaboration, and reintegrate to enable customer success at advanced processes." Pretty weighty stuff. ( www.cadence.com.)NanoTech Seminars - Hosted by Magma Design, the seminars will "provide designers, developers, engineers and managers with information on how to address nanometer design challenges ... At these informative and interactive technical seminars you’ll hear how cutting-edge semiconductor companies are using Magma’s IC implementation solution to reduce their IC development costs." This may all sound pretty vendor specific, but I'm betting that there's lots of learning to be had nonetheless. November 15th in Santa Clara, November 16th in Boston, and November 18th in Denver. ( www.magma.com.)Asian Test Symposium & Workshop on RTL and High Level Testing - ATS and WRTLT will be co-located conferences will be taking place in Kentig, Taiwan from November 15th to 17th. Organizers say: "Following the traditions set up by its predecessors, ATS'04 aims to provide an open forum for worldwide researchers and industrial practitioners to exchange innovative ideas on VLSI testing. This year, the theme is on the 'Enabling Technology For SOC Production,' covering all aspects of technical issues on design-for-testability, test integration, diagnosis, repair, and yield enhancement of a complex chip with embedded digital, analog, and/or memory components. Please note that "co-located" is somewhat of a relative term here. WRTLT is actually taking place in Osaka, Japan on November 11th and 12th. Organizers say, "The purpose of this workshop is to bring researchers and practitioners on LSI testing from all over the world together to exchange ideas and experiences on register transfer level (RTL) and high level testing." The hope is that you will attend WRTLT and then move on to ATS. Not a bad idea as both Japan and Taiwan, like most places in the world, are lovely at this time of the year.( http://wrtlt04.su.cit.nihon-u.ac.jp/~wrtlt/)Software Developers Forum Distinguished Speaker - U.C. Berkeley's Steven Weber will be speaking on November 18th on "The Co-evolution of Innovation: How Open and Closed Systems Together Will Shape the Future of Property Rights." Weber says that his talk will critique the "naive use of 'the commons' notion, and explain how open source does and does not reflect the logic of the commons." I'm guessing that if you're reading EDA Confidential, you probably have some pretty strong opinions of your own on this topic, so maybe you should plan on attending. Like last month, the presentation will be at the Xerox PARC Auditorium in Palo Alto. By the way, Wind River's Jerry Fiddler will be doing the introductions. Should be very interesting! ( www.sdforum.org/dss) |