Beach Solutions announced it has acquired VCX Software, Ltd., an IP management, profiling, delivery, and IP portals. VCX runs the portal: www.theVCX.com. Beach says it is "committed to enhancing theVCX.com portal and supporting the numerous commercial and informational websites that utilize the VCX Gateway search engine. This acquisition further enhances Beach’s design environment by adding the robust and scaleable VCX database and its proven IP management infrastructure." Terms of the agreement were not disclosed, however it is known that the VCX staff, technology and IP are transferring to Beach.

Jim Ensell, Chair of the FSA IP Subcommittee, is quoted in the Press Release: "VCX Software has in its many guises, been a real contributor towards the creation of a higher quality IP supply-chain. This new combined entity of VCX Software and Beach solutions technology promises to bring some exciting new and practical solutions that will help the FSA drive its mission to create a robust, high quality IP supply chain for the benefit of its membership."

Simon Davidmann, EDA entrepreneur and VCX Board member, is also quoted: "The combination of VCX and Beach is a natural and compelling fit. The domain above RTL is very complex, unstructured and risky. But I believe that in the next 5-10 years as Moore's law terminates, the activity in the back end of the chip design process will stabilize, with much of the innovation and value in EDA moving to the front end. The front end of EDA will be the place to be and it will be a new generation of company such as Beach Solutions that leads the way."

Synopsys, Inc. announced it has acquired "certain assets" and hired the engineering team of LEDA Design, a developer of mixed-signal IP. LEDA Design has a team of 80+ experienced digital and mixed-signal IP design engineers and support personnel located in Yerevan, Armenia who will now join the Synopsys DesignWare IP engineering team. The terms of the transaction are not being disclosed.

Open Core Protocol International Partnership (OCP-IP) announced an updated version of their OCP 2.0 compliant transactional models implemented in SystemC. The organization says the models "standardize the way OCP- based communication is modeled at various abstraction levels. Their availability ensures increased model interoperability and reusability. The updated OCP SystemC transaction channel models include a speed-optimized transaction layer 2 (TL2) channel. This new TL2 channel is up to 100% faster than the previous version. The new release also includes an OCP monitor and layer adapters."

The Embedded Microprocessor Benchmark Consortium (EEMBC) says it "plans to add an energy consumption metric to the performance scores it provides for embedded processors tested against its application-focused benchmarks. The consortium has formed two working groups to establish methodologies for the energy consumption benchmarks."

"A group addressing energy measurements for hardware platforms and devices is being headed up by Shay Gal-On of PMC-Sierra. A group addressing energy measurements using simulation for IP processor cores is being headed up by Moshe Sheier of CEVA. The consortium has additionally engaged the services of David Kaeli, associate professor in Northeastern University's Department of Electrical and Computer Engineering and director of its Computer Architecture Research Laboratory, to guide its energy benchmark developments. Kevin Kranen, director of strategic programs at Synopsys, has also been actively involved in this process."

EEMBC's members have agreed that the energy metric will be an optional component of the performance benchmark scores published for each processor and will take into account the energy consumed by the benchmarked devices while running each of the consortium's application-focused benchmark suites. Once the standardized methods are finalized, the details of how EEMBC measures energy consumption will be available for download from www.eembc.org. EEMBC invites companies involved in related activities to join its energy metric development efforts." Seems like an extremely reasonable request.

** Pals & Partners **

True Circuits, Inc. announced it has signed Amos Technologies as an authorized sales representative for True Circuits silicon-proven timing IP in Israel.

TeraSystems, Inc. announced its membership in the LSI Logic RapidChip Partner Program, which the companies say "offers Platform ASIC customers RTL analysis and physical prototyping tools to develop advanced, next-generation products efficiently. The RapidChip Partner Program reduces time-to-revenue, design risk and system costs by providing Platform ASIC designers with third-party development tools; these include intellectual property, design services and design tools that combine quality and flexibility for consumer, communications, storage and other markets." That's a lot!

Ronnie Vasishta, Vice President of Technology Marketing at LSI Logic adds emphasis in the Press Release: "TeraForm-RapidChip can help to dramatically shorten development cycles as it is tightly coupled to the RapidWorx design system for design integrity, ease-of-use, reuse, support and quality."

Synplicity Inc. also says it has joined LSI Logic's RapidChip Partner Program. As everyone knows, and the Press Release emphasizes: "Synplicity and LSI Logic have worked closely together for more than 18 months to develop customized synthesis and physical synthesis software that targets LSI Logic's RapidChip platform ASICs. With Synplicity's membership in the RapidChip Partner Program, RapidChip customers are able to utilize the Amplify RapidChip software, the only physical synthesis solution optimized for RapidChip devices, delivering the best performance, density and design productivity for LSI Logic's platform ASIC devices."

So, now you won't be surprise to learn that ...

LSI Logic announced the formation of the RapidChip Platform ASIC Partner Program, a cooperative effort between LSI Logic and third-party providers of IP, design services and EDA tools. The 13 initial companies participating in the first partner program in the Platform ASIC space include: ARM, Arrow, Denali Software, GDA Technologies, Memec, PLDApplications, Pinpoint Solutions, Synplicity, Silicon Infusion, TeraSystems, Daito Electron Co., Innotech, and Reptechnic Design.

** New Business Cards **

Golden Gate Technology, Inc. announced that Dennis Heller has been named as CEO. The company also reminds readers that it recently received $9 million in first-round venture funding. Dennis Heller has approximately 20 years of EDA experience, including executive and management roles at Avanti, Synopsys, and IKOS Systems. He began his career as a microprocessor designer. Heller has a BSEE and MSEE from the University of Wisconsin, a school which is currently making him very proud on the football field (albeit still ranked behind Cal, one might point out). With Heller as CEO, now Michael Burstein, company Co-founder and CEO, will serve as CTO. Please recall that Burstein co-founded Gambit Automated Design, which was acquired by Synopsys, and Descartes Automation Systems, which was acquired by Mentor Graphics. Surely, here is an individual who knows how to spell 'Exit Strategy.'

Aldec, Inc. announced that its Active-HDL product has been selected as "the most easy-to-use HDL simulator with the best price for its value." The company says the award is part of the first annual FPGA Journal Awards sponsored by FPGA and Programmable Logic Journal and that winners were selected based on feedback from design engineers in several formal surveys and studies held over the course of the year. Kevin Morris, Editor-in-Chief of the journal is quoted in the Press Release: "Users responded that Aldec's simulator was extremely approachable and easy to learn. In addition, they highlighted the company's whole-solution approach to simulation and debug and its clear focus on FPGA design in particular. Readers also found Aldec's tools to be an outstanding value for the price."

AccelChip Inc. announced today that company CTO and Vice President of Engineering Michael Bohm has been invited to speak at IEEE Signal Processing Society meetings across the U.S. and Canada. Bohm’s presentations focus on "the process and challenges of implementing a MATLAB algorithm in an FPGA or an ASIC. It discusses topics such as design style; micro-architecture trade-offs for area, speed and latency; and the challenges of using FPGAs as DSP accelerators."