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** The Fab Owners Association (FAO) announced the addition of its latest member, Spansion LLC, the Flash memory venture of AMD and Fujitsu Ltd. The FOA has also announced the addition of National Semiconductor and Applied Materials as new associate members

The semiconductor manufacturers represented in the FOA have combined annual revenues of $9.7B and control over 600,000 8" equivalent silicon wafers manufactured in the world on a monthly basis. FOA's announced members are AMI Semiconductor, Cypress Semiconductor, Delphi Electronics, Fairchild Semiconductor, Intersil, Jazz Semiconductor, LSI Logic, Micrel Semiconductor, ON Semiconductor, Spansion, and ZMD AG.

L.T. Guttadauro, FOA Executive Director, is pleased: "Spansion's addition is reflective of our ongoing commitment to enhance our membership with semiconductor technology leaders. Expanding membership allows us to pursue efficiencies that are not practical for a single company. Our associate members are also essential, providing our member companies with quick access to innovations in technology and service. We are constantly developing programs that put associates together with member company senior executives."

** Design for Debug Consortium – An open meeting to discuss the requirements of design for debug (DfD) products and methodologies will be held at DAC. Meeting organizers will announce the formation of a new DfD Consortium to facilitate the functional debug of silicon devices mounted in the target system (referred to as "in situ"). All interested parties are encouraged to attend, including: Vendors of DfD-related offerings such as software, intellectual property, hardware ports and methodology training; electronic system/chip designers with DfD experience and/or interest; industry consultants, standards organizations and associations; and market research analysts and trade media. This is interesting!

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** Berkeley Design Automation Inc. has announced its entry into the analog/RF IC verification market. The company's mission is: "To address the major verification challenges in the design of high-performance analog/RF ICs."

Per the Press Release: " Dealing with the nonlinear and stochastic behavior in analog circuits is a major challenge for designers because the analog circuits not only generate noise internally, but they are also extremely sensitive to noise generated by other circuits in an SoC. Existing analog verification tools lack the circuit analysis technology required to accurately analyze noise when operating in a nonlinear time-varying environment. Often, designers are forced to use silicon iterations and a variety of approximation methods to analyze noise in order to minimize noise problems."

The company’s technology is based on research conducted by the founders at U.C. Berkeley and the University of Illinois, and addresses characterization of nonlinear, stochastic, time-varying behavior of complex analog and RF circuits. Products using this technology provide very accurate predictions that dramatically reduce the need for silicon re-spins. The company has announced its initial product, PLL Noise Analyzer.

Berkeley Design Automation was founded by Amit Narayan, Vice President of Engineering; and Amit Mehrotra, CTO; who did their doctoral research together at the Berkeley. Amit Mehrotra’s Ph.D. thesis topic and his research at the University of Illinois "set the foundation" for the company's stochastic nonlinear circuit analysis technology. This technology enables the accurate modeling of the nonlinear, time-varying behavior of circuits at the transistor level.

Ravi Subramanian, Berkeley Design Automation's president and CEO. "Our customers have told us that the greatest challenge in the design process today is to reduce the rate of silicon spins required to achieve volume production for these analog-rich ICs. Berkeley Design Automation has successfully delivered to the market a new generation of IC verification technology that has been customer-validated to provide greater predictability and certainty to the design of these complex ICs."

Abbas El Gamal, Professor of Electrical Engineering and Director of the Information Systems Lab at Stanford University. "The increased performance demands and circuit complexities make the noise analysis approaches used in traditional tools grossly inaccurate. The circuit analysis technology developed by Berkeley Design Automation provides fast and accurate noise analysis for current and future analog/RF circuits." Nice to hear a Cardinal endorsing a Bear!

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** Arteris SA announced it has named K. Charles Janac as CEO. Alain Fanet, Founder and initial CEO at Arteris, will become CTO Per the Press Release: "Janac’s career spans 20 years and multiple industries including electronic design automation, semiconductor capital equipment, nanotechnology, industrial polymers and venture capital. In the first decade of his career, he held various marketing and sales positions at Cadence Design Systems where he helped build it into one of the ten largest software companies in the world. He joined HLD Systems as president, shifting the company’s focus from consulting services to IC floor planning software and building the management, distribution and customer support organizations. He then formed Smart Machines, manufacturer of semiconductor automation equipment and sold it to Brooks Automation. After a year as Entrepreneur-in-Residence at Infinity Capital, where he consulted on IT investment opportunities, he joined Nanomix as president and CEO helping build this start-up nano-technology company. Janac has a BS and MS degree in Organic Chemistry from Tufts University and an MBA from Stanford." Another Cardinal in the news!

** Bluespec, Inc. announced that Brian McAloon, Group Vice President, DSP, Media and Communications Products for Analog Devices, has joined Bluespec’s Board of Directors. Per the Press Release: "With Analog Devices since 1987, McAloon has been serving in his current position since 2001 where he is responsible for Analog‘s General Purpose DSP products, wireless handset and broadband chipsets, and various audio and video processing solutions. McAloon began his Analog career as General Manager of Analog's Irish Division before becoming Vice President of Europe in 1991 and then Vice President of Worldwide Sales and Marketing in 1992. Prior to joining Analog Devices, McAloon held a number of senior management positions in Design, Manufacturing and Sales with National Semiconductor in Scotland and South East Asia. He has a BSEE from Glasgow University in Scotland."

** Forte Design Systems announced two new executives, plus the expansion of its sales team in Europe and Asia. The

Tom Katsioulas has been named Senior Vice President of Strategy and Business Development. . Katsioulas brings over 20 years of experience in EDA and IC industries. Prior to joining Forte he was a management consultant for EDA startups following his tenure as the founder and CEO of AmmoCore Technology. Katsioulas has also held senior marketing positions at Cadence Design Systems and led product strategies that quadrupled their physical tool business. Prior to Cadence, Katsioulas held management and engineering positions at Tangent Systems and Digital Equipment Corporation.

Brett Cline, formerly Forte’s vice president of marketing, has been promoted to the role of vice president of customer operations & services and corporate communications. Jacob Jacobsson, Forte’s CEO,. is quoted: "Forte places a great deal of importance on active support and communication with our customers. Brett’s job is to ensure the continuing success of our customers in using our products, thus supporting the accelerating use of our products in our customer base."

Forte also announced its European headquarters in Grenoble, France, headed up lby François Constant and Vincent Thibault. Constant has 20+ years of industry sales experience having held management positions at Summit Design and Synopsys. He was also co-founder and CEO of Arexsys. Thibault joins Forte as European applications manager having held a wide variety of technical and management positions at Synopsys and Sagem Group.

Forte has been busy – the company also announced it has signed Seloco as its Korean distributor.

** Silicon Navigator Corporation announced that its CEO and founder George Janac has been elected as a new member to the Silicon Integration Initiative (Si2) Board of Directors for 2005-2006. Silicon Navigator has a Director-level membership in Si2's OpenAccess Coalition, and Silicon Navigator's VP of Engineering, Steve Potter, was recently elected to represent Silicon Navigator on Si2's OpenAccess Change Team. Silicon Navigator says it is the only startup represented on the Board and on the OpenAccess Change Team.

Steve Schulz, President & CEO at Si2, is pleased: "I wish to welcome our new Board member, George Janac. We are extremely pleased to have his insight and expertise on the strategic and business affairs of Si2. Mr. Janac has founded and led a number of successful EDA startup companies, and Silicon Navigator is breaking new ground in the development of infrastructure for the OpenAccess ecosystem."

** Tensilica, Inc. announced that Antonio Viana has joined the company as Senior Vice President of Worldwide Sales. Viana comes from ARM, Ltd., where he was Vice President of North American sales. Viana has worked for ARM since 1998 and held a number of positions during his tenure there. Prior to ARM, he was director of sales for Encore Industries and worked for SGI and Hughes Aircraft. He has a BS in industrial and systems engineering from California State Polytechnic University at San Luis Obispo.

** VaST Systems Technology Corp. announced that Erin Marshall has been named as sales director of US Central Region and John Faase has been named as director of US Sales-West.

"Erin Marshall's experience as vice president of sales for Barcelona Design, Inc., and her experience in both sales and operations for Cadence Design Systems and as enterprise business director for Texas Instruments make her exceptionally well qualified to head the VaST central region sales effort " said VaST CEO Alain Labat in the Press Release> "John's background as a highly successful business development and account manager for Synopsys, design manager for Intel , and regional sales manager for Nassda Corp. and Synplicity make him similarly well qualified to lead our western US sales effort. I am personally delighted to add the extraordinary talents of John and Erin to the VaST team. Both will enable VaST to provide an even higher level of support to our customers."

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** Gabe Moretti, noted EDA veteran, has launched a new web-based publication: GABEonEDA.

The site is dedicated to the thoughtful analysis of the EDA industry. It provides articles, selected product reviews, and a chance to talk back through its Letters to the Editor facility. The goal of the new site is to distill the events and cover those that have or promise to have a significant impact on our industry. In addition to covering EDA tools and methodologies, the articles and product reviews will also cover semiconductor and IP news. The content of the site will be updated at least 26 times a year.

"This is not technically a blog," said Mr. Moretti "although it is a vehicle for my own editorial opinions. It is also a source of distilled news items that impact the industry."

EDA Confidential Editor Peggy Aycinena can be quoted: "Welcome to the neighborhood, Gabe!"

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** Chartered Semiconductor Manufacturing updated its second-quarter guidance, which was originally provided on April 22, 2005.

George Thomas, senior vice president & CFO of Chartered, is quoted: "Revenues including our share of Silicon Manufacturing Partners (SMP or Fab 5) are now expected to be at the higher end of our prior guidance and revenues at Chartered level are expected to be approximately at the mid point of our prior guidance. Our share of SMP revenues is expected to be higher than prior guidance. Consistent with higher revenues, our second-quarter net loss will be at the lower end of the range guided previously."

** YOGITECH says it has raised "early stage" venture capital financing from Toscana Venture of SICI. (Sviluppo Imprese Centro Italia) The One Million Euros investment will support the first phase of the commercial and technological development of a new leading technology.

Silvano Motto,CEO of YOGITECH, is quoted: "YOGITECH invested strategic resources and expertise in the fields of Robustness and Safety and the raised capital will allow YOGITECH to boost the development of our innovative patented approach. This is complementary to the current products’ portfolio and offer, therefore it will also strengthen YOGITECH’s commitment to the current business units."

Mr. Ulivagnoli, Private Equity Manager of Banca CR Firenze, is keen to represent SICI at YOGITECH’s Board: "I see YOGITECH as a high potential outsider worth to be financially supported on the ground of its business credibility and realistic goals".

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** UMC announced that is has reached a major milestone with the celebration of its 25th anniversary this month.

Per the Press Release: "Since its establishment as Taiwan’s first semiconductor company in 1980, UMC has grown to become a major global IC foundry service provider at the forefront of SoC production technology. The company’s ability to thrive for a quarter of a century in one of the world’s most competitive and challenging industries was highlighted in 2004 with record high revenues of US $3.7 Billion."

"UMC was initially founded as a small-scale IDM chip manufacturing company in 1980, that licensed technology from RCA to enable the delivery of its first product: an electronic watch IC. The company began its transformation into a pure play foundry in 1995 by establishing three separate joint-venture foundry companies. UMC acquired a fourth local foundry company in 1998, and in 2000 the group completed Taiwan’s largest ever merger with the consolidation of the five joint-venture companies into a single foundry, UMC."

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** Accellera announced three additional video tutorials from the 2005 Design & Verification Conference have been posted by Demos on Demand. Check it out on the Accellera website. Tutorials include; SystemVerilog assertions: Best practices for functional verification; Pragmatic ABV: Effective assertion-based verification; Transitioning to SystemVerilog for verification