There’s been a plethora of news from VSIA, SPIRIT, and Accellera ...

** VSIA Reorganizes - These excerpts are from a recent letter to the membership announcing the reorganization:

"The VSIA Board and Staff have completed a great deal of research over the past year, looking into both the commercial and technical relevance and opportunity for VSIA and VSIA initiatives. Based on this study and research, we have identified a restructure plan that we will describe within this letter. As you know, no organization, whether a for-profit corporation, non-profit or government entity, can remain static over time and also remain relevant. As our industry has evolved, so have the challenges ahead and our mission has changed to address these challenges. Our new mission drives our structure, ensures that VSIA will be guided by the leaders of the SoC industry, and that the standards, specifications and documents we create will be more broadly adopted."

"We have an opportunity to more fully develop as ‘The’ SoC/IP umbrella organization focused on both commercial and technical solutions to the complex issues of SoC and IP development, IP integration and reuse. Taking on this challenge requires that we restructure and move from our many groups (DWGs, TC, Adoption Groups, Advisory Committees, etc.) to a "Pillar" approach. The Pillars will address both technical and commerce issues and they will have legal and marketing support—all within the Pillar. Each Pillar will have a base of representation from at least four large companies who are committed to the Pillar issues. Any company of any size who wants to participate will be encouraged to join, but the Pillar will not be created without the large companies. The reason for this structure is to streamline our approach, allowing us to produce work more efficiently and faster, and to ensure that the work created reflects the needs of the industry and will achieve broad adoption."

"We will start with three Pillars: The IP Quality Pillar, the IP Protection Pillar and the R&D Pillar. Most of the other DWGs that currently exist will be moved to the R&D Pillar. This will allow the interested VSIA members to further explore the issues in a more interactive, research-oriented environment and then determine if the efforts warrant a separate Pillar. There is still work to be done to fully identify how Pillars will form, who will join and at what stage, what happens to work coming out of the Pillar, how is it approved, and who gets access to documents and other work and when. These issues will be worked on over the next few months."

Susan Cain, newly named as Executive Director of VSIA, invited members in a separate communiqué to submit their "thoughts and comments" on the new structure and other related issues.

Meanwhile, I had a chance to chat by phone with Mike Kaskowitz, VSIA President, who told me: "These are fundamental changes in VSIA. In the old structure, the DWG did the technical work and the Board got together to drive things. The VSIA itself produced the output of these documents, but with so many activities going one, we weren’t having a particularly large amount of member participation. Now VSIA will be the incubator for various standards, where they can be totally handled within each Pillar. No permissions or approvals will be required from the Board to move forward. We’re wanting four companies, more or less, to be at the core of each Pillar - senior people, not just engineers from the 4 different companies. If member companies really put some meat behind what they’re doing in VSIA, [we’ll see concrete results]."

"Why did organizations like SPIRIT [appear], causing a bit of frustration in the industry over the introduction of yet another organization? SPIRIT was created because some people felt there was ineffectiveness on the part of VSIA to get things done. At VSIA, we got to a point where we felt that if these other organization were springing up, then we must be becoming irrelevant to the industry. In response to that, however, a lot of people said, ‘No, VSIA is important!’ That’s why our Board felt that by a reorganization we could become a place for incubating [new ideas and standards]."

"I definitely agree that we’re competing a bit for the hearts and minds of the industry. The old VSIA was unfortunately viewed by some as stodgy and unable to get things done. Now we intend to be more successful, and I would hope that top management in our member companies will know about it. We’re basically saying to the industry - people love to offer criticisms and critiques, but the solving of problems is something entirely different. We’re saying put up or shut up, and hoping that every member in VSIA joins a Pillar and understands anew why they’re involved with us. We’re literally calling people bluff. We’re saying we have a solution, do you want to be part of it? If the industry wants VSIA to continue to exist, they’re going to have to be willing to put their energy into it."

** The SPIRIT Consortium (Structure for Packaging, Integrating and Re-using IP within Tool-flows) announced that it has released a proposed SPIRIT 1.0 standard to the SPIRIT membership for review. The consortium says Version 1.0 is expected to be approved for public release in Q4 2004 and will provide a standard to support multiple industrial tool-flows and IP libraries.

Per the Press Release: "The proposed SPIRIT 1.0 specification provides a complete solution for RT-level SoC design encapsulation and IP interoperability, as well as interoperability of configurable and non-configurable IP with multiple tool sets. By enabling a standard machine and human readable description of IP block structure and general attributes in XML (eXtensible Markup Language), SPIRIT-compliant IP will be able to flow smoothly into EDA tools that support the SPIRIT format, such as system design, co-verification, simulation and synthesis tools."

"Having achieved a major milestone towards an approved SPIRIT 1.0 standard, the consortium today sets itself a new target - to release a SPIRIT 2.0 (Version 2) standard, which extends the specification to cover interoperability between tools and extends the technical scope to explicitly support Electronic System Level (ESL) and Verification. This will include, for example, the ability to launch application-specific tasks operating on SPIRIT formats from within different EDA tools. It will also enable provision of configurable IP for automated ESL design, assembly, verification and simulation."

Ralph von Vignau, Consortium Chairman and Director Technology & Standards of Philips Semiconductors Chief Technology Office - Reuse Technology Group, is quoted: "Thanks to the tremendous effort put in by the consortium’s founding companies, we now have a proposed specification for review that will allow members to encapsulate IP blocks and share them with each other to validate interoperability of IP libraries and multiple tool sets."

** Accellera announced that its Board and Technical Committee members have approved SystemVerilog 3.1a as an Accellera standard for language-based design verification, and that the organization has begun the IEEE standardization process.

Dennis Brophy, Accellera Chairman, is quoted in the Press Release: "SystemVerilog 3.1a truly heralds the age of unified design and verification languages. Our work on language-based design started over 10 years ago with the Verilog and VHDL hardware description language standards, and we are very pleased to announce another significant milestone in the evolution of design language standards that improves both design and verification and to be working with the IEEE-Standards Association to accelerate the accreditation of SystemVerilog 3.1a."

Vassilios Gerousis, Accellera's Technical Committee Chairman, is also quoted: "The SystemVerilog 3.1a committees have analyzed over 300 feedback items with 90% approval, indicating wide acceptance of SystemVerilog by both users and EDA vendors. Based on this community feedback, the SystemVerilog technical subcommittees focused our 3.1a release on the stability of the language and the addition of user-requested enhancements. As we did with SystemVerilog 3.0 and 3.1, we maintained complete backward compatibility with the IEEE Std 1364-2001 standard and SystemVerilog errata releases."

In addition to correcting errata discovered in SystemVerilog 3.1, SystemVerilog 3.1a incorporates new features and donated technology from Bluespec, Mentor Graphics, Motorola, Novas Software and Synopsys, which has been added to earlier SystemVerilog technology donations from Real Intent and Synopsys for version 3.1.

Per the Press Release: "SystemVerilog 3.1a enhancements include the extension of memory system tasks for complex memory modeling, operator overloading for simplified expressions, and tagged unions with pattern matching for code conciseness and improved formal analysis. Assertion enhancements aim to improve the ability of designers and verifiers to specify design intent and behavior. These include environmental constraints to facilitate formal analysis and random simulation, and a broader scope of assertions for more comprehensive behavior specification. Enhancements for testbench generation include: fine-grain process control for multi-threaded testbench development; dynamic and static queues and stream generation for complex verification scenarios; virtual interfaces for flexibility and expressiveness of testbench infrastructure; random weighted case and functional coverage for users to set up a meaningful constrained-random environment."

"Several of SystemVerilog 3.1a's features are aimed at improving the existing Verilog use model. Separate compilation and packages allow a C- or VHDL-like approach to compiling code in individual pieces. A vendor-independent API allows access of proprietary waveform file formats for higher performance and obsoletes the disk-consuming ASCII Value Change Dump (VCD) files. SystemVerilog tasks can be exported in the DPI so that a foreign language can interact with SystemVerilog as if it were interacting with its own, such as a C routine that calls a task that consumes time and blocks until that task completes."

In further developments, Accellera and the IEEE Standards Association (IEEE-SA) announced May 28th that Accellera is giving the copyright of its language reference manual for SystemVerilog 3.1a to the IEEE-SA's Corporate Advisory Group.

Per the Press Release: "This group provides a platform for developers to produce market-relevant, full-consensus IEEE standards and will help guide standards through rapid accreditation. Further, Accellera recommends a liaison be designated between the SystemVerilog Study Group and the Verilog 1364 Working Group to ensure coordination. By offering the SystemVerilog 3.1a LRM copyright to the IEEE-SA, Accellera fulfills its promise made at last year's Design Automation Conference. The transfer of standards to the IEEE is the final stage of Accellera's proven development and standardization process. The IEEE-SA will provide its focus on global standards to SystemVerilog and will support a complete spectrum of corporate development services including liaison with related IEEE societies and other IEEE corporate functions. The ongoing, strong partnership between Accellera and IEEE-SA is expanded through the IEEE-SA's corporate standards program."

Not everyone is as enthused as those quoted in the Press Release, however. In fact, acrimony was the order of the day at the Accellera breakfast panel on Wednesday, June 9th, at DAC in San Diego where it was obvious that a serious schism has developed within the Accellera membership.

Panel members Cadence, Aldec, and Novas made it clear that they believe a more gradual "phased approach" to enacting the language is appropriate. Those companies maintain that the slower schedule is more attuned to the desires of the user community. They also argued that the method by which the language standard was donated to the IEEE - by way of a new standards working group within the IEEE, not the existing IEEE 1364 SystemVerilog committee already in place - further inhibits the appropriate roadmap for adoption.

Also on the panel, however, were the voices of Mentor and Synopsys busy crying foul against the "phased-approach" faction, and arguing that Cadence et al’s motivation for the slower timeframe is self-centered at best, inhibiting to progress at worst. Synopsys and Mentor spearhead the faction delighted with the developments announced in the Press Releases above. It can be argued that their in-house technical support for SystemVerilog is well underway and will benefit markedly from efforts on the part of IEEE to bring the donated version of the language into an IEEE-endorsed reality.

Beach Solutions has appointed Doug McCafferty as President. McCafferty was previously CEO of LEDA Systems, which was sold to QualCore Logic. McCafferty has 20+ years’ experience in the EDA and semiconductor industries, including time spent as an early stage investor in numerous technology enterprises. He began his EDA career at Valid Logic, which merged with Cadence Design Systems in 1991. He also served in a management role at Archer Systems, acquired by EPIC Design Systems and now part of Synopsys. McCafferty was an executive and an investor in Ultima, which was acquired by Celestry, now part of Cadence. Additionally, he founded Circuit Semantics. McCafferty is also the founder and managing partner of Silicon Valley Investment Group (SVIG). Clearly, the musical chairs in EDA continue.

Celoxica Holdings Ltd. announced $6.3 million in new investment from existing investors Advent Venture Partners, Cazenove Private Equity, Intel Capital and Quester Venture Capital. Celoxica says it will use the funding to push revenue growth and new product development.

CoWare Inc. announced that Brooke Seawell has joined its Board of Directors. Seawell will also lead the Board Audit Committee. Seawell is a venture partner with Technology Crossover Ventures, which he joined in 2000. Prior to TCV, Seawell spent 25 years serving in financial and operational positions at several high-tech companies - Executive Vice President at NetDynamics, which was acquired by Sun Microsystems in 1998, and a Senior Vice President and CFO at Synopsys. Additionally, Brooke was Vice President and CFO at Weitek, which he took public in 1988. In 1979, he served as Co-founder and CFO of Southwall Technologies. Brook is currently on the Board of Directors of Informatica Corporation and NVIDIA Corporation. More musical chairs.

TeraSystems, Inc. announced the appointment of Noriaki "Ken" Kikuchi as General Manager of its Nihon TeraSystems KK office in Japan. Per the Press Release: "Kikuchi-san brings more than 15 years in field operations, sales and major account management, primarily in the EDA marketplace and, most recently, was Global Account Director at Synopsys Japan. He holds a bachelor’s degree from the Department of Commercial Science, Chuo University, and will be based at the TeraSystems KK headquarters in Tokyo."

TSMC says that its CTO, Chenming Hu, will resign in July to resume his academic career at U.C. Berkeley. The Office of the CTO will be merged into the company’s R&D organization headed by Shang-Yi Chiang, Senior Vice President of Research and Development. TSMC Deputy CEO F.C. Tseng is quoted: "Dr. Hu has had a decade long association with TSMC, first as an advisor then as CTO. As TSMC CTO, he leaves a deep impact through the strategic planning and execution of our most advanced technologies and TSMC’s patent portfolio strategy and management. In addition, he established the TSMC Academy. We’re grateful for Dr. Hu’s great contributions and regret his departure."

Barcelona Design, Inc. announced several months ago the appointment of Ariel Sella as CEO and President. Previously, Sella was Executive Vice President of Products and, earlier, EVP of Marketing.

Joe Costello, Chairman of the Board of Barcelona, was quoted in the announcement of Sella’s appointment: "Ariel brings a vast and prolific range of expertise to the helm of Barcelona, stretching back to the wild days of EDA, in the mid-1980s. His experiences as an internal ‘start-up’ executive (while we were both at Cadence) and his subsequent roles in the venture capital community and dot com world give him an acute perspective on what it takes to move a company to its next level. [Meanwhile], I want to thank Thomas Heydler for transforming Barcelona from a scrappy startup with great technology and vision into a real, revenue-producing vendor with hot products based on that innovative technology. All of us at Barcelona wish Thomas the best and are sure we¹ll see him working miracles with his future endeavors."

Prior to joining Formula Ventures, Sella was co-founder of both MyWay Online and Ubique, which were acquired by America Online. He held various management positions at Cadence Design Systems, Clarity Systems, and Applicon. Sella has a BA in Computer Science from the U.C. Berkeley.

Ariel Sella and I chatted by phone several weeks before DAC. Among the things he told me during our conversation: "We are making a change at Barcelona, opening up the technology for our customers. We’re seeing this as a very exciting time for us, looking at the history of the company over the last 4 years as it developed new technologies and ways to design analog circuits without relying on Spice for design. In the past, we’ve been able to handle pretty large structures. Now with our new introductions and products, we’ll be able to proliferate the methodology and tools in the marketplace."

"If you look closely at we’re doing at Barcelona, there’s no other vendor that has equation-based synthesis. In fact, if you’re designing a high-speed PLL for instance as a clocking circuit, it may take 2 or 3 months on Spice on 3 process corners to get it to work. Using our technology, however, you can do the design on 49 process corners in just one hour. You simply can’t do that in Spice; it just takes too long. So our methodology is competing with the old methodologies. It’s really analog synthesis rather than analog Spice that we’re offering. We’re clearly out to replace Spice with our technology."

"In the past, Barcelona has provided engineers to customers for doing the work, and at times might have actually have been [perceived as] the bottleneck on a project. Now with our new announcements, we’re providing a methodology that’s thorough and methodical. Now we’re providing good tools, good solvers, optimizers and the methodology to go with them. It’s a matter of finding customers experiencing big enough pain with their designs and training them to use the solutions we can provide."

"June 14 - Synopsys, Inc., today announced that sanctions were issued against Nassda Corporation on Friday, June 11, 2004 in Synopsys' pending trade secret litigation against Nassda in Santa Clara County Superior Court."

"In a series of orders, the Court ruled conclusively that Nassda and its founders copied or derived from Synopsys' source code or other Synopsys materials all non-public portions of the first 60,000 lines of Nassda's HSIM source code, and all non-public ideas and concepts reflected in those lines of code. The Court also ruled that Nassda created a development log for HSIM after the fact in an effort to avoid liability to Synopsys, and that the Nassda defendants acted together to destroy relevant evidence."

"Under these rulings, neither the individual Nassda defendants nor Nassda itself may introduce any evidence at trial to rebut these facts."

"The Court's orders also struck the answer of Jeh-Fu Tuan, a Nassda founder and individual defendant, to Synopsys' amended complaint. Accordingly, Mr. Tuan may not contest any of Synopsys' allegations in the complaint."

"'The Court's rulings clearly establish facts which support Synopsys' position that Nassda misappropriated Synopsys' trade secrets and used Synopsys' intellectual property in developing HSIM,' said Rex S. Jackson, Synopsys vice president and general counsel. 'The Court has sent a clear message that it will not tolerate the intentional destruction of evidence.'"

"The Court's latest sanctions replace its previous orders of January 2003, which shifted the burden of proof to Nassda on several key issues. The sanctions were issued by Judge Read Ambler (Ret.), who is serving as Discovery Referee in the litigation and is a former Presiding Judge of the Santa Clara County Superior Court. Synopsys is also pursuing additional claims against Nassda alleging infringement of two of Synopsys' patents in the United States District Court for the Northern District of California."

"June 14 - Nassda Corp. today commented on the rulings and orders recently issued in California state court by the discovery referee with respect to its litigation with Synopsys, Inc."

"As Nassda reported in January 2003 and September 2003, the discovery referee previously issued orders that created certain ‘rebuttable presumptions’ in favor of Synopsys. On June 11, 2004, the discovery referee vacated the orders creating the rebuttable presumptions but issued orders against Nassda and the individual defendants in a manner that is favorable to Synopsys and not favorable to Nassda and the individual defendants."

"These orders limit Nassda’s defenses regarding the timing and the development of the initial HSIM source code and the evidence that Nassda and the remaining individual defendants can present at trial. For purposes of trial, among other things, the orders established as facts that: (i) the first 60,000 lines of source code of HSIM and all ideas and concepts reflected therein, to the extent they were not publicly known, were derived from Synopsys’ source code or other Synopsys’ materials while the individual defendants were employed by Synopsys and (ii) Nassda and the individual defendants acted in concert to intentionally alter, destroy, lose or misplace items requested in discovery and conceal evidence. These orders also struck the answer of one individual defendant, Jeh-Fu Tuan. The discovery referee denied Synopsys’ request to strike the answers of Nassda and the remaining individual defendants."

"The discovery referee granted in part and denied in part Nassda’s request to preclude Synopsys from revising and broadening substantially its alleged trade secrets that are the subject of the litigation. The discovery referee also ordered Synopsys to provide discovery to Nassda on certain of the alleged trade secrets."

"’There have been many preliminary rulings in this case, and we expect many more as the current discovery process continues,’ said Dr. Sang Wang, Chief Executive Officer. ‘Some of the rulings are favorable to us and others are not. None of these rulings, however, resolves any of the claims made by Synopsys against Nassda and the trial judge or jury will reach their own conclusions based upon the evidence presented at trial. We disagree with the discovery referee’s orders and we intend to continue to defend ourselves vigorously.’"

"’Over 250 companies and organizations world wide have adopted Nassda’s new-generation nanometer solutions,’ continued Dr. Wang. ‘The difference our customers see in the performance and capabilities of our products is due to our own innovative development. We will continue to focus on further product innovation and customer support.’"

"Nassda will post copies of the discovery referee’s orders discussed in this press release on the investor relations portion of its web site to the extent permissible under court order."