EDAC’s Numbers - The EDA Consortium’s Market Statistics Service (MSS) announced that EDA industry revenue for Q1 of 2004 was $995 million, a 6-percent increase over Q1 2003.

* Services revenue increased to $76 million, a 31-percent increase over Q1 2003.
* Semiconductor intellectual property was $78 million, a 15-percent increase over Q1 2003.
* EDA license and maintenance revenue was $840 million in Q1 2004, a 3-percent increase over Q1 2003, and 84 percent of the total reported revenue.
* Computer-aided engineering generated revenue of $470 million in Q1 2004, a 6-percent increase over Q1 2003.
* PCB and multi-chip module layout revenue was $85 million in Q1 2004, a 5-percent increase over Q1 2003.
* IC physical design and verification revenue of $285 million was down slightly from $288 million in Q1 2003.

Accellera announced that its Board of Directors has approved Accellera's Property Specification Language (PSL) standard version 1.1 as an Accellera design verification standard, and that the organization has begun the IEEE standardization process for PSL with the IEEE Corporate Advisory Group.

Per the Press Release: "The PSL 1.1 effort focused on refinement of PSL 1.01 and on alignment of syntax and semantics between PSL and SystemVerilog Assertions (SVA) where possible. In addition to correcting errata discovered in PSL 1.01, PSL 1.1 incorporates new features and user-driven enhancements that benefit EDA vendors and users alike. The PSL extensions subcommittee focused on common requests from users, including the addition of a SystemVerilog flavor, adoption of SVA built-in functions, addition of labels on directives as well as report clauses on certain directives, relaxation of some flavor macros and refinement of operator precedence."

Dennis Brophy, Accellera Chairman, is quoted: "PSL 1.1 supports the new age of design verification. Effectively, it takes the electronics industry into the era of assertion-based verification, a powerful means for increased confidence in the correctness of a chip or system design prior to fabrication."

Cadence Design Systems, Inc. announced that President and CEO Michael Fister has been elected to the Cadence Board of Directors. Fister was named President and CEO of Cadence in May 2004. Prior to joining Cadence, Fister spent 17 years at Intel Corp., where he was most recently senior vice president and general manager of the company's Enterprise Platforms Group. Fister has a BSEE and MSEE from the University of Cincinnati.

Esterel Technologies announced the selection of Chip Downing as CEO for Esterel Technologies, Inc., the U.S. arm of Esterel Technologies, and Vice-President of Embedded Market Operations. Most recently, Downing served as Vice President of Business Development at Validated Software Corp.

Sequence Design announced that Jerry Frenkil has been promoted to CTO. Most recently, Frenkil served as Sequence's Vice President of Advanced Development. Per the Press Release: "Mr. Frenkil's tenure with Sequence began when the company merged with Sente in 2000. He was one of the founders of Sente, the pioneer in low-power design tools. He has published papers on IC and low power design, and holds several patents on circuit design and design automation."

Frenkil has 25+ years of experience in the semiconductor and EDA industries. Prior to co-founding Sente, Frenkil was an independent consultant focused on IC design. He also held management positions at VLSI Technology and Mostek. Frenkil has a BSEE from the University of Texas.

Carbon Design Systems announced it has joined the 0-In Design Automation's Check-In Partner Program. The companies say that the assertion synthesis capability of 0-In's Archer Verification System when coupled with Carbon's DesignPlayer engine will provide design bug identification without sacrificing runtime performance.

Applied Wave Research, Inc. (AWR) announced that its Analog Office design suite has been selected for the prestigious 2004 LSI of the Year Award in the Design Environment/Development Tools category against 150 other nominations. The Award is sponsored by Semiconductor Industry News and Reed Exhibitions Japan, the awards were announced at the annual Embedded System Expo & Conference in Tokyo in July. James Spoto, AWR president and CEO, is quoted: "Being selected by such a prestigious committee of world renowned professors from leading Japanese universities lends special significance to this award. It is continued validation of the growth of the high-frequency design community in Japan and strong demand for AWR products in the region."

EMA Design Automation announced the formation of the EMA Consulting Services Group to "make available high quality, enterprise-wide OrCAD Capture CIS implementations. Key factors are library data management and interfaces into the customer’s MRP system to leverage items such as cost information, parts availability, and preferred part lists. The EMA Consulting Services Group also provides web-based CIS deployments."

Alan Diamond, Manager of the EMA Consulting Services Group, is quoted: "EMA can provide very high value strategic services at costs our customer base will welcome. It allows the smaller customer to realize high leverage processes, like their larger competitors, but with significantly less overhead."

Fujitsu Ltd. and Cadence Design Systems announced a partnership agreement - a Premier Design Partner agreement - under which the companies say they will create "advanced" SoC design environments. The agreement is being described as "revolutionary" in the Press Release for the following reasons:

"It provides design solutions that go beyond a simple sales agreement for EDA tools. The agreement encompasses tens of thousands of Cadence licenses, including numerous SoC Encounter licenses. The worldwide Fujitsu Group and all of its design centers will have access to licenses covered by this agreement. In addition to its standard support, Cadence will provide personnel support organizationally to the worldwide Fujitsu Group and its design centers in order to fully leverage this agreement. As strategic business partners, Fujitsu and Cadence will jointly develop methodologies that merge design and process technologies, and plan to expand their global business collaboration to markets such as in the U.S. and China. Under this agreement, Fujitsu will deploy to all of its design centers the combination of a variety of licenses and a new design methodology known as physical prototyping (also referred to as silicon virtual prototyping) for SoC development for 0.13-micron technology and beyond."

[Editor's Note: If this isn't revolutionary, what is?]

Kilopass Technology, Inc. announced that Global UniChip Corp. (UniChip) has signed a corporate agreement to add Kilopass' embedded non-volatile memory (NVM) technology, XPM, to UniChip's IP portfolio. In addition, UniChip says it has joined Kilopass Technology's Design Services partner program.

Jack Peng, Founder, President and CEO of Kilopass Technology, is quoted: "We are delighted to establish this partnership with UniChip. UniChip has a strong team of industry veterans with the necessary experience and capabilities customer seek in SOC design service providers. They will help accelerate the adoption of our XPM technology into designs created for high volume products."