** Synopsys, Inc. announced that the FTC has requested additional information and documentary material in connection with its review of Synopsys' proposed acquisition of Nassda Corp. Not surprisingly, Synopsys says it will promptly respond to the FTC request. It's important to note that this FTC request extends the waiting period under the Hart-Scott-Rodino Antitrust Improvements Act of 1976. Synopsys announced on December 1, 2004 that Synopsys and Nassda had entered into a merger agreement for the acquisition of Nassda by Synopsys in an all cash transaction at $7.00 per share and, subject to the closing of the acquisition, to settle all outstanding litigation by Synopsys against Nassda and certain Nassda officers, directors and employees.

** Meanwhile, Nassda Corp. also announced that the FTC has requested additional information and documentary material in connection with its review of the proposed merger between Nassda and a subsidiary of Synopsys.

** Nassda Corp. announced financial results for the quarter ended December 31, 2004, the first quarter of Nassda's fiscal 2005. Revenue for the quarter ended December 31, 2004 was $11.3 million, an increase of 16% from $9.7 million for the quarter ended December 31, 2003 and an increase of 2% from $11.0 million for the quarter ended September 30, 2004. Net income for the quarter ended December 31, 2004 was $1.3 million, or $0.05 per diluted share, an increase of 135% from $572,000, or $0.02 per diluted share, for the quarter ended December 31, 2003 and an increase of $68.6 million from a net loss of $(67.3) million, or $(2.50) per diluted share, for the quarter ended September 30, 2004. Operating expenses for the first quarter of fiscal 2005 were lower than expected, primarily due to lower litigation costs. As a result, Nassda says it was able to achieve an operating margin of 14% for the quarter ended December 31, 2004.

** Mentor Graphics Corp. announced that its fourth quarter 2004 bookings and revenues had achieved "record levels," with revenues expected to exceed Thomson First Call consensus estimates of $204 million. Bookings for the fourth quarter were up about 40%, year over year. The company also grew backlog, up approximately 35% from the fourth quarter of 2003. Fourth quarter special charges are expected to result in GAAP basis earnings below guidance. Earnings per share on a pro forma basis are expected to modestly exceed consensus estimates. The company says that fourth quarter bookings performance was broad-based across all regions and product lines, and not driven by any particular large transactions. Bookings in North America were up 15%, Europe was up 50%, and Japan and the Pacific Rim were both up over 100% over the fourth quarter of 2003. Nice.

** The New Kids on the Block **

** Calypto Design Systems, Inc. announced its arrival on the EDA stage and articulated the company's strategy for "bridging the gap between electronic system level design and IC implementation." The company says it intends to "broadly deploy EDA products based on unique, proprietary technology that will connect system-level models and RTL design flows in order to support faster verification times and design at a higher level of sequential abstraction … The company intends to commence its first broad scale product release in second quarter of 2005."

The company was founded in 2002 and, to date, says it has raised $22+ million in Series A and Series B funding from firms including: Infineon Ventures, JAFCO Ventures, Tallwood Venture Capital, and Walden International. The company has Board of outside directors including George Pavlov, General Partner of Tallwood Venture Capital, Lip-Bu Tan, Chairman of Walden International, and Albert Yu, former Intel SVP and Private Investor.

Mahesh Balakrishnan, Managing Director of Infineon Ventures N.A, is quoted in the Press Release: "Today, the process of ensuring that a complex chip design will match its functional system requirements is among the most time-consuming, expensive, and fallible processes that chip design teams go through. Calypto has a unique grasp on the issues and challenges that design teams are wrestling with. We made the investment in them because we believe that they have the vision, team, and technology to address these challenges."

Calypto Design has also named the senior management team. Devadas Varma is CEO. Michael Sanie is Vice President of Marketing and Business Development. Larry Lapides is Vice President of Sales. Gagan Hasteer is Vice President of Engineering. Anmol Mathur is Chief Architect.

Devadas Varma is a former Cadence fellow, and previously held CTO and senior engineering positions at Ambit, Viewlogic, and Mentor Graphics. Michael Sanie was Group Director of Industry Initiatives at Cadence and Director of Marketing and Business Development for IC Design at Numerical Technologies. He has also held marketing and technical positions at Actel, Compass Design Automation and VLSI Technologies. Larry Lapides was Vice President of Sales at Verisity. Prior to Verisity, he was busy building sales teams for Surefire Verification and Exemplar Logic. Gagan Hasteer was Director of Engineering for Innologic System prior to their acquisition by Synopsys. Anmol Mathur was the architect of the Cadence datapath synthesis engine and served on a tools development team at the MIPS division of SGI.

The Press Release explains the new company by outlining current issues in verification: "A complex IC today contains more than one million lines of RTL code that must be verified against functional requirements. This code is constantly changing through the design process as designers target aggressive power consumption and timing constraints, and must be re-verified through these multiple iterations. This functional verification is consuming up to 75% of total design time and resources. Yet, an estimated 45% of all design starts require multi-million dollar silicon re-spins because of undetected functional bugs. The fastest way to find functional errors and verify system requirements is to design and verify at a higher level of abstraction."

"Regardless of whether design teams have already adopted a system-level design flow, the teams are already moving up in abstractions. To meet power or timing goals, design teams make micro-architectural refinements (such as retiming, pipelining, state re-encoding and resource sharing) to their designs. These refinements change the sequential nature of the original designs, and thereby move up in a sequential level of abstraction from a pure RTL level."

"These changes have not been well-supported by a standard EDA design flow. There has been no easy way for design teams to know which sequential changes to make, to know how to perform and automate these changes, and most importantly – no easy way for design teams to ensure functional equivalency as they make these sequential changes."

Devadas Varma, CEO of Calypto, gets the last word: "Today, design and verification teams must make a leap of faith when they move to a higher level of design abstraction – or when they move from system-level verification models to RTL. The semiconductor industry has a growing need for EDA solutions that will simplify the design flow while enabling designers to move to higher levels of sequential abstraction. There has been no good, automated connection that allows design and verification teams to move between different levels of sequential abstraction. Our technology solves this problem."

Surely the following news should have had top billing here, but by the time of this posting on January 18th – all of the major analysts have chimed in on this news, and ESNUG's John Cooley has heard back from over 100 of his close and personal friends regarding these developments. What more is there to say except …

** Cadence Design Systems, Inc. announced January 12th that the company has signed a definitive agreement to acquire Verisity Ltd. The companies say that when the acquisition process is complete, Moshe Gavrielov, currently CEO of Verisity, will join the Cadence executive management team, and Yoav Hollander, who is Founder and CTO at Verisity, will "play an integral role in setting Cadence's verification technology direction."

The terms of the agreement are such that Cadence will acquire Verisity in an all-cash transaction. Verisity stockholders will receive $12 in cash in exchange for each outstanding share of Verisity stock, upon closing of the acquisition. The entire deal, of course, is subject to the customary shareholder and government approvals. Probably a safe bet at this point that the approvals will be forthcoming.

Mike Fister, President and CEO at Cadence, is quoted in the Press Release: "The global electronics industry is under unprecedented pressure to develop and bring to market innovative products as quickly as possible. Our acquisition of this highly innovative team and successful business is consistent with Cadence's focus on enabling the world's leading electronics companies to address the demand for increasingly complex systems."

Moshe Gavrielov of Verisity is also quoted: "Customers are demanding solutions that automate the entire verification process and make it more predictable from planning to closure. This requires the integration of our VPA solution with a unified verification infrastructure. The combination of the two companies will greatly accelerate the delivery of these integrated solutions."

** Jasper Design Automation announced, also on January 12th, that the company has acquired Safelogic. The terms of the transaction were not disclosed.

The companies say, "The acquisition brings together technology leaders in complementary areas within the formal verification market, creating a combined company with the EDA industry’s strongest solution for verification and debugging of block-level designs using assertions and high-level requirements. Safelogic brings to Jasper one of the world’s fastest formal proof engines. When integrated with Jasper’s unique Precognitive engine, which automatically determines which parts of a design are relevant for a particular proof, this solution will give users the highest performing formal proof solution. The merged company has one of the formal industry’s strongest engineering teams, with development sites in Mountain View, Calif., Berkeley, Calif., and Göteborg, Sweden."

The merged company will continue to operate under the Jasper Design Automation brand and will be based in Mountain View, CA. Pär-Jörgen Pärson has joined the Jasper board of directors, and Jonas Risberg, a Safelogic board member, will participate on Jasper’s board as a board observer. All Safelogic employees became employees of Jasper Design Automation in December 2004, when the transaction closed. Safelogic was originally founded in 1999.

Harry Foster, chairman of the IEEE-1850 PSL Committee and chief methodologist at Jasper Design Automation, is quoted in the Press Release: "Safelogic is widely recognized as having made a major contribution to the development of the PSL standard, particularly as it relates to formal proof. In contrast to the many rudimentary and incomplete implementations out there, Safelogic has the most comprehensive support of PSL in the formal industry. This, combined with Jasper’s support of Verilog-based requirements and commitment to SystemVerilog Assertions, puts the combined company at the forefront of assertion language support."

** New Business Cards **

** Meanwhile, Jasper Design Automation also announced that it has formed a Technical Advisory Board (TAB) made up of technologists from the academia working in the field of formal verification. Jasper says the TAB will advise the company’s management team on academic research trends in formal verification, provide guidance on Jasper’s technical product development, and educate students on the commercial trends in formal verification. Initial members of the TAB include Alan Hu, Associate Head of the Department of Computer Science at the University of British Columbia; Sharad Malik, Professor in the Department of Electrical Engineering at Princeton University, and Chair of DAC 2004; Satoshi Goto, Professor at the Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, Japan; and Claudionor Coelho, Associate Professor at the Federal University of Minas Gerais, Belo Horizonte, Brazil. Jasper should be proud of this pretty heavy-duty crew!

** Atrenta Inc. announced that Charles Schadewitz has been named as Vice President of Worldwide Sales. He will report to Chairman, President and CEO Ajoy Bose. Prior to Atrenta, Schadewitz served as Vice President of Sales at Cadence Design Systems. He came to Cadence after serving in a similar role at Simplex Solutions. Schadewitz has a BSMA from U.C. Berkeley.

Additionally, Atrenta announced that John Rizzo has joined to the company and will report to the Vice President of Marketing. Previously, Rizzo was at Intel, Oracle, Informative, and Apple Computer. He has a BSEE from Stanford. Simon Young has been hired at Atrenta, reporting to John Rizzo. Previously, Young was at Nassda, Synopsys, Silicon Metrics, Mentor Graphics, Intel and TI. Simon Young has a MSEE from Imperial College in London. And finally, Alan Feinberg also joins Atrenta as senior business unit director, having served most recently as vice president of marketing and North American sales at Monterey Design Systems. Before starting his own consulting business, Tekstart, Feinberg had several director-level sales and sales operations roles at Synopsys. Feinberg has a BSEE from the University of Rochester and in MBA from Northeastern University.

** Applied Wave Research, Inc. (AWR) announced that it is "teaming with Rohde & Schwarz." The companies say that the partnership will produce test solutions that include Rohde & Schwarz test and measurements instruments along with AWR software.

Chris Paris, Director of European Operations for AWR, is quoted in the Press Release: "AWR’s TestWave software used in conjunction with the new Rohde & Schwarz high-performance vector network analyzer, ZVB, provides design engineers with the ability to gather measured data and use that data in conjunction with our circuit simulation tools in Microwave Office design suite. This enables designers to investigate such phenomena as heating effects in transistors and their effect on overall circuit performance. At the system level, AWR’s Visual System Simulator 2004 (VSS2004) software links directly with Rohde & Schwarz’ industry-leading, digital signal generators and vector signal analyzers, enabling schematic simulation, test signal generation, and dynamic data gathering so that wireless system designers can perform trade-off studies with hardware-in-the-loop."

** Eagleware Corp. announced today that the company name has changed to Eagleware-Elanix Corp. to reflect Eagleware's recent acquisition of Elanix, Inc., an ESL design tool provider. In addition, the company announced a new version of SystemView, SystemView by Elanix 2005, with library support for the emerging Ultra-Wideband (UWB) IEEE standards.

Eagleware-Elanix CEO, Todd Cutler, is quoted in the Press Release: "We changed our name to emphasize the strengths of our combined companies. Our new version of SystemView addresses our goal to expand our customers' design options for improving power, speed and accuracy with design software that models the behavior and performance of new communications standards."

Think you've got a handle on the latest in acronyms? Read on …

Eagleware-Elanix says that SystemView 2005 supports "both candidate standards for Ultra-Wideband communications-Multi-band Orthogonal Frequency Division Multiplexing (MB-OFDM) and Direct Sequence Ultra-Wideband (DS-UWB). With the new libraries, SystemView users can build the physical layer from transmit to receive with channel model interference. Support for Common Signaling Mode (CSM) is integrated within the libraries, as well as support for the standard preambles. Developers can design either MB-OFDM or DS-UWB or evaluate both standards within a single system."

Frank Vincze, Systems Design Product Manager at Eagleware-Elanix, is quoted: "UWB design is one of the fastest growing application areas in our customer base. These new UWB libraries are being added in response to overwhelming customer demand. By supporting both of the candidate standards, we are helping our customers protect their design investments, regardless of the eventual selection."

** Giga Scale Integration Corp. (Giga Scale IC) announced that its chip estimation tool, InCyte, has been named a finalist by the IEC for a DesignVision Award in the ASIC and IC Design Tools category of the first annual IEC DesignVision Award program. Winners of the award, which organizers say honors achievement in electronic design innovation, will be announced at DesignCon on February 1st.