Episode VII:
DFM Strikes Back

by Peggy Aycinena

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Editor's Note: This is the fourth in a 4-part series on design issues.

This final episode is as attempt to add (yet more) content to the current discussion underway (raging) in and around the EDA space regarding Design for Manufacturing.

In Episode IV, a panel discussion at ICCAD 2004 proposed some conflicting agendas:

* The move to deeper and deeper submicron may be a but obsessive considering that it is harder and harder to manufacture reliable and high-yield products. Perhaps the design industry should slow down and harvest the performance and functionality available in the current process technologies.

* Alternatively, it is finally time for designers to be working to satisfy both functionality and manufacturing requirements, not just the functionality. That's because the move to DSM is happening and nobody's going to stop it – and why should they?

* IDMs may prove to be the only venue within which successful moves to the smaller geometries can be achieved, given that is requires such an intensely integrated design and manufacturing team to prevail over the intense physical affects that can no longer be ignored of deep-submicron on-chip structures.

* Alternatively, the tools for DSM design need to be out-sourced to third party vendors more than ever because IDMs cannot afford to throw the necessary levels of resources at tool development and support now that those tools must be so incredibly sophisticated and nimble. However, if that doesn’t happen – the EDA industry will die.

Clearly, Episode IV indicated there is a lot of controversy about the move to smaller nodes and how to deal with the consequences.

Episode V highlighted the transient affects that can occur in chips even after they are manufactured and deployed in the field. These affects become more problematic when the products are deployed in critical mission settings – and, again, when the on-chip device geometries are very small.

In addition, in Episode V technologist laid out some of the specific problems associated with the move to deep-submicon design. There are systematic and random variations that occur in chips during manufacturing, and the affects of these variations are magnified at small process geometries. There's no avoiding that fact that the variations occur. How to repair the damage once it's done – or more importantly, to predict and minimize the variations in the first place – is the challenge facing designers and those who provide the tools they use in their work.

Finally, in Episode VI, there was a discussion about ways in which the yield and failure predictions can be made and utilized. Those predictions requires a great deal of cooperation from the foundries to produce and process the statistical data upon which they are made – and then, an equal amount of cooperation from both the tools vendors and the tool users to utilize and capitalize on the ability to make those predictions.

And now we come to Episode VII, and the final question:

Can DFM Come to the Rescue?

Can Design for Manufacturing tools, methodologies, solutions, strategies, consultants, companies, and fundamental philosophies solve the multiple, complex technical challenges to support the move to smaller geometries, to insure that yields cease to decline, and to guarantee that tool providers and their customers – both the designers and the manufacturers – can stay competitive in an environment of harsh and relenting time-to-market pressures?

Well if DFM can't come to the rescue, it won't be for want of trying, because these days it seems that every keynote, panel, technical presentation, and new company launch is based on piecing together some part of the DFM puzzle. If you think DFM only exists in the minds of academics and visionaries, think again.

DFM – whatever that means and however that's implemented – is here. People are talking about it everywhere. Technologies are studying it, tool vendors are touting it – dozens of new start-ups are being funded based on the 'reality' of the thing – and manufacturers are stumping for it. The only ones who seem to be late to the party are the designers. They're apparently dreading it.

The move to DFM seems to portend the need for yet more tools for these long suffering people, tools that will predict, tweak, optimize, iterate, optimize again, and then predict, tweak, optimize, iterative, optimize yet again (based on a variety of prediction models, device characterizations, and design rules) to try to maximize the manufacturability and minimize the yield problems of the design the designers working on once it reaches the fab and the field beyond.

These reluctant DFM converts notwithstanding, it would seem we're quickly moving into the Golden Epoch of Design for Manufacturability and Design for Yield. If things go well, Moore's Law will be honored yet again, and 90 and 65-nanometer designs will be celebrated just as their larger counterparts were in earlier epochs.

Of course, that's the future. Getting between here and there is the quest. Getting there first is the victory.

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The Mentor Graphics User2User Conference took place the last week of April at the Marriott Hotel in Santa Clara, CA. There was a very large attendance at the conference, and although the majority of the people there appeared to be board designers, they listened with interest to the opening keynote addresses that covered topics such as verification, design for manufacturing, and system-level design.

It's not that these topics aren't important to board designers – because they are – but there's often a different spin on the subjects when the device under development is a board rather than an IC. In any case, one of keynote addresses on the opening morning of the conference was given by Anthony Nicoli, Mentor's Director of Marketing for the Calibre Physical Verification and Extraction Design to Silicon Division.

(Nicoli has a BSEE/MSEE from MIT, and an MBA from Northeastern. Only worth mentioning for those reluctant to listen respectfully to someone in marketing.)

Nicoli cataloged the history and the issues surrounding DFM. He pointed out that in 1995, yields were at approximately 90 percent for devices built in the range of 500 nanometers (0.5 micron). By 2002 at 180 nanometers, the yields had dropped to approximately 50 percent and have definitely not improved with the move to 130 and 90 nanometers. He said the yield problems are characterized by random variation due to particle interactions, systematic variations due to manufacturing process interactions and parametric variations due to performance interactions. The latter two, Nicoli said, are the ones of greatest concern.

Per Nicoli, parametric variations such as resistive and capacitive effects are dominating at 90 nanometers. The move from aluminum to copper interconnects provided better on-chip connectivity, but at a cost as the copper is contributing to greater interconnect parasitics. In addition, planarity fills are adding capacitive affects to the mix, along with a host of other affects, which now need to be accounted for at 90 nanometers and below. The good news, Nicoli said, is that the tools currently available on the market are helping to control the respins that are being precipitated by all of this. The bad news, he said, is that there's an intense need for much more accurate electrical simulation models for on-chip circuitry on this scale.

Manufacturing variations are competing for attention with these parametric affects. Nicoli said that it's pretty clear that the design tool industry has not caught up with the information that's available from the fabrication process. There's not yet an efficient way to prioritize that information and help engineers know how to reflect that information in their design choices.

Things happen during manufacturing and deployment, and at 90 nanometers and below, they can not be ignored. Nicoli said the design rules that point to better yield and performance must be refined, and compliance more rigorously encouraged. He sympathized with the layout engineer who are already needing to minimize the size of their designs, make it work while meet the timing specifications, and having to run more and more physical verification checks on the design – and fix the errors – all while meeting the development schedule that been laid out and enforced by management.

Nicoli was not painting a particularly rosy picture, and it's hard not to conclude that perhaps the move to smaller geometries is not warranted. It seems like somebody ought to tell the foundries to stop and either let folks catch up, or stop and just leave well enough alone. (Would that be 180 nanometers? 90 nanometers? Probably depends on who you talk to.)

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On Tuesday, April 24th, TSMC announced its move to 65 nanometers.

"TSMC unveiled its newest semiconductor manufacturing process today at a Technology Symposium. First wafers are expected in December 2005. The new 65-nanometer Nexsys Technology for SoC Design allows designers to build logic devices with double the density of the company's industry leading 90nm technology. This massive integration – the equivalent of more than 750 billion transistors on a single 12-inch wafer – enables significant cost savings to market movers across the IC industry."

"Benefits of TSMC's new process technology include a standard cell gate density twice that of TSMC's 90-nanometer Nexsys process; a 6T SRAM cell size of less than 0.5um2 (half that of its 90-nanometer counterpart); and a 1T memory cell size that is a 65 percent smaller than the 90-nanometer memory cell. The 65-nanometer Nexsys technology features an aggressive gate oxide thickness to further enhance transistor performance."

"From a power and performance perspective, the 65-nanometer Nexsys technology leads the industry with a 50 percent speed gain (TSMC's 65-nanometer General Purpose process versus its 90-nanometer General Purpose process); and a 20 percent standby power reduction. High-speed 65-nanometer versions are expected to lead the industry in power/performance tradeoffs."

"In response to customer demand, TSMC's first 65-nanometer Nexsys technology, which will enter first production in December 2005, is optimized for low power. A high-speed version will be available in 2006, followed later in the year by a general-purpose 65-nanometer process. A version employing SOI technology and an ultra-high-speed version will be introduced in 2007. Logic and mixed-signal options are slated for all versions, with embedded memory available in each.

"TSMC's first 65-nanometer silicon was a fully functional SRAM that featured more than 100 million transistors and was validated in April 2004. Since then, some customers including Altera Corp. and others, have taped out and received functional prototypes of their own designs, including logic and memory, for initial validation and benchmarking. Engineers at multiple companies are designing to the process, and tapeouts of production devices are expected to reach TSMC in the second half of 2005."

"Early design rules and SPICE models for the new technology have been developed. TSMC libraries will be available in the fourth quarter of 2005, and third party library and IP developers are fast at work developing additional offerings. TSMC's 65-nanometer Nexsys process is supported by Reference Flow 5.0 and will receive additional support as future iterations of the industry-leading design flow are developed. Process and design tools available to engineers are outlined in power and leakage management and design for manufacturing (DFM) guidelines."

"The new technology features a minimum number of process changes, such as strained silicon and a new nickel silicide, to shorten time to volume. The 65-nanometer Nexsys technology is the third-generation TSMC process to employ low-k dielectrics and the fourth generation to use copper interconnects."

"The 65-nanometer process may be the first-generation process to use immersion lithography techniques, developed in partnership between TSMC and ASM Lithography. A leading proponent of immersion techniques, TSMC took delivery of the first production-worthy 193-nanometer immersion lithography system in 2004. Capable of 132nm wavelengths, the 193nm immersion system also provides a greater than 200 percent depth-of-field improvement versus dry lithography systems. The new 65-nanometer process will be implemented in TSMC's industry-leading 300mm manufacturing facilities, Fab 12 and Fab 14."

Et fini.

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Lunch was served to approximately 25 journalists and analysts at the TSMC Forum at the San Jose Convention Center. The presentation was a Q&A format, and three executives from TSMC – Deputy CEO F.C. Tseng, Senior VP of Worldwide Sales & Services Kenneth Kin, and Senior VP for R&D Shang-Yi Chiang – fielded questions from a table up front.

Questions from the journalists ranged across topics:

* Does everybody need 65 nanometers?

* How will it ramp?

* Do you have a two-pronged development strategy? One for early adopters and one for mainline customers?

* Will there be a premium charged to the customers on this next technology node?

* Will fees be based on wafer counts or good die produced?

* Are foundries starting to invest in the fabless side of the market?

* Where will you locate future fabs? China? India? Are talent and labor markets considerations in the decision?

The answers were given out carefully. The journalist were subdued. The atmosphere was not tense – but it wasn't a party either. The fellows from the foundry were in control. The journalists were marginalized. The questions were irrelevant. The answers were predictable. No information, other than a nuance or two, was revealed above and beyond what was in the press release.

The move to 65 nanometers is here. End of story. Deal with it.

We'll help you work to use it. So pay the fees and move on.

It's expensive and will probably have some yield issues for sometime to come, but early adopters will deal with it, while also taking advantage of the volume/price trade-offs. Mature customers will come around eventually.

Sitting in the back and watching the Q&A for 45 minutes, it was hard not to feel defeated. Here I had constructed a careful set of articles building to the conclusion that as the tool vendors and their technologists would slowly produced the "solutions" needed to facilitate the move to ultra deep-submicron design. But the foundries didn't wait.

The foundries are moving on into ultra DSM, they'll solve the problems as they arise, and they will let us know when the solutions are available. And, they will decide on what timetable information about device characterization and statistical predictive data will be made available. And not surprisingly, will be their timetable.

The single most important – and only – answer I came away with after attending the TSMC press lunch was that the foundries answer to no man. Forget all of the keynotes, panel discussion, and technical sessions. The start-ups, the buzz, the second and third rounds of funding. The toys, give-aways, press announcement, etc. The foundries are not waiting for small players and venture capitalists to decide when the "industry" is really up and running in DFM. DFM is not coming to the rescue, striking back, or emerging in a random walk sort of way.

It's already happening. It's already happened.

Step up to the bar and order a drink. If you're lucky they'll put an extra ice cube in there, and an extra shot as well, to dull the pain.

Et fini.

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May 2, 2005

Peggy Aycinena owns and operates EDA Confidential. She can be reached at peggy@aycinena.com

Copyright (c) 2005, Peggy Aycinena. All rights reserved.