Episode VI:
DFY & The Jedi Knight

by Peggy Aycinena

John Kibarian is tantamount to a celebrity these days. Every time you turn around or go to a technical conference, John is on the program – either as a panelist, as a keynote speaker, or as a participant in the technical sessions.

Why is John Kibarian so popular these days and what is it that he's saying that everybody wants to hear from him? Hopefully this article will answer those questions. You'll see why this intense and intellectual technologist is indeed a Jedi Knight.

John Kibarian is founder and CEO of PDF Solutions, Inc.

PDF Solutions has been in existence for 12 years at this point, but the last several years have been particularly interesting for the company. PDF is about yield, including Design for Yield – a concept that along with Design for Manufacturing has come into its own with the move to 90-nanometer device geometries and below. Everybody's talking about the concepts of DFY and DFM these days.

Lots of people in lots of different venues are busy suggesting what should be done, and many new companies and initiatives are emerging in and around all of that effort. What's really remarkable, however, is how often PDF Solutions comes up in those discussions in all of those different venues, which of course why John is so popular.

IEEE's ISSCC, for instance, was held in mid-February at the Marriott Hotel in San Francisco. This is a scientific conference with an emphasis on R&D rather than on marketing and product positioning. The fact that John Kibarian was chosen as a speaker during one of the technical sessions at ISSCC is a reflection of the science and engineering that is at the heart of what PDF Solutions is doing.

I attended Kibarian's talk at ISSCC along with approximately 400 others. Several days later, I had a chance to talk by phone with John, at which time he was able to answer a number of the questions that I had based on hearing his talk.

Before you see his responses, I'm going to summarize my understanding of the technology behind John's company.

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PDF Solutions has proprietary process and design simulation and analysis software, test chips, methodologies, and services that can help predict and improve manufacturing results before product ramp. PDF’s customers are IDMs, fabless semiconductor companies and foundries.

For designers, PDF is relevant because through its pDfx technology, PDF allows them to build process-awareness into their designs up-front to impact yield and manufacturability. How it works is that PDF produces test chips that it submits to the foundries. These test chips have a structured experiment across a layout feature set called a layout "design of experiments" (DOE) that forms a basic set of yield microstructures for any design in a target technology. Such a DOE is supplied for all critical features including transistors, contacts, vias, and metal lines.

Data is collected as to the statistical occurrence of failures in these microstructures versus the process variability that might come into play during the manufacturing process. That data is used to calibrate PDF’s yield simulator, YRS. YRS is used to score the manufacturability of IP blocks just like SPICE is used to score the electrical performance of those blocks. Those scores are made available to designers by way of EDA tool vendors’ synthesis, place and route (SP&R) systems. In their SP&R tool of choice, the designer can optimize his design for manufacturability at the same time he is optimizing for timing, power, and functionality.

There is no cost to the EDA vendor or the EDA tool users. The only cost is to the foundries who are paying to run PDF’s characterization vehicle test chips. PDF is not an EDA tool provider. It's a blend of a DFM and a DFY facilitator. The foundries are becoming increasingly dependent on this type of data pipelining so as to give the designers as much assistance as possible in producing manufacturable designs.

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Kibarian – Hugo de Man gave one of the opening keynotes at ISSCC. His comment was that we may be in the midst of a software paradise, but on the hardware side, we’re in "Nano Hell" because of all the production issues we have to deal with. Yield loss, signal integrity, etc – these are all things that make 65 nanometers and 45 nanometers so difficult for volume production. Nano Hell is just a catchy way of referring to the manufacturing problems in hardware today.

Proactive DFM is putting DFM before verification. You go through logic, timing verification, logic verification, and printability verification. This is where a lot of people then put DFM. But at that point it’s too late. When we define DFM, we mean addressing manufacturability during technology mapping and physical design. That means before verification. Hence you are not creating additional iterations to close the design.

If you are implementing DFM after the design is complete, at the DRC or chip finishing stage and you're telling a designer that they can get five yield points for making a change to the layout, they may not think it's worth the effort to work toward those improvements because they could risk the tapeout date. But if we make it earlier and straightforward for them to incorporate good manufacturability when they create the layout in the first place, and it doesn't create any overhead for them – we are moving toward proactive DFM. We think that's what everybody really wants to do these days.

Our belief is that these changes must be made in the design IP and in the EDA systems to eliminate overhead and minimize complexity for the IC designer. Of course, the real technical hang up has always been availability of yield models and simulation early in the flow to make the results meaningful—how to get really accurate data early in the flow and use it in an intelligent way. This is the problem that PDF has solved for the industry.

We track 3 metrics of success:

* What is the design block's sensitivity to random yield loss mechanisms?

* How sensitive is the design block to process variations and systematic mechanisms?

* How much performance variability is this design block sensitive to as the process printing window varies?

We score IP on these three metrics and continue to update these metrics as the process matures. In that way, every new design can take full advantage of the process capability and the most effective DFM corrections can be applied at tapeout. So while we do continuously update the process characterization, we would not anticipate a re-spin for these DFM modifications, having done right at the time of tapeout for each new design.

When people think of feedback loop for yield, traditionally that has meant design the chip, build it, measure it, identify how to improve it, and revise it. That just isn’t practical any more because of short market windows and high costs associated with that loop. However, feedback about what layouts work in manufacturing is critical for nanometer technologies. So what we are doing is running our CV test chips as the basis for our models, and from that point on, the feedback loop can be in the SP&R flow.

What makes this feedback loop possible is our patented layout-process characterization and yield simulation technology. As I said earlier, our test chips contain a layout DOE that forms a basic set of yield microstructures for any design in a target technology. We then extract layout attribute dependent yield models from these test chips. Our yield simulator then analyzes a design to account for the usage of each of these yield microstructures that finally rolls up into an overall chip yield. It’s this simulated yield information that is passed on to the synthesis systems so that yield can now become part of the synthesis objective function.

So, now we get back to your original question. By continuously updating our characterization of the process capability, and by updating our yield models from technology node to technology node to account for new yield mechanisms in advanced processes, we are providing a feedback loop for DFM.

There are IEEE standards bodies on a variety of topics. But there is no IEEE standards body that is creating definitions for design for XXX. Everybody seems to have his or her own taxonomy about what DFM and DFY really are. So the fact is that manufacturability means different things to different folks.

I have an anecdote that brings this point home. One of our DFM customers in 2000 had two product lines. One was a cell phone. For that, they were running 10,000 wafer starts a month and the factory was going to figure out how to center the process for that design. So the designers cared about maximizing the defect limited yield, i.e. the product’s robustness against uncontrollable particles. This is design for yield. Variance doesn’t matter. You just want as high yield as possible.

The other product line was a network-processing unit. Big two square centimeter chips at two lots per month. If the yield is 50% some months, 20% some months, and again 50% the following month, they’ve got a problem. The volume is so low that the factory is never going to get the process centered for this design, but the designers would rather have a consistent 40% yield every time than an average yield of 50% with high variability. They want consistent yield and reduced variability. These guys were much more concerned about the design’s sensitivity to process drift and variation. So for them, sensitivity to systematics and process excursions had to be very good.

These were two designs, both running on the same process, same fab, same standard cell IP, but very different manufacturability goals.

So in our taxonomy, DFM means I've designed the chip that runs through manufacturing the way that works best for my product.

Since our solution lets the designer specify their manufacturability objective more broadly than just defect limited yield, you can call us a DFM supplier. However, I think "tool vendor" is the term that might be more difficult to put on us.

One of our first tools was a yield simulator in 1996. It took inspection data and would predict yield. But the numbers we came up with were really inaccurate. We realized that inspection data is really best used for production control, not for calibrating DFM models.

So we determined that we needed to be in the test chip business and we started providing test chips to the manufacturers for use in optimizing manufacturing recipes. A side benefit was to calibrate the yield models for DFM. What evolved is that our business became selling solutions—called yield ramp infrastructures—to improve yield. Included in those solutions are a variety of tools and services and test chips addressing a variety of manufacturing issues.

It’s probably more DFM than DFY, but once you’re in the factory, a point software application alone is not enough. At some point we have needed test chips, a custom tester, yield modeling software, a YMS (yield management software) system, and an extensive set of methods to apply a broad set of technology in a way that is consistent with customers’ existing tools and methods. In short, when your business is yield improvement, the scope is broad and most existing labels don’t fit well.

We actually are in the business of selling both products and services. Primarily what our customers are buying is yield acceleration, but this comes in the form of process and design simulation and analysis software, test chips, methodologies, and services that can help predict and improve manufacturing results before product ramp. We've got customers wherever there are fabs – in Europe, the U.S., and Asia.

The cost in engineering time and silicon to fully characterize a fab to enable DFM is huge. We need to spend all of our R&D dollars to get that technology built and applied correctly. Our CV test chips are an important component of characterizing and improving yields for over ten 90nm and below processes. Now, we are in a position where this characterization is done once and can be provided to all designers, independent of which design flow they prefer. We'll partner with any of the vendors and take our yield modeling data into their flows.

At the same time we need our EDA partners. If you're going to do DFM, you've got to be in on the creation of the design. Companies might be willing to pay to improve their yield, but they don’t want the extra overhead of an additional step in the design flow. So that’s why we are integrating our technology for design engineers – pDfx – into SP&R tools. It’s not about price; it’s about their time. They need to optimize for yield along with timing, area, routability, etc. So by partnering with the major SP&R vendors, we can provide a better solution to the designers than what any company can provide on its own.

We've got relationships now with many of the major EDA vendors. I think the three major vendors have all been receptive at the technical level–it just makes sense. Our pDfx capability has already been released by Magma. We’re not here to pick sides. We are agnostic and we have told them all that. We need to work with all the major flows. It’s probably not as hard for us to partner as it is for other EDA companies because we don’t compete with our partners.

Moreover, EDA vendors have a need for independent yield simulation. They are all spending a lot of money in R&D for routing – printing, CMP-aware, printability-aware. They all need to demonstrate that what they are doing is better. With PDF’s yield simulation there is a way to do this. They show the fabs they need the data and they need us. The fabs pay because at the end of the day they are responsible for yield.

So, by choosing not to compete with the existing EDA vendors and partnering with them in an open way, we are providing a better, more practical solution.

Engineers know how good we are at characterizing silicon, but at times it can be hard for them to get a handle on what we do. We know that the engineering culture is always a little skeptical to something that's new and different. An engineer might say, "It doesn’t work anyway. Besides, we've tried that before."

We don't think the dismissive comments are a big deal. We know that at the gut level, everybody is recognizing that the processes today are very different than they've been in the past and there is a lot more to take into account if you want good product yield.

It's also true that in emerging areas, there's always a lot of hype – things that don't make a lot of sense to folks. We feel the skepticism of the designers is not because they question whether DFM is needed but rather if anyone is providing a real solution. We're offering a practical solution that has a big impact on the quality of the design. Ours is the first productive solution for dealing with yield. It’s not a step after the design flow. It’s integrated into it. And it is based on models rather than on rules. So compared with extended design rules and back end fixes, it is far more effective. We think that anybody – even a contrarian – can look at our products and services and know we're offering a real solution to a real problem.

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Editor's Note – This is the third in a 4-part series on design issues.

* Episode IV: EDA Dies

* Episode V: WID & D2D

* Episode VI: DFY & The Jedi Knight

* Episode VII: DFM Strikes Back

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March 23, 2005

Peggy Aycinena owns and operates EDA Confidential. She can be reached at peggy@aycinena.com

Copyright (c) 2005, Peggy Aycinena. All rights reserved.